[paper] Abstraction NBTI model

Stephan Adolf and Wolfgang Nebel

Abstraction NBTI model

it - Information Technology, Sep. 2021

DOI: 10.1515/itit-2021-0005

Abstract: Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus, one is interested in predicting this effect during design time. In this work, an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently, the conversion into estimated threshold voltage damages is a very time-consuming process.

Fig: Trap in the gate oxide of a PMOS transistor

Acknowledgement: The author thanks Kim Grüttner for proofreading the manuscript of the paper. This research is funded by the German Research Foundation through the Research Training Group “SCARE: System Correctness under Adverse Conditions” (DFG-GRK 1765/2), https://www.uni-oldenburg.de/en/scare/. The simulations were partly performed on the HPC Cluster CARL at the University of Oldenburg (Germany), funded by the DFG through its Major Research Instrumentation Program (INST 184/157-1 FUGG) and the Ministry of

Science and Culture (MWK) of the Lower Saxony State.

[paper] BioDynaMo: a modular platform for high-performance agent-based simulation

Lukas Breitwieser^1,2, Ahmad Hesam^1,3, Jean de Montigny¹, Vasileios Vavourakis^4,5, Alexandros Iosif⁴, Jack Jennings⁶, Marcus Kaiser^6,7,8, Marco Manca⁹, Alberto Di Meglio¹, Zaid Al-Ars³, Fons Rademakers¹, Onur Mutlu², Roman Bauer¹⁰

BioDynaMo: a modular platform for high-performance agent-based simulation

Bioinformatics on 21 September 2021

DOI: 10.1093/bioinformatics/btab649/6371176 

  
1 CERN openlab, CERN, European Organization for Nuclear Research, Geneva, Switzerland
2 ETH Zurich, Swiss Federal Institute of Technology in Zurich, Zurich, Switzerland
3 Delft University of Technology, Delft, The Netherlands
4 Department of Mechanical & Manufacturing Engineering, University of Cyprus, Nicosia, Cyprus
5 Department of Medical Physics & Biomedical Engineering, University College London, UK
6 School of Computing, Newcastle University, Newcastle upon Tyne, UK
7 Department of Functional Neurosurgery, Ruijin Hospital, Shanghai Jiao Tong University School of Medicine, Shanghai, China
8 Precision Imaging Beacon, School of Medicine, University of Nottingham, UK
9 SCimPulse Foundation, Geleen, Netherlands
10 Department of Computer Science, University of Surrey, Guildford, UK

Abstract: Agent-based modeling is an indispensable tool for studying complex biological systems. However, existing simulation platforms do not always take full advantage of modern hardware and often have a field-specific software design.

Results: We present a novel simulation platform called BioDynaMo that alleviates both of these problems. BioDynaMo features a modular and high-performance simulation engine. We demonstrate that BioDynaMo can be used to simulate use cases in: neuroscience, oncology, and epidemiology. For each use case we validate our findings with experimental data or an analytical solution. Our performance results show that BioDynaMo performs up to three orders of magnitude faster than the state-of-the-art baselines. This improvement makes it feasible to simulate each use case with one billion agents on a single server, showcasing the potential BioDynaMo has for computational biology research.

Availability: BioDynaMo is an open-source project under the Apache 2.0 license and is available at www.biodynamo.org. Instructions to reproduce the results are available in supplementary information.

Fig: BioDynaMo’s layered architecture. BioDynaMo is predominantly executed on multi-core CPUs, is able to offload computations to the GPU, and supports Linux operating systems. BioDynaMo provides a rich set of low- and high-level features commonly required in agent-based models. On top of these generic features, BioDynaMo offers model building blocks to simplify the development of a simulation. Even if BioDynaMo does not provide the required building blocks, users still benefit from all generic agent-based features (illustrated by the vertical extension of the “Simulation" layer).

Acknowledgments: We want to thank Giovanni De Toni for his work on the BioDynaMo build system. This work was supported by the CERN Knowledge Transfer office [to L.B. and A.H.]; the Israeli Innovation Authority [to A.H.]; the Research Excellence Academy from the Faculty of Medical Science of the Newcastle University [to J.dM.]; the UCY StartUp Grant scheme [to V.V.]; the Medical Research Council of the United Kingdom [MR/N015037/1 to R.B., MR/T004347/1 to M.K.]; the Engineering and Physical Sciences Research Council of the UK [EP/S001433/1 to R.B., NS/A000026/1, EP/N031962/1 to M.K.]; a PhD studentship funded by Newcastle University’s School of Computing [to J.J.]; the Wellcome Trust [102037 to M.K.]; the Guangci Professorship Program of Ruijin Hospital (Shanghai Jiao Tong Univ.) [to M.K.]; and by several donations by SAFARI Research Group’s industrial partners including Huawei, Intel, Microsoft, and VMware [to O.M.]. The authors have declared that no competing interests exist.

[paper] Compact Modeling of pH-Sensitive FETs Based on 2D Semiconductors

Tarek El Grour, Francisco Pasadas, Alberto Medina-Rull, Montassar Najari, Enrique G. Marin, Alejandro Toral-Lopez, Francisco G. Ruiz, Andrés Godoy, David Jiménez and Lassaad El-Mir

Compact Modeling of pH-Sensitive FETs Based on Two-Dimensional Semiconductors

arXiv:2109.06585 [physics.app-ph; submitted on 14 Sep 2021]

DOI: 10.1109/TED.2021.3112407

   

LAPHYMNE Laboratory, Gabes University, Gabes, Tunisia

PEARL Laboratory, Departamento de Electrónica y Tecnología de Computadores, Universidad de Granada, Spain

The Innovation and Entrepreneurship Centre, Jazan University, Jazan, Saudi Arabia.

Departament d’Enginyeria Electrònica, Escola d’Enginyeria, Universitat Autònoma de Barcelona, Spain

Abstract: We present a physics-based circuit-compatible model for pH-sensitive field-effect transistors based on two-dimensional (2D) materials. The electrostatics along the electrolyte-gated 2D-semiconductor stack is treated by solving the Poisson equation including the Site-Binding model and the Gouy-Chapman-Stern approach, while the carrier transport is described by the drift-diffusion theory. The proposed model is provided in an analytical form and then implemented in Verilog-A, making it compatible with standard technology computer-aided design tools employed for circuit simulation. The model is benchmarked against two experimental transition-metal-dichalcogenide (MoS2 and ReS2) based ion sensors, showing excellent agreement when predicting the drain current, threshold voltage shift, and current/voltage sensitivity measurements for different pH concentrations.

Fig: a) Schematic depiction of a 2D-ISFET b) its quivalent capacitive circuit

Acknowledgments: This work is supported in part by the Spanish Government under the projects TEC2017-89955-P, RTI2018-097876-B-C21 and PID2020-116518GB-I00 (MCIU/AEI/FEDER, UE); the FEDER/Junta de Andalucía under project BRNM-375-UGR18; EC under Horizon 2020 projects WASP No. 825213 and GrapheneCore3 No. 881603. E.G. Marin gratefully acknowledges Juan de la Cierva Incorporación IJCI-2017-32297. A. Toral-Lopez acknowledges the FPU program (FPU16/04043). F. Pasadas acknowledges funding from PAIDI 2020 and Andalusian ESF OP 2014-2020 (20804). F. Pasadas and D. Jiménez also acknowledge the partial funding from the ERDF allocated to the Programa Operatiu FEDER de Catalunya 2014-2020, with the support of the Secretaria d’Universitats i Recerca of the Departament d’Empresa i Coneixement of the Generalitat de Catalunya for emerging technology clusters to carry out valorization and transfer of research results. Reference of the GraphCAT project: 001-P-001702.

[paper] EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Robert Ondica and Viera Stopjakova

EKV Model for Bulk-Driven Circuit Design Using g_mb/I_D Method

IEEE AFRICON; 13-15 September 2021; Arusha (TZ)

 
Institute of Electronics and Photonics; Faculty of Electrical Engineering and Information Technology; Slovak University of Technology; Bratislava (SK)

Abstract: The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measured and extracted small-signal parameters of standalone transistor samples fabricated in 130 nm CMOS technology and the simulation results obtained using the proposed bulk-driven EKV v2.63 model and foundry-provided BSIM model v3.3. The transistor samples were analyzed with power supply of VDD = 0.4 V The paper also discusses the implementation of 3D graphs as a result of introducing another degree of freedom into the essential MOS transistor characteristics, while maintaining the ease of using the design hand-calculation with the original gm/ID approach.

Fig: Bulk-Driven TEF vs Inversion Coefficient – g_mb/I_D

Acknowledgment: This work has been supported in part by the Slovak Research and Development Agency under grant APVV 19-0392, the Ministry of Education, Science, Research and Sport of the Slovak Republic under grants VEGA 1/0731/20 and VEGA 1/0760/21, and ECSEL JU under project PROGRESSUS (Agr. No. 876868)

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Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

Francisco J. García-Sánchez, Life Senior Member, IEEE,

and Adelmo Ortiz-Conde, Senior Member, IEEE

IEEE TED Aug 9. 2021

DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela

Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.

Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of V_GB versus ID_sat (lines) comes from denormalization and the explicit ID_sat versus V_GB (symbols) comes from denormalization of the proposed explicit expressions

IFS2021-MT Registration Now Open

IFS2021-MT Registration Now Open

Will the current shortages continue through 2022?  Get the answer to this and other key questions at IFS2021-MT, Future Horizons' Mid-Term Industry Webinar:
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Our proven methodology, based on our analyses of the industry ecosystem and our interpretation of how these interact, is based on our 55 plus years of direct industry experience, longer than any other analyst and most industry execs. We are also not afraid to stick our necks out and go against the comsensus tide to ensure you get the right information, backed up by data and sound analytical process. As a result, our industry forecasts have consistently proved accurate and insightful, second to no-one. and this event will be no exception.

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[mos-ak] [open registration] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

The MOS-AK/Grenoble Workshop Program is available online:
https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar; use the online form/link below to register:

https://forms.gle/neAwxTczP9PVE7uU6

Registered MOS-AK/Grenoble participants will receive an online access link on SEPT.3 before the main event;

any related enquiries can be sent to register@mos-ak.org

-- W.Grabinski; MOS-AK (EU)

WG240821

[book] Fully Depleted SOI

Sorin Cristoloveanu; Fully Depleted Silicon-On-Insulator:

Nanodevices, Mechanisms and Characterization
2021 Elsevier B.V. 

ISBN: 978-0-12-819643-4

Fully Depleted Silicon-On-Insulator provides an in-depth presentation of the fundamental and pragmatic concepts of this increasingly important technology.

There are two main technologies in the marketplace of advanced CMOS circuits: FinFETs and fully depleted silicon-on-insulators (FD-SOI). The latter is unchallenged in the field of low-power, high-frequency, and Internet-of-Things (IoT) circuits. The topic is very timely at research and development levels. Compared to existing books on SOI materials and devices, this book covers exhaustively the FD-SOI domain. 

Key Features:

• Written by a top expert in the silicon-on-insulator community and IEEE Andrew Grove 2017 award recipient
• Comprehensively addresses the technology aspects, operation mechanisms and electrical characterization techniques for FD-SOI devices
• Discusses FD-SOI’s most promising device structures for memory, sensing and emerging applications

Table of Contents:

Front Matter

Preface

Part I: Technology

Chapter 1 - FD-SOI technology pp. 3-37

Part II: Mechanisms in FD-SOI MOSFET

Chapter 2 - Coupling effects pp. 41-70

Chapter 3 - Scaling effects pp. 71-114

Chapter 4 - Floating-body effects pp. 115-138

Part III: Electrical characterization techniques for FD-SOI structures

Chapter 5 - The pseudo-MOSFET pp. 141-177

Chapter 6 - Diode-based characterization methods pp. 179-200

Chapter 7 - Characterization methods for FD-SOI MOSFET pp. 201-238

Part IV: Innovative FD-SOI devices

Chapter 8 - Electrostatic doping and related devices pp. 241-265

Chapter 9 - Band-modulation devices pp. 267-298

Chapter 10 - Emerging devices pp. 299-348

FD-SOI teasers pp. 349-352

Index

[mos-ak] Re: [Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
18th MOS-AK ESSDERC/ESSCIRC Workshop
Grenoble (online), Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online:
https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar; use the online form/link below to register:
https://forms.gle/neAwxTczP9PVE7uU6

Registered MOS-AK/Grenoble participants will receive an online access link on SEPT.3 before the main event;
any related enquiries can be sent to register@mos-ak.org

-- W.Grabinski; MOS-AK (EU)

WG180821

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[mos-ak] Re: [Final Program] 5th Sino MOS-AK Workshop Xi'an (hybrid/online) August 11-13, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th Sino MOS-AK Workshop Xian

August 11-13, 2021

The Xidian University Host and local MOS-AK Organizers are providing following login information

Meeting link for 12th-13th. August  

https://meeting.tencent.com/s/HSfS9ZbTFZra

(no need to have password and can discuss/Q&A )

Meeting ID：357 1681 8021

Live channel: https://meeting.tencent.com/l/OWgMlNVDPe7E 

(can not discuss  just listen, password is 812813)

If anyone wants to attend MOS-AK Xian Training Course on 11th. August. 

https://meeting.tencent.com/s/xX8DrFfcVkWl

Meeting ID：716 195 769

Live channel: https://meeting.tencent.com/l/xPZezoHpYMwT 

(cannot discuss, just listen, password is 210811)

Please also note that all presentation timing listed in the workshop program  

https://www.mos-ak.org/xian_2021/

is in local Chinese time zone (GMT+8)

-- Min Zhang; XMOD Technologies (CN) 

-- W.Grabinski; MOS-AK (EU)

-- 

Enabling Compact Modeling R&D Exchange

www.mos-ak.org

--

WG080921

On Monday, July 5, 2021 at 5:30:55 PM UTC+2 Wladek Grabinski wrote:

Arbeitskreis Modellierung von Systemen und Parameterextraktion 

Modeling of Systems and Parameter Extraction Working Group

5th Sino MOS-AK Workshop Xian

August 11-13, 2021

Together with local Xidian University Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to the 5th Sino MOS-AK Workshop Xian workshop which will be Virtual/Online event. Scheduled, MOS-AK/Xian workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/xian_2021/

Venue: Hybrid event at Xidian University <xidian.edu.cn>

会议场所：西安电子科技大学北校区阶梯教学楼112报告厅, 

西安市雁塔区太白南路2号西安电子科技大学（北校区）

No.2, South Taibai Road, Xian Dianzi University, Xi'an, 710071

Online Registration is open

Workshop Secretary: Meng Zhang Mobile:13619295980

any related enquiries can be sent to regist...@mos-ak.org

Post-workshop publications, selected, the best papers will be selected and recommended for further publication in the renowned journal such as Weily's International Journal of Microwave and Optical Technology Letters special issue.

-- Min Zhang; XMOD Technologies (CN) 

-- W.Grabinski; MOS-AK (EU)

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG050721

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[paper] Systematic approach for IG-FinFET amplifier design using gm/Id method

Alireza Hassanzadeh and Sajad Hadidi

Systematic approach for IG-FinFET amplifier design using gm/Id method

Analog Integrated Circuits and Signal Processing (2021)

https://doi.org/10.1007/s10470-021-01917-9

EE Department, Shahid Beheshti University, Tehran, Iran

Abstract: In this paper, a systematic approach has been used to apply gm/Id method for the design of Independent Gate (IG) FinFET amplifiers. The design of high-performance amplifiers using gm/Id method has been successfully applied to nanometer devices. IG-FinFETs have been widely used in digital circuit implementations. However, the application of IG-FinFETs in analog circuits is limited and brings many advantages including low power, low voltage operation of transistors. Independent gates of FinFET can receive different voltages that facilitate low voltage operation of the circuit. Simulation-based gm/Id method has been applied to IG-FinFET transistors and a systematic methodology has been developed for the design of IG-FinFET amplifiers. The Berkeley BSIM-IMG 55 nm technology parameters have been used for HSPICE simulations. The designed amplifier has a DC gain of about 45 dB while consuming 6.5 µW from a single 1 V power supply.

Fig: gm/Id vs. normalized Id(Vbg)

[paper] Compact Model for Electrostatics of III–V GAA Transistors

Mohit D. Ganeriwala, Francisco G. Ruiz*, Enrique G. Marin* and Nihar R. Mohapatra

A unified compact model for electrostatics of III–V GAA transistors with different geometries

Journal of Computational Electronics (2021)

Published: 07 August 2021

DOI: 10.1007/s10825-021-01751-2

 
Department of Electrical Engineering, Indian Institute of Technology Gandhinagar, Gandhinagar, Gujarat, 382355, India
*Department of Electronics, University of Granada, Granada, Spain

Abstract: In this work, a physics-based unified compact model for III-V GAA FET electrostatics is proposed. The model considers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed first using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unified representation. The efficacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrödinger solver. The proposed model is found to be accurate for GAA FETs with different geometries, dimensions and channel materials and computationally efficient.

Fig: III–V GAA transistors with different geometries

Acknowledgements: This work is supported by the Visvesvaraya PhD scheme by MeitY, Gover nment of India Enrique G. Marin gratefully acknowledges Juan de la Cierva Incorporation IJCI-2017-32297 (MINECO/AEI).

#Tata Group Looking To Enter #Semiconductor #Manufacturing

#Tata Group Looking To Enter #Semiconductor #Manufacturing https://t.co/wRzBoxdPrf #semi https://t.co/B74v7K54NK

— Wladek Grabinski (@wladek60) Aug 9, 2021

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August 10, 2021 at 12:19AM
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[paper] #32bit microprocessor on #plastic

[paper] Z. Yu, “A #32bit microprocessor on #plastic,” Nature Electronics, Aug. 2021 https://t.co/K9hOZx05k6 #semi https://t.co/tO7TGBh5Gw

— Wladek Grabinski (@wladek60) Aug 9, 2021

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August 09, 2021 at 03:16PM
via IFTTT

Foxconn to Acquire Macronix's #6inch #wideband gap semiconductors #Wafer #Fab [EE Times Asia https://t.co/4fohHYy2za] #semi https://t.co/8St4KWqdnZ

Foxconn to Acquire Macronix's #6inch #wideband gap semiconductors #Wafer #Fab [EE Times Asia https://t.co/4fohHYy2za] #semi https://t.co/8St4KWqdnZ

— Wladek Grabinski (@wladek60) Aug 9, 2021

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[paper] Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

Hocheon Yoo and Chang-Hyun Kim, Senior Member, IEEE 

Unified Compact Model for Thin-Film Heterojunction Anti-Ambipolar Transistors

IEEE Electron Device Letters (2021)

DOI 10.1109/LED.2021.3102219

* Department of Electronic Engineering, Gachon University, Seongnam 13120, South Korea

Abstract: This letter proposes an advanced compact model for anti-ambipolar transistors based on a lateral thin-film material heterojunction. The modeling idea focuses on an analytical description of component currents and bridging methods necessary for controllable transition between operation regimes. The model is validated by experimental data, and predictive simulations are carried out to demonstrate its applicabilities.

Fig: (a) Cross-sectional device structure of an AAT and its energy diagram at a negative VD (G: gate, S: source, and D: drain). (b) Conceptual illustration of the geometrical origin of the anti-ambipolar switching behavior.

Acknowledgements: This work was supported by the National Research Foundation of Korea (NRF) grants funded by the Korean government (MSIT) (NRF-2019 R1C1C1003356, NRF2020 R1A2C1101647).

[paper] Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries

Mike Brinson and Felix Salfelder 

Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries 

In 28th MIXDES (2021), pp. 35-40 

DOI: 10.23919/MIXDES52406.2021.9497545 

Abstract—The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated.

Fig: A Qucs-S/Xyce test bench for simulating and displaying BJT Ic/V ce

output characteristics with 1µA ≤ Ib ≤ 10µA in 1µA steps.

[paper] Model for Ultra-Scaled MoS2 MOSFET

Weiran Cai, Wenrui Lan, Zichao Ma*, Lining Zhang, Mansun Chan*

A Full-region Model for Ultra-Scaled MoS2 MOSFET Covering Direct Source-Drain Tunneling 

9th International Symposium on Next Generation Electronics (ISNE), 2021, pp. 1-3,

DOI: 10.1109/ISNE48910.2021.9493621

College of Electronic and Information Technology, Shenzhen University, Shenzhen, China

* Hong Kong University of Science and Technology, Hong Kong, China

Abstract: A full-region model for ultra-scaled monolayer MoS2 MOSFETs is reported in this work. The electrostatic potential in the scaled transistor structure is analyzed based on a first-principle verified potential model. A continuous full region current model is then developed to capture the short channel effects. Based on the potential model, the barrier height and width for direct source-drain tunneling are obtained. The direct tunneling module reproduces the essential physics observed from numerical device simulations. After integration with the thermionic emission model, the full-region current model is implemented into a SPICE simulator and the model convergence is verified by simulating typical circuits.

A drift-diffusion current model of the full region is straightforwardly derived with Taylor expansions of a Si model or from the Pao-Sah integral. It resembles the EKV current model and allows similar expressions of small signal models:

Fig: The impact of SCEs on devices of different channel length is showed in (a) Ids–Vg and (b) Ids–Vd characteristics predicted by the model covering SCEs. When channel length becomes smaller, SCEs becomes more serious. 

Acknowledgement: This work is supported in part by the Natural Science Foundation of China under Grant 61704144, the Shenzhen Science and Technology Project under JCYJ20180305125340386, the General Research Fund (GRF) from Research Grant Council (RGC) of Hong Kong under Grant 16206219

Please, no #Moore: '#Law' that defined how chips have been made for decades has run itself into a cul-de-sac

Please, no #Moore: '#Law' that defined how chips have been made for decades has run itself into a cul-de-sac https://t.co/O2hLg7hPWb #semi https://t.co/BbQV8R20tS

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[paper] Modeling and investigation of SET Inverter Circuit

C. Shyamala, V. Kalpana

Modeling and investigation of SET Inverter Circuit

International Journal of Innovative Research in Engineering 25 

Vol. 2, Issue 3 (May-June 2021), pp: 25-28 

ISSN No: 2582-8746; www.theijire.com

* Department of EEE, RV College of Engineering, VTU University, Karnataka. India.

Abstract: This paper presents an analytical model Inverter based on the theory of single electron transistor(SET). The proposed design is very flexible such that it can be used for single gate, multi-gate, symmetric, asymmetric devices and most importantly it can also consider the effect of background charge. It can also be used for large voltage range of drain-source voltage irrespective of the bias conditions. The proposed design has been simulated with SPICE and the characteristics produced by the proposed design have been verified against Monte Carlo simulator SIMON [1].

Fig: Schematic diagram of single electron inverter

Reference:

[1] SIMON - A single electron device and circuit simulator

https://www.lybrary.com/simon/examples.html

What is #TinyML, and why does it matter?

What is #TinyML, and why does it matter? https://t.co/6zq9Ar1ZU5 #semi https://t.co/Xqth7bzMYH

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Russian Forum "Microelectronics 2021

Russian Forum "Microelectronics 2021"

Preliminary Program

September 7-9, Moscow, JSC "ENPO SPELS"

The Scientific Conference Pre-session (based on Section 5)
Moderators: Bobkov S.G. IPPM RAS Nikiforov A.Yu. CEPE NRNU MEPhI

Section 1: Navigational communication VLSI and modules
Moderators: I. L. Korneev JSC NIIMA Progress Steshenko VB JSC "RKS"

Section 2: High performance computing systems
Moderators: Khrenov G.Yu. JSC "Baikal Electronics" Bychkov I.N. JSC "MCST"

Section 3: Information control and radio engineering systems
Moderators: Pereverzev A.L. NRU MIET Yakunin A.N. NRU MIET P.M. Eremeev JSC "Research Institute" Submicron "

Section 4: Technologies and components of micro- and nanoelectronics
Moderators: Shelepin N.A. JSC "NIIME" Putrya M.G. NRU MIET Egorov A.Yu. LLC "Connector Optics"

Section 5: Micro- and optoelectronic products for general and special purposes
Moderators: Bobkov S.G. IPPM RAS Nikiforov A.Yu. CEPE NRNU MEPhI

Section 6: Design and simulation systems for electronic components and systems
Moderators: Rusakov S.G. Corresponding member of RAS Zavalin Yu.V. JSC "NIIMA" Progress "

Section 7: Microwave integrated circuits and modules
Moderators: Minnebaev V.M. JSC "NPP" Pulsar " P.V. Panasenko JSC "NIIME" Mukhin I.I. JSC "NIIMA" Progress "

Section 8: Microsystems. Sensors and Actuators
Moderators: Timoshenkov S.P. NRU MIET Dyuzhev N.A. STC NMST

Section 9: Special technological equipment
Moderators: Biryukov M.G. JSC NIITM Alekseev A.N. CJSC "NTO"

Section 10: Neuromorphic computing. Artificial intelligence
Moderators: Kryzhanovsky B.V. FGU FSC NIISI RAS Tel'minov O.A. JSC "NIIME" Gornev E.S. JSC "NIIME"

Section 11: Quantum Technologies - Quantum Sensors
Moderators: Gorbatsevich A.A. FIAN, NRU MIET Bogdanov Yu.I. FTIAN, NRU MIET S.P. Kulik Moscow State University named after M.V. Lomonosov

IJHSES Special Issue Volume 29, Issue 01n04, 2020

IJHSES Special Issue on Nanotechnology for Electronics, Biosensors, 

Additive Manufacturing and Emerging Systems Applications 

Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Volume 29, Issue 01n04 (March, June, September, December 2020) 

This Special issue on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications comprises peer reviewed articles selected from the 29th annual symposium of the Connecticut Microelectronics and Optoelectronics Consortium (CMOC), virtually held on October 2, 2020 and hosted by Information Technology Staff, University of Connecticut (Storrs Campus).

Organized by a team of seven academic institutions and about eighteen companies across the United States, this symposium sign-posted the progress and development of state-of-arts research in high-speed electronics over the last 30 years.

Articles include keynote presentations by three experts in their field:

• Dr. H. Lee, Electronic and IR Sensing in Forensics, U. New Haven, and Henry Lee Center for Forensic Research
• Dr. E. Fossum, Quanta Image Sensor, Dartmouth College
• Dr. J. Chow, Quantum Computing, IBM Thomas J. Watson, Research Center

The papers presented span from novel materials and devices, biosensors and bio- nano- systems, artificial intelligence, robotics and emerging technologies, to applications in each of these fields, Systems for implementing data with security tokens; single chemical sensor for multi-analyte mixture detection; RF energy harvesters; additively manufactured RF devices for 5G, IoT, RFID and smart city applications are also included in this special issue on high performance materials for implementing high-speed electronic systems.

In the area of material synthesis, modeling of dislocations behavior in various II-VI and III-V heterostructures and their gettering at sidewall bringing novel approaches are also featured

Coming hot on the heels, are recent developments on high performance devices include equivalent circuits models at room and 4.2K; quantum dot nonvolatile memories, 3D- confined quantum dot channel (QDC) and spatial wavefunction switched (SWS) FETs for high-speed multi-bit logic and novel system applications.

In summary, the papers selected for this special issue cover various aspects of h performance materials and emerging devices for implementing high-speed electronic systems. We would like to take this opportunity to express our thanks to the authors, participants, and reviewers for their contributions and active participation, networking, and knowledge sharing on a variety of research areas.

#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design

#Efabless & #OpenROAD Advance Commercial #OpenSource #Chip #Design https://t.co/h6mSqWzJHh #semi https://t.co/u3TDibKq9I

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[special issue] on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems

Guest editorial for the special issue 

on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems: 

Connecting technologies to applications

Valeria Vadalà, Giovanni Crupi

First published: 27 July 2021; DOI: 10.1002/jnm.2940

The μmWave and mmWave frequencies have been historically associated with niche applications such as space and defense; however, in the last years wireless communications have caused a rapid growth of interest in mass-market applications, representing the enabling technology for the new Information Age where all “things” need to be connected. Internet of Things, Industry 4.0, and Smart Cities are portraits of this concept in different contexts, from entertainment to healthcare applications. This exciting scenario triggers the continuous increase of performance requirements such as huge bandwidth, low latency, and very high data rate of emerging wireless technologies (i.e., 5G and 6G). This special issue takes a step forward in the different branches of knowledge related to μmWave and mmWave devices, circuits, and systems, oriented to wireless applications from the device level up to the application level. From the reader's point of view, the goal is to drive to a comprehensive overview on salient aspects of these topics and to provide interesting hints to overcome the upcoming technological challenges.

REFERENCES:
[1] Cao K-J, Zhang A, Gao J-J. Sensitivity analysis and uncertainty estimation in small-signal modeling for InP HBT (invited paper). Int J Numer Model El. 2021; 34(5): 2851. DOI: 10.1002/jnm.2851
[2] Tang X, Yang T, Jia Y, Xu Y. FW-EM-based approach for scalable small-signal modeling of GaN HEMT with consideration of temperature-dependent resistances. Int J Numer Model El. 2021; 34(5):e2882. DOI: 10.1002/jnm.2882
[3] King JB. Efficient energy-conservative dispersive transistor modelling using discrete-time convolution and artificial neural networks. Int J Numer Model El. 2021; 34(5): 2894. DOI: 10.1002/jnm.2894
[4] Li Y, Mao S, Fu Y, et al. A scalable electrothermal model using a three-dimensional thermal analysis model for GaN-on-diamond high-electron-mobility transistors. Int J Numer Model El. 2021; 34(5):e2875. DOI: 10.1002/jnm.2875
[5] Alim MA, Ali MM, Crupi G. Measurement-based analysis of GaAs HEMT technologies: Multilayer D-H pseudomorphic HEMT versus conventional S-H HEMT. Int J Numer Model El. 2021; 34(5):e2873. DOI: 10.1002/jnm.2873
[6] Osmanoglu S, Ozbay E. From model to low noise amplifier monolithic microwave integrated circuit: 0.03–2.6 GHz plastic quad-flat no-leads packaged Gallium-Nitride low noise amplifier monolithic microwave integrated circuit. Int J Numer Model El. 2021; 34(5):e2859. DOI: 10.1002/jnm.2859
[7] Piacibello A, Costanzo F, Giofré R, et al. Evaluation of a stacked-FET cell for high-frequency applications (invited paper). Int J Numer Model El. 2021; 34(5):e2881. DOI: 10.1002/jnm.2881
[8] Wu M, Cai J, King J, Chen S, Su J, Cao W. Design of a multi-octave power amplifier using broadband load-pull X-parameters. Int J Numer Model El. 2021; 34(5):e2878. DOI: 10.1002/jnm.2878
[9] Abdulbari AA, Abdul Rahim SK, Soh PJ, Dahri MH, Eteng AA, Zeain MY. A review of hybrid couplers: State-of-the-art, applications, design issues and challenges. Int J Numer Model El. 2021; 34(5):e2919. DOI: 10.1002/jnm.2919
[10] Piltyay S, Bulashenko A, Sushko O, Bulashenko O, Demchenko I. Analytical modeling and optimization of new Ku-band tunable square waveguide iris-post polarizer. Int J Numer Model El. 2021; 34(5):e2890. DOI: 10.1002/jnm.2890
[11] Qas Elias BB, Soh PJ, Abdullah Al-Hadi A, Vandenbosch GAE. Design of a compact, wideband, and flexible rhombic antenna using CMA for WBAN/WLAN and 5G applications. Int J Numer Model El. 2020; 34(5):e2841. DOI: 10.1002/jnm.2841
[12] Zhang X, Cunjun R, Dai J, Ding Y, Ullah S, Kosar Fahad A. Design of a reconfigurable antenna based on graphene for terahertz communication. Int J Numer Model El. 2021; 34(5):e2911. DOI: 10.1002/jnm.2911
[13] Gatte MT, Soh PJ, Kadhim RA, Abd HJ, Ahmad RB. Modeling and performance evaluation of antennas coated using monolayer graphene in the millimeter and sub-millimeter wave bands. Int J Numer Model. 2021; 34(5):e2929. DOI: 10.1002/jnm.2929
[14] Xing C, Qi F, Liu Z, Wang Y, Guo S. Terahertz compressive imaging: understanding and improvement by a better strategy for data selection. Int J Numer Model El. 2021; 34(5):e2863. DOI: 10.1002/jnm.2863

#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers

#STM Manufactures First #200mm Silicon Carbide #SiC #Wafers [ST News https://t.co/BTdQoaGlnA] #semi https://t.co/cgX8Jxqtsy

— Wladek Grabinski (@wladek60) Jul 27, 2021

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[paper] Above Vth Model for SC DG MOSFETs

David Chuyang Hong; Yuan Taur

An Above Threshold Model for Short-Channel DG MOSFETs

in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021

DOI: 10.1109/TED.2021.3092310.

*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA

Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.

Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation

Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.

[paper] VNWFET Including Tied Compact Model

Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1, 

and Abhishek Kumar3

3D Logic Cells Design and Results Based on Vertical NWFET Technology 

Including Tied Compact Model

In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.

DOI: 10.1007/978-3-030-81641-4_14

1 Lyon Institute of Nanotechnology, University of Lyon, France
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan

Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.

Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)

Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).

[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[Final Program] 18th MOS-AK ESSDERC/ESSCIRC Workshop Grenoble; Sept. 6, 2021

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

18th MOS-AK ESSDERC/ESSCIRC Workshop

Grenoble, Sept. 6, 2021

Together with local Host and MOS-AK Organizers as well as all the Extended MOS-AK TPC Committee, we invite you to the consecutive 18th MOS-AK ESSDERC/ESSCIRC Workshop. Scheduled Virtual/Online MOS-AK event aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors.

The MOS-AK Workshop Program is available online: 

https://www.mos-ak.org/grenoble_2021/

Venue: Online MOS-AK Webinar;

use the online form/link below to register.

Online Registration is open

any related enquiries can be sent to registration@mos-ak.org

Post-workshop publications, selected, the best papers will be recommended for further publication in the special compact/SPICE modeling issue of the Solid State Electronics.

-- W.Grabinski; MOS-AK (EU)

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Enabling Compact Modeling R&D Exchange

www.mos-ak.org

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WG210721

[paper] Compact Analytical Modeling of FD Dual Material DG MOSFET

Shahana Akter1, Md. Mirazur Rahman1 and Md. Arif Abdulla Samy2

Compact Analytical Modeling of Surface Potential 

of a fully depleted Dual Material Double Gate MOSFET

Materials Mechatronics and Systems Engineering 2021, 1, 1. https://citescript.com/Journals/index.php/mmsj/

1 Department of EEE, Primeasia University
2 ATLAS Experiment, CERN

Abstract: Scaling transistors to gain speed while reducing capacitance and cost, is a key topic of today’s semiconductor industry, which is widely affected by Short-Channel Effects, the phenomenon that reduces efficiency. To dominate that unwanted effect, a 2-dimensional electrostatic potential modeling of the fully depleted channel, with high-k based dual material double gate (DMDG) MOSFET, has been developed in this paper. The expression for the electrostatic potential of DMDG has beendeveloped using 2-D Poisson’s equation with appropriate device boundary conditions. The device performance has been analyzed with the variation in device parameters, such as channel length, channel thickness, oxide thickness, and other key parameters. For authenticating, results have also been compared with state-of-the-art published results. This research was successful to exhibit that the proposed model could overcome Drain-induced Barrier Lowering, enhancing mobility carrier resulting to optimize short channel effect, which can bring a revolutionary change in transistor industry as well as in low power VLSI applications.

Fig: Device structure for the 2D double gate MOSFET

Acknowledgment: Authors would like to thank Professor Dr. Quazi Deen Mohd Khosru for his guidance in every step of this research. Without his valuable and persistent help, it would not be possible to conclude this project. The project has no external funding.