Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1,
and Abhishek Kumar3
3D Logic Cells Design and Results Based on Vertical NWFET Technology
Including Tied Compact Model
In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.
DOI: 10.1007/978-3-030-81641-4_14
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan
Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.
Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)
Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).
