Wednesday, October 31, 2018

IEEE LM Workshop on History of microchips in Switzerland

The Swiss IEEE LM has organized local Workshop on "History of microchips in Switzerland". This workshop is a follow-on of the IEEE Milestone celebration of Feb.22, 2018 in Neuchatel and was held in the same building of the Uni. Neuchatel at Rue A.L. Breguet 2, room 3416. The event was organized and chaired by Hugo Wyss, IEEE LM, with following agenda:

Session 1 (2:30 - 3:50pm): From Germanium to Silicon, 1955 - 1970
Speakers:
  • W. Grabinski (EDS)
  • M. Lamoth (Favag)
  • J.-D. Chauvy (CEH)
  • H. Wyss (IEEE LM)
  • E. Vittoz (early CEH period)
Coffee break at Cafeteria, first floor, 3:55 - 4:10 pm

Session 2 (4:15 - 5:50pm): From Bipolar to CMOS, 1970 - 1980
Speakers:
  • H. Wyss  (IEEE LM)
  • N. de Rooji (IMT)
  • P.-R. Beljean (AMSTN)
  • others (open discussion)
The workshop was closed with a standing apero at Cafeteria.

The IEEE Milestone for the developments of Swiss quartz watch
(Uni. Neuchatel at Rue A.L. Breguet 2)

J.-D. Chauvy talk during Session 1: From Germanium to Silicon, 1955 - 1970;
chaired by H. Wyss, IEEE LM (sitting at very right)

An 1" wafer with one of the very first Swiss integrated circuits






Qucs-S 0.0.21 released

Qucs-S 0.0.21 has been released by Vadim Kuznetsov. It's a special Qucs version that allows to run Ngspice/Xyce simulators from the Qucs GUI. This release contains mostly bugfixes and small improvements. Here the short changelog:
  1. Redesign of Parameter Sweep. Enabled sweep for log and list parameter type.
  2. Fixed Voltage probe bug
  3. Fixed missing phase of AC source
  4. Added SMD resistor model
See release notes and download links here:
https://github.com/ra3xdh/qucs_s/releases/tag/0.0.21
Linux tarball and DEB/RPM packages are available. Windows installer will be added later.
See also https://ra3xdh.github.io/ for documentation and more info about Qucs-S.

Follow Qucs-devel mailing list

Qucs-devel@lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/qucs-devel

Friday, October 26, 2018

The #Digitization Of #China And Opportunities For #OpenSource Collaboration https://t.co/RNgs4kYilz


from Twitter https://twitter.com/wladek60

October 26, 2018 at 01:01PM
via IFTTT

Monday, October 15, 2018

FOSDEM 2019 CAD and Open Hardware Devroom Call for Participation

This is the call for participation in the FOSDEM 2019 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Sunday 3 February 2019 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
  • Field solvers such as openEMS
  • Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD and SolveSpace
  • Open Hardware projects such as the Teres laptop and the lowRISC SoC
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017, which enlarged its scope in the CAD and Open
Hardware devroom in 2018.

Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM19 
before 1 December 2018.

Important dates
8 December 2018: deadline for submission of proposals
15 December 2018: announcement of final schedule
3 February 2019: devroom day

Monday, October 8, 2018

Michael Shur winning the 2018 IEEE EDS J.J. Ebers Award


Congratulations to Prof. Michael Shur for winning the 2018 IEEE EDS J.J. Ebers Award "For pioneering the concept of ballistic transport in nanoscale semiconductor devices"

Recent Winners of the J.J. Ebers Award
2017 - Kang L. Wang "For contributions and leadership in strained SiGe and magnetic memory technologies"
2016 - Jaroslav Hynecek "For the pioneering work and advancement of CCD and CMOS image sensor technologies"
2015 - Jack Yuan-Chen Sun "For sustained leadership and technical contributions to energy efficient foundry CMOS technologies"
2014 - Joachim N. Burghartz "For contributions to integrated spiral inductors for wireless communication ICs and ultra-thin silicon devices for emerging flexible electronics"
2013 - Nobukazu Teranishi "For development of the Pinned Photodiode concept widely used in Image Sensors”
2012 - Yuan Taur "For contributions to the advancement of several generations of CMOS process technologies"
2011 - Stuart Ross Wenham “For technical contributions and successful commercialization of high efficiency solar cells”
2010 - Mark E. Law “For contributions to widely used silicon integrated circuit process modeling”

Friday, October 5, 2018

1st Latin American Electron Devices Conference in Colombia

The 1st Latin American Electron Devices Conference (LAEDC 2019) will be held from February 24 to 27 2019 in Armenia, Colombia.

It will take place in parallel with the 2019 Latin American Symposium on Circuits and Systems (2019 LASCAS), also from February 24 to 27 2019 in Armenia, Colombia.


LAEDC is intended to be a top international conference about electron devices. It is thought to become the Latin American equivalent to ESSDERC in Europe. As ESSDERC is held in parallel with a solid state circuits conference, ESSDERC, LAEDC will be organized in combination with LASCAS.

LAEDC will also be the Latin American equivalent to the Electron Devices Technology and Manufacturing Conference (EDTM), organized every year in Asia.

Proceedings will be published by IEEE and will be available on IEEE Xplore.

There is a negotiation to publish a Special Issue in a top journal  containing extended versions of selected papers presented in LAEDC.

One of the topics of LAEDC is Modeling and Simulation. All electron devices can be targeted.

The deadline for paper submission is October 15 2018.

Armenia City is the capital of the department of Quindio. It is located in the Colombian region known as the coffee triangle. Since 2011, this region is recognized by the UNESCO as a world cultural heritage due to its exceptional landscapes that are the mixture of natural beautifulness and cultural traditions around the coffee growing. Different theme parks related to cultural and agricultural traditions are also located in the department of Quindio, which turns out the LAEDC an opportunity not only for academic exchange but also for knowing and enjoying the traditions around the coffee growing.

As Publication Chair, I strongly encourage researchers in device modeling to submit papers to the  1st Latin American Electron Devices Conference!

New offer of a Ph D scholarship about Device modeling in Tarragona (Spain)

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for three years.  The position will start between February and April 2019.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of devices for flexible and printed electronics, including sensing applications, in particular organic and oxide TFTs.
The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices. We are currently coordinating a European Union funded project (DOMINO) about those topics.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible) with passport number
2) Copy of their diploma
3) copy of their passport
4) Academic certificate (translated into English by an official translator) including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:
Prof. Benjamin IñiguezDepartment of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26

43007
Tarragona (Spain)

 Email: benjamin.iniguez@gmail.com 

Tel: +34977558521 Fax:+34977559610

Deadline for documents submission: October 20 2018.
 
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information.
Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

Thursday, October 4, 2018

[mos-ak] [2nd Announcement and C4P] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
11th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 5, 2018

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 11th International MOS-AK Workshop which will be organized at Silvaco HQ on Dev. 5, 2018 (co-located with the IEDM and CMC Meetings)

Planned 11th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2018
  • 2nd Announcement - Nov. 2018
  • Final Workshop Program - Oct. 2018
  • MOS-AK Workshop: Dec. 5, 2018
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)

Postworkshop IJHSES Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG041018

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Monday, October 1, 2018

[mos-ak] [2nd Announcement and Call for Papers] 2nd MOS-AK/India Conference, IIT Hyderabad, Feb. 25-27, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
2nd MOS-AK/India Conference
IIT Hyderabad
Feb. 25-27, 2019 

Together with the MOS-AK/India Steering Committee and executive local organizers at the IIT Hyderabad as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd MOS-AK/India Conference at IIT Hyderabad between Feb. 25-27, 2019 

Venue
Indian Institute of Technology (IIT) Hyderabad
Hyderabad, Kandi
Telangana State, India

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

Compact Modeling Track  
Circuits and Systems Track  
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • FOSS TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT and SOI-based memory cells
  • Organic, Bio/Med devices/technology modeling
  • Microwave, RF device modeling, HV/Power device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D reliability/ageing, DFY, DFT 
  • Foundry/Fabless Interface Strategies
  • Analog Circuits
  • Biomedical and Life-Science Circuits, Systems and Applications
  • Circuits and Systems for Communication
  • Emerging Technologies for Circuits and Systems
  • HP/HV IC Designs
  • Memory Circuits and Systems
  • Mixed Signal Circuits
  • RF/mm-Wave IC Design and Technology
  • Sensory Systems System-on-Chip and CAD
  • Testing Technology
  • VLSI Systems & Applications
  • And any other IC design related topic

Online Abstract Submission (any related enquiries can be sent to secretary.mosak.india@gmail.com)

Original unpublished works in topics related to the following areas (but not limited to) can be submitted for publication. The proceedings of the conference will be submitted to IEEE Explore. Best Paper Award: Gold leaf, Silver leaf and Bronze leaf certificates will be given to best papers.

Highest Ranked papers from regular submission will be invited to extend their paper in the form of a book chapter. All these submission will be published in the form of a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoters of MOS-AK/India 2019 Conference. 
Author Instruction and Registration Details available as a pdf document

Important Dates:
Call for Papers - 1 Sept. 2018
2nd Announcement -  1 Oct. 2018
Paper and Tutorial Submission Deadline - 1 Nov. 2018
Notification of Acceptance - 15 Dec. 2018
Registration and Camera Ready Paper Submission - 10 Jan. 2019
Final Conference Program - 15 Jan. 2019
MOS-AK/India Conference - February 25-27, 2019
Online registration (to be open in Jan. 2019; any related enquiries can be sent secretary.mosak.india@gmail.com)

Extended MOS-AK Committee


WG010118
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