[paper] Above Vth Model for SC DG MOSFETs

David Chuyang Hong; Yuan Taur

An Above Threshold Model for Short-Channel DG MOSFETs

in IEEE TED, vol. 68, no. 8, pp. 3734-3739, Aug. 2021

DOI: 10.1109/TED.2021.3092310.

*Department of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093 USA

Abstract: An above-threshold I–V model is developed for short-channel double-gate (DG) MOSFETs. It is a non-gradual channel approximation (non-GCA) model that takes into account the contribution to carrier density from the encroachment of source–drain bands into the channel. At low-drain bias voltages, the effect appears as a gate-voltage-dependent reduction of channel resistance, with stronger effects at low gate overdrives. At high-drain biases, the intersection of source band encroachment with the gate-controlled channel potential leads to a point of virtual cathode a small distance from the source. By incorporating the depletion of carriers in the source and drain regions into the boundary conditions, the Ids-Vds and Ids-Vgs characteristics generated by the model are shown to be consistent with TCAD simulations.

Figure below shows the schematic of a DG MOSFET (undoped). The device operation is governed by 2-D Poisson’s equation

Fig: Schematic of a DG MOSFET. The parameters assumed are tsi=4nm, ti=2nm, εsi=εi=11.8ε0, with channel length L ranging from 15 to 7nm. The gate work function is 0.28eV below that of intrinsic silicon so Vt=0.247V.