Wednesday, February 28, 2018

[paper] Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

Proceedings of 43rd Annual Conference of the IEEE Industrial Electronics Society
IECON 2017
Lorenzo Ceccarelli, Paula Diaz Reigosa, Amir Sajjad Bahman, Francesco Iannuzzo,
Frede Blaabjerg
Center of Reliable Power Electronics, Department of Energy Technology Aalborg University,
Pontoppidanstræde 101
9220 Aalborg, Denmark 

ABSTRACT: A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules [read more...]

Fig.: SiC MOSFET model structure. 

Sunday, February 25, 2018

Call for papers for a Special Issue of IEEE Transactions on Electron Devices on Compact #Modeling for Circuit... https://t.co/N6U0dXHmu1


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February 25, 2018 at 10:48AM
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Call for papers for a Special Issue of IEEE Transactions on Electron Devices on Compact #Modeling for Circuit Design - IEEE Journals & Magazine https://t.co/MNRwd2XitA


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February 25, 2018 at 10:48AM
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Compact #Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition - IEEE Journals &... https://t.co/xp2Ff5Tlcp


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February 25, 2018 at 12:17AM
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Compact #Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition - IEEE Journals & Magazine https://t.co/yTSpsNriwQ


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February 25, 2018 at 12:17AM
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Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the... https://t.co/RBNC96OpbO


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February 25, 2018 at 12:10AM
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Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the Distributed Nature of Currents - IEEE Journals & Magazine https://t.co/wNNqfPzf0P


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February 25, 2018 at 12:10AM
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Saturday, February 24, 2018

Extraction of Process Variation Parameters in FinFET Technology Based on Compact #Modeling and Characterization https://t.co/1RTYdSlig5


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February 24, 2018 at 12:38PM
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Friday, February 23, 2018

#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin... https://t.co/xKqgbSKTJs


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February 23, 2018 at 04:08PM
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#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin Song, Ying Xiao, Xinnan Lin, Mansun Chan, Fellow, IEEE https://t.co/yNcMnQarbw


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February 23, 2018 at 04:08PM
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[Short Course] RFSOI: from basics to practical use of wireless technology

RFSOI: from basics to practical use of wireless technology

18th of March, Granada, Spain
LLN
  
Incize organizes a one-day short course at EuroSOI-ULIS about Silicon-on-Insulator (SOI) technology for RF applications. The tutorial is given by globally recognized experts in the field. It aims to provide its participants with the knowledge about SOI materials, devices, circuits and performance.

  
The Silicon-on-Insulator (SOI) technology is gaining more grounds in the domains of RF applications. Nearly 100% of RF antenna switches in wireless system Front-End Modules (FEM) are based on SOI. A FEM entirely built on SOI can be implemented in the observable future as both academia and industry are working in this direction.

  
This tutorial will be of interest for engineers and graduate students willing to prepare themselves for the future RF applications.

Program:Sunday, March 18
08:00 – 08:50RF SOI, fabrication, materials and eco-system
(Abstract)
Ionut Radu
Director of Advanced R&D
Soitec, France
Ionut Radu
08:50 – 09:40Fundamentals of RF SOI technology(Abstract)Jean-Pierre Raskin
Professor
UCL, Belgium
Jean-Pierre
09:40 – 10:10Break
10:10 – 11:0022nm FDSOI Technology optimized 
for RF/mmWave Applications
 (Abstract)
David L. Harame
RF CTO Development and Enablement
GlobalFoundries, Germany
David L. Harame
11:00 – 11:50RF SOI technology and components for 5G connectivityChristine Raynaud
Program Manager (Business Development – Technology to Design)
CEA-Leti, France
Christine Raynaud
11:50 – 13:30Lunch
13:30 – 14:20Analog and RF design on SOI (Abstract)Barend van Liempd
Senior Researcher
imec, Belgium
Barend van Liempd
14:20 – 15:10Techniques and tricks for RF measurements on SOI Andrej Rumiantsev
Director RF Technologies
MPI Corporation, Germany
Andrej Rumiantsev
15:10 – 15:40Break
15:40 – 16:30FOSS TCAD/EDA tools for advanced 
SOI-device modeling
 (Abstract)
Wladek Grabinski
R&D CM Manager
MOS-AK, Switzerland
Wladek Grabinski
16:30 – 17:20RF design flow for SOIIan Dennison
Design Systems Senior Group Director
Cadence, UK
Ian Dennison


To register, please use the EuroSOI-ULIS registration website

More information about the EuroSOI-ULIS conference and the technical Program


For any inquiries please email us at info@incize.com
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Thursday, February 22, 2018

[paper] TFET Devices Re-Evaluation Résumé

Capturing Performance Limiting Effects in Tunnel-FETs
Michael Graef1,2, Fabian Hosenfeld1,2, Fabian Horst1,2, Atieh Farokhnejad1,2
Benjamín Iñíguez2 and Alexander Kloes1
1Competence Centre for Nanotechnology and Photonics, THM, Giessen, Germany
2DEEEA, Universitat Rovira i Virgili, Tarragona, Spain
ISTE OpenScience DOI: 10.21494/ISTE.OP.2018.0220

Abstract: In this paper a two-dimensional analytical Tunnel-FET model is revised. It is used to evaluate performance enhancing measures for the TFET regarding device geometry and physical effects. The usage of hetero-junctions is discussed and a way to suppress the ambipolar behavior of the TFET is shown. In focus of this work are the emerging variability issues with this new type of device. Random-dopant-fluctuations (rdf) have a major influence on the device performance. This effect is analyzed and compared with rdf effects in a MOSFET device. The drawn conclusions lead to a re-evaluation of performance limiting aspects of fabricated TFET devices [read more: 10.21494/ISTE.OP.2018.0220]

 FIG: a) Schematic geometry of an n-type DG Tunnel-FET, showing its structural parameters and doping profiles. b) Schematic band structure of a n-Tunnel-FET showing the different operating regimes and their dominating currents. 


[paper submission] MIXDES 2018


This year the 25th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018 will take place on June 21-23, 2018 in Gdynia, Poland

Submit a paper <https://www.mixdes.org/Mixdes3/>

Wednesday, February 21, 2018

#NEST is a simulator for spiking neural network #model https://t.co/BZaG7UkZXD https://t.co/0yGf5g7nNJ


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February 21, 2018 at 08:33PM
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[paper] Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy Based on EKV3.0 Model

Amine AYED and Hamadi GHARIANI
LETI Laboratory-ENIS
Sfax, Tunisia
IJACSA Vol. 8, No. 12, 2017

Abstract—In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz [read more...]

Fig.: Eye diagram for a VCO output @ 433MHz


Tuesday, February 20, 2018

#KiCad is big news for schematic capture, says Digi-Key https://t.co/XY3vD0xjCV #opensource https://t.co/TGhgnhIf6D


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February 20, 2018 at 10:44PM
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How to #format academic #paper on #Linux with groff -me https://t.co/7pK3YKTalH https://t.co/VjHS6T4gSB


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February 20, 2018 at 01:20PM
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Saturday, February 17, 2018

Multi-Function, #OpenSource, Reconfigurable Test And #Measurement #Platform https://t.co/kHU80VDFrl


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February 17, 2018 at 05:32PM
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Thursday, February 8, 2018

Today in Tech - 1956 - Douglas “Doug” Ross is best known to have originated the term “CAD” https://t.co/xO2K99dn7i #model


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February 08, 2018 at 10:20PM
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BSIM3v3 to EKV2.6 Model Parameter Extraction

BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation
using LM Algorithm on 0.18um Technology node
Kirmender Singh and Piyush Jain
Int. Journal of Electronics and Telecommunications 2018 Vol.64 No.1 pp.5-11

Abstract: The industry standard BSIM3v3 and BSIM4.0 have been replaced by BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 is next generation, defacto industry standard model for bulk MOSFET. This model is charge based which is continuous from weak to strong inversion of operation. The core of analytical and physical BSIM6 model[3] is charge, with drain current equation expressed in form of source (qs) and drain charge (qd). This model has all its governing equations continuous and can be used to develop design methodology using IC based approach. But its method of computing qs and qd is complicated which is different from Vittoz traditional charge calculation method. The continuous interpolation equation of drain current as adopted by EKV2.6 although is empirical but its compact expression is preferred by analog designer to get intuitive design guidance. BSIM6 is a combined effort by BSIM and EKV modeling groups based on charge based continuous equations. Although EKV2.6 model is not valid for deep submicron process as it only includes submicron short channel effects like velocity saturation (VS), vertical field mobility reduction (VFMR), Drain induced barrier lowering (DIBL), channel length modulation (CLM) etc. But it still offers some benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient (IC) has found extensive acceptance in designer community as it offers enhanced design elegance in EKV then more complicated BSIM model. This paper discuses first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18µ technology node. The 0.18µ technology is chosen as it is still more common technology node in analog circuit design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated with currentvoltage(I-V), intrinsic voltage gain (Avi) and Early voltage circuit parameter (VA) with BSIM3v3 model [read more...]

Flow-chart of BSIM to EKV conversion steps
(source:
D. Stefanovic and M. Kayal “Structured Analog CMOS Design" Springer Publications, 2008)

Meet #India’s women #opensource warriors https://t.co/OmYxPwCdlg https://t.co/KdqUF66d4E


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February 08, 2018 at 02:56PM
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ASAP7 predictive design kit development and cell design technology co-optimization: V. Vashishtha, M. Vangala and L. T. Clark, Invited #paper ICCAD, Irvine, CA, 2017 https://t.co/DS9MHtX5H4


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February 08, 2018 at 02:01PM
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Saturday, February 3, 2018

Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model... https://t.co/8wb8YJas8V


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February 03, 2018 at 11:45AM
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Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model https://t.co/t0nkAEKBcw https://t.co/Av6FzcFvip


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February 03, 2018 at 11:45AM
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Thursday, February 1, 2018

F. Rasheed, M. S. Golanbari, G. Cadilha Marques, M. B. Tahoori and J. Aghassi-Hagmann, "A Smooth EKV-Based DC #Model for Accurate Simulation of Printed Transistors and Their Process Variations," in IEEE TED, vol. 65, no. 2, pp. 667-673, Feb. 2018.https://t.co/vQ0xogjSx4


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February 01, 2018 at 07:56PM
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