Thursday, 22 February 2018

[paper submission] MIXDES 2018


This year the 25th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2018 will take place on June 21-23, 2018 in Gdynia, Poland

Submit a paper <https://www.mixdes.org/Mixdes3/>

Wednesday, 21 February 2018

#NEST is a simulator for spiking neural network #model https://t.co/BZaG7UkZXD https://t.co/0yGf5g7nNJ


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February 21, 2018 at 08:33PM
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[paper] Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy Based on EKV3.0 Model

Amine AYED and Hamadi GHARIANI
LETI Laboratory-ENIS
Sfax, Tunisia
IJACSA Vol. 8, No. 12, 2017

Abstract—In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18μm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz [read more...]

Fig.: Eye diagram for a VCO output @ 433MHz


Tuesday, 20 February 2018

#KiCad is big news for schematic capture, says Digi-Key https://t.co/XY3vD0xjCV #opensource https://t.co/TGhgnhIf6D


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February 20, 2018 at 10:44PM
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How to #format academic #paper on #Linux with groff -me https://t.co/7pK3YKTalH https://t.co/VjHS6T4gSB


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February 20, 2018 at 01:20PM
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Saturday, 17 February 2018

Multi-Function, #OpenSource, Reconfigurable Test And #Measurement #Platform https://t.co/kHU80VDFrl


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February 17, 2018 at 05:32PM
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Thursday, 8 February 2018

Today in Tech - 1956 - Douglas “Doug” Ross is best known to have originated the term “CAD” https://t.co/xO2K99dn7i #model


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February 08, 2018 at 10:20PM
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BSIM3v3 to EKV2.6 Model Parameter Extraction

BSIM3v3 to EKV2.6 Model Parameter Extraction and Optimisation
using LM Algorithm on 0.18um Technology node
Kirmender Singh and Piyush Jain
Int. Journal of Electronics and Telecommunications 2018 Vol.64 No.1 pp.5-11

Abstract: The industry standard BSIM3v3 and BSIM4.0 have been replaced by BSIM6.0 compact MOSFET model for deep submicron technology node. The BSIM6.0 is next generation, defacto industry standard model for bulk MOSFET. This model is charge based which is continuous from weak to strong inversion of operation. The core of analytical and physical BSIM6 model[3] is charge, with drain current equation expressed in form of source (qs) and drain charge (qd). This model has all its governing equations continuous and can be used to develop design methodology using IC based approach. But its method of computing qs and qd is complicated which is different from Vittoz traditional charge calculation method. The continuous interpolation equation of drain current as adopted by EKV2.6 although is empirical but its compact expression is preferred by analog designer to get intuitive design guidance. BSIM6 is a combined effort by BSIM and EKV modeling groups based on charge based continuous equations. Although EKV2.6 model is not valid for deep submicron process as it only includes submicron short channel effects like velocity saturation (VS), vertical field mobility reduction (VFMR), Drain induced barrier lowering (DIBL), channel length modulation (CLM) etc. But it still offers some benefits to have first cut design methodology because of its much simplified analytical equations. The inversion coefficient (IC) has found extensive acceptance in designer community as it offers enhanced design elegance in EKV then more complicated BSIM model. This paper discuses first step in analog design process by extracted core EKV2.6 intrinsic model parameters from industry standard BSIM3v3 model on 0.18µ technology node. The 0.18µ technology is chosen as it is still more common technology node in analog circuit design. The model parameters are extracted for different bins and optimisation is done using nonlinear optimisation LM algorithm. The optimised EKV2.6 parameters are validated with currentvoltage(I-V), intrinsic voltage gain (Avi) and Early voltage circuit parameter (VA) with BSIM3v3 model [read more...]

Flow-chart of BSIM to EKV conversion steps
(source:
D. Stefanovic and M. Kayal “Structured Analog CMOS Design" Springer Publications, 2008)

Meet #India’s women #opensource warriors https://t.co/OmYxPwCdlg https://t.co/KdqUF66d4E


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February 08, 2018 at 02:56PM
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ASAP7 predictive design kit development and cell design technology co-optimization: V. Vashishtha, M. Vangala and L. T. Clark, Invited #paper ICCAD, Irvine, CA, 2017 https://t.co/DS9MHtX5H4


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February 08, 2018 at 02:01PM
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Saturday, 3 February 2018

Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model... https://t.co/8wb8YJas8V


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February 03, 2018 at 11:45AM
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Assessing the impact of temperature and voltage variations in near-threshold circuits using an analytical #model https://t.co/t0nkAEKBcw https://t.co/Av6FzcFvip


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February 03, 2018 at 11:45AM
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Thursday, 1 February 2018

F. Rasheed, M. S. Golanbari, G. Cadilha Marques, M. B. Tahoori and J. Aghassi-Hagmann, "A Smooth EKV-Based DC #Model for Accurate Simulation of Printed Transistors and Their Process Variations," in IEEE TED, vol. 65, no. 2, pp. 667-673, Feb. 2018.https://t.co/vQ0xogjSx4


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February 01, 2018 at 07:56PM
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