Showing posts with label Single-electron transistor. Show all posts
Showing posts with label Single-electron transistor. Show all posts

Aug 5, 2021

[paper] Modeling and investigation of SET Inverter Circuit

C. Shyamala, V. Kalpana
Modeling and investigation of SET Inverter Circuit
International Journal of Innovative Research in Engineering 25 
Vol. 2, Issue 3 (May-June 2021), pp: 25-28 
ISSN No: 2582-8746; www.theijire.com

* Department of EEE, RV College of Engineering, VTU University, Karnataka. India.

Abstract: This paper presents an analytical model Inverter based on the theory of single electron transistor(SET). The proposed design is very flexible such that it can be used for single gate, multi-gate, symmetric, asymmetric devices and most importantly it can also consider the effect of background charge. It can also be used for large voltage range of drain-source voltage irrespective of the bias conditions. The proposed design has been simulated with SPICE and the characteristics produced by the proposed design have been verified against Monte Carlo simulator SIMON [1].
Fig: Schematic diagram of single electron inverter

Reference:
[1] SIMON - A single electron device and circuit simulator
https://www.lybrary.com/simon/examples.html




Sep 21, 2020

[tutorial] next generation 3D nano device simulator

Single-electron transistor - laterally defined quantum dot - 3D Tutorial
Stefan Birner
https://www.nextnano.com

Single-electron transistor - laterally defined quantum dot In this tutorial, we simulate an AlGaAs/GaAs heterostructure grown along the z direction. This structure leads to a two-dimensional electron gas (2DEG). By appying a gate voltage on top of the structure in the (x,y) plane, one is able to deplete the 2DEG and a laterally defined QD is formed. By adjusting the gate voltage, one is able to tune the number of electrons that are inside the QD.
This figure shows the conduction band edge Ec(x,y) and the electron density n(x,y) for the 2DEG plane, i.e. at z = 8 nm below the GaAs/AlGaAs heterojuntion. The geometry of the top gates is indicated by the blue regions. The following figure shows the calculated conduction band edge and the electron density of the heterostructure. The results are similar to Fig. 4 in paper [1].
The following figure shows two 2D slices through the lateral (x,y) plane at a distance of 8 nm below the AlGaAs/GaAs interface. In the middle, the electron density is shown. The electron density has been calculated classically. At the bottom, the conduction band edge is shown. The results are similar to Fig. 5 in paper [1]. At the top, the four gates are shown.

REF:
[1] A. Scholze, A. Schenk, W. Fichtner; Single-Electron Device Simulation; IEEE TED 47, 1811 (2000)