[program] 16th AEC at INAOE

16th Advanced Electronics Congress

<https://www-elec.inaoep.mx/~SEA/2026/>

National Institute of Astrophysics, Optics and Electronics

Luis Enrique Erro No. 1, Tonantzintla, Puebla, México

September 09 - 11, 2026

The Electronics Coordination of INAOE proudly organizes its traditional Advanced Electronics Congress, now in its 16th edition, with the valuable support of the IEEE Electron Devices Society (EDS), the IEEE Instrumentation and Measurement Society (I&M Society), and the IEEE Puebla Section.

Since its inception in 2008, the Congress has aimed to bring together undergraduate and graduate students, researchers, and faculty members in Mexico with internationally recognized experts in the fields of microelectronics, nanoelectronics, integrated circuit design, high-frequency systems, communications, and instrumentation. Guided by this objective, the invited speakers present the most significant recent advances in their respective areas of expertise.

Throughout the Congress’s long history, the program has not only covered specialized topics related to these fields but has also embraced interdisciplinary perspectives in areas such as optics, agriculture, medicine, and a wide range of computer systems applications.

In addition, the Advanced Electronics Congress serves as a forum for interaction among colleagues and students, fostering interinstitutional collaboration and networking opportunities in alignment with the mission and international vision of the IEEE Societies within the IEEE Puebla Section

16th Advanced Electronics Congress Program
(September 09 - 11, 2026)

Wednesday, September 09th

Time	Topic	Speaker	Institute
08:00 - 09:00	Congress Registration
08:30 - 09:00	Inauguration
09:00 - 10:00	“Las herramientas que mueven el mundo”	Dr. Guy Paic	Instituto de Ciencias Nucleares (ICN), UNAM
10:00 - 11:00	“Desde la Ciencia de Frontera hasta el Desarrollo Tecnológico: Plataforma de Biosensado Multiespectral para Detección de Pesticidas”	Dra. Daniela Díaz Alonso	Ibero México, CD-MEMS INAOE
11:00 - 11:30	Break
11:30 - 12:30	“Diseño y caracterización de estructuras integradas para microondas”	Dra. Gabriela Méndez Jeronimo	CICESE, Ensenada, Baja California, Mexico, INAOE
12:30 - 13:30	“Modelado, prototipado y diseño ASIC para procesadores empleados en PLCs”	Dr. Carlos Alberto Hernández Gutiérrez	CINVESTAV, CDMX

Thursday, September 10th

08:00 - 09:00	Congress Registration
09:00 - 10:00	“Merging Smart Sensors, IoT, AI and Digital Twins Technologies for Digital Transformation in Agriculture”	Dr. Octavian Postolache	Instituto Universitario de Lisboa. Distinguished Lecturer IEEE Instrumentation and Measurement Society
10:00 - 11:00	“Electrodo de batería de ion litio a base de Silicio con recarga asistida por luz”	Dr. Enrique Quiroga González	Instituto de Física, BUAP
11:00 - 11:30	Break
11:30 - 12:30	“Aplicación del Control Predictivo a Convertidores CD-CD”	Dr. Germán Ardul Muñoz Hernández	BUAP, Tecnológico Nacional de México, Puebla.
12:30 - 13:30	“Exploring 22 nm FDSOI Transistors: Electrical Characterization, Reliability, and Temperature Effects”	Dra. Paulina Mariana Maya Hernández	INAOE

Friday, September 11th

08:00 - 09:00	Congress Registration
09:00 - 10:00	“Processor Validation in Industry in the Age of AI: Challenges, Innovations, and Career Opportunities”	Dr. Francisco Elías Rangel Patiño	Intel Guadalajara
10:00 - 11:00	“Space Mapping Design Optimization: Power in Simplicity Rooted in Engineering Practice”	Dr. José Ernesto Rayas Sánchez	ITESO en Guadalajara
11:00 - 11:30	Break
11:30 - 12:30	“Visión por Computadora, FPGAs y Sistemas Embebidos para solución de problemas AgroIndustriales”	Dr. Marco Aurelio Nuño Maganda	Universidad Politécnica de Victoria
12:30 - 13:30	“Integración de Sensores IoT y Realidad Aumentada para Sistemas Ciberfísicos”	Dr. Yehoshua Aguilar Molina	Universidad de Guadalajara, Centro Universitario de Los Valles
13:30 - 14:00	Closure

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Organizing Committee

• Dr. Juan Manuel Ramírez Cortés
• Dr. Roberto Stack Murphy Arteaga
• Dr. José de Jesús Rangel Magdaleno
• Dr. José Hugo Barrón Zambrano
• Dra. Ma. Teresa Sanz Pascual
• Dr. Mariano Aceves Mijares
• Dr. Daniel Durini Romero

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Contact

Valeria Rodríguez <vrdz@inaoep.mx>

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© INAOE/AGC 2026

[paper] Flexible TFT Electronics

Hikmet Çeliker, Wim Dehaene and Kris Myny

Multi-project wafers for flexible thin-film electronics by independent foundries.

Nature (2024)

DOI: 10.1038/s41586-024-07306-2

1. ESAT, KU Leuven, Leuven, Belgium
2. imec, Leuven, Belgium

Abstract: Flexible and large-area electronics rely on thin-film transistors (TFTs) to make displays large-area image sensors, microprocessors, wearable healthcare patches, digital microfluidics, and more. Although silicon-based complementary metal–oxide–semiconductor (CMOS) chips are manufactured using several dies on a single wafer and the multi-project wafer concept enables the aggregation of various CMOS chip designs within the same die, TFT fabrication is currently lacking a fully verified, universal design approach. This increases the cost and complexity of manufacturing TFT-based flexible electronics, slowing down their integration into more mature applications and limiting the design complexity achievable by foundries. Here we show a stable and high-yield TFT platform for the fabless manufacturing of two mainstream TFT technologies, wafer-based amorphous indium–gallium–zinc oxide and panel-based low-temperature polycrystalline silicon, two key TFT technologies applicable to flexible substrates. We have designed the iconic 6502 microprocessor in both technologies as a use case to demonstrate and expand the multi-project wafer approach. Enabling the foundry model for TFTs, as an analogy of silicon CMOS technologies, can accelerate the growth and development of applications and technologies based on these devices.

FIG:  Photograph of all three chips at once: the vintage WDC 65C02 in a 40-pin DIP package (left), the flex LTPS 6502 (middle) and the flex IGZO 6502 (right)

Acknowledgements: We thank PanelSemi (a system-on-film foundry service provider in Taiwan) for providing LTPS panels and Pragmatic for providing IGZO wafers as a verification of our designs, using their foundry-mode panel and wafer delivery services. Part of this work has received funding under the Horizon Europe programme from the European Research Council under grant agreement no. 101088591 ‘ORISON project’. Views and opinions expressed are, however, those of the authors only and do not necessarily reflect those of the European Union or the European Research Council. Neither the European Union nor the granting authority can be held responsible for them.

[paper] Characteristics and ultra-high total ionizing dose response

Termo, Gennaro, Giulio Borghello, Federico Faccio, Kostas Kloukinas, Michele Caselle, Alexander Friedrich Elsenhans, Ahmet Cagri Ulusoy, Adil Koukab, and Jean-Michel Sallese

 Characteristics and ultra-high total ionizing dose response 

of 22 nm fully depleted silicon-on-insulator

Journal of Instrumentation 19, no. 03 (2024): C03039

DOI 10.1088/1748-0221/19/03/C03039

a CERN, Geneva, Switzerland

b École Polytechnique Fédérale de Lausanne, Switzerland

c Karlsruhe Institute of Technology, Germany

Abstract: The radiation response of MOS transistors in a 22 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology exposed to ultra-high total ionizing dose (TID) was investigated. Custom structures including n- and p-channel devices with different sizes and threshold voltage flavours were irradiated with X-rays up to a TID of 100 Mrad(SiO2) with different back-gate bias configurations, from −8 V to 2 V. The investigation revealed that the performance is significantly affected by TID, with the radiation response being dominated by the charge trapped in the buried oxide.

Fig: Schematic of the irradiated transistors in 22 nm FDSOI 

Complementary paper:

[1] Termo, Gennaro, Giulio Borghello, Federico Faccio, Stefano Michelis, A. Koukab, and J-M. Sallese. "Fab-to-fab and run-to-run variability in 130 nm and 65 nm CMOS technologies exposed to ultra-high TID." Journal of Instrumentation 18, no. 01 (2023): C01061.

Summer School on Organic Electronics and Neuromorphic Systems

Summer School on Organic Electronics and Neuromorphic Systems

June 17-20, 2024

will consist of a comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. By means of a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of organic materials, devices and circuits for microelectronics, as well as of neuromorphic devices and circuits with the world’s leading experts in these fields.

This Summer School is sponsored by the EU-funded BAYFLEX (Bayesian Inference with Flexible electronics for biomedical Applications) project. It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the Summer School is Prof. Benjamin Iñiguez.

PhD students can present posters showing some of their results in a session on June 20 afternoon. Interested PhD students can submit short abstracts of the results they want to present in the Poster Session.

Invited Speakers

• Jiri Pfleger, Czech Academy of Sciences (organic memristors),  
• Luisa Petti, University of Bolzano (organic electronics), 
• Chiara Bartollozzi, Italian Institute of Technology, Italy (event driven vision/robotics, CMOS) (neuromorphic), 
• Wilfred G. van der Wiel, Chair NanoElectronics Group | Director BRAINS Center for Brain-Inspired Nano Systems (organic +neuromorphic), 
• Sébastien Sanaur, IMT, France (neuromorphic), 
• François Danneville, IEMN, Lille, France (spiking neurons), 
• Simone Fabiano, University of Linköping, Sweden (organic + neuromorphic), 

Mini-Colloquium:

• Lluís F. Marsal, Universitat Rovira i Virgili, Tarragona, Spain, 
• Arokia Nathan, University of Cambridge, Darwin College, UK, 

• Paul Berger, Ohio State University, USA, 
• Radu A. Sporea, University of Surrey, UK, 
• Angèle Reynders, TU-Eindhoven, The Netherlands, 

Postdoc position in GaN power devices

The POWERlab (https://powerlab.epfl.ch) at EPFL is looking for excellent and motivated candidates to work on new concepts for power electronic devices based on GaN heterostructures. The candidate will pursue novel ideas related to concepts developed in our laboratory, for example [1]. The candidate will have the opportunity to work on several aspects involved in demonstrating high-performance power devices (cleanroom fabrication, device simulation and characterization) relying on the excellent facilities in our laboratory and at EPFL. Most importantly, the candidate is encouraged to try new ideas and approaches.

Profile: The candidate is expected to have a solid theoretical background in semiconductors and experience in cleanroom fabrication of GaN electronic devices, with strong aptitude to perform experiments, explore new concepts, and communicate his/her findings in high-quality scientific publications.

What is offered: The selected candidate will be offered a fellowship with very competitive salary and excellent conditions to excel in his/her research.

How to apply: If you are interested, and have the correct profile for this position, please send your CV to elison.matioli@epfl.ch, including publication list and names of two references.

REF:

[1] L. Nela, J. Ma, C. Erine, P. Xiang, T.-H. Shen, V. Tileli, T. Wang, K. Cheng and E. Matioli, “Multi-channel nanowire devices for efficient power conversion” Nature Electronics, 4, 284–290, (2021)

IEEE EDS MQ at NIT Silchar Silchar, Assam (IN)

IEEE EDS Mini-Colloquium 

on Micro/Nanoelectronics, Devices, Circuits and Systems, 

29-31 Jan 2023 (Hybrid Mode)

DATES	LOCATION	HOST	REGISTER
Date: 29 Jan 2023 Time:10:00AM to 06:00PM  (UTC+05:30)  Add Event to Calendar  iCal  Google Calendar	National Institute of Technology Silchar Dept of ECE, NIT Silchar Silchar, Assam India 788010 Building: ECE/CSE Building	National Inst of Technology - Silchar, ED15 Kolkata Section Chapter NANO42 Co-sponsored by Dr. Trupti R. Lenka	Starts Dec.1, 2022 Ends Jan.28,2023 No Admission Charge Register NOW

Agenda with following contribution Distinguished Lecturers: 

• Anil Kottantharayil (anilkg@ieee.org)
• Gananath Dash (gndash@ieee.org)
• Ajit Kumar Panda (akpanda62@hotmail.com)
• Manoj Saxena (msaxena@ieee.org)
• Brajesh Kumar Kaushik (bkkaushik23@gmail.com)
• Samar Saha (samar@ieee.org)
• Hiroshi Iwai (h.iwai@ieee.org)
• Taiichi Otsuji (taiichi.otsuji.e8@tohoku.ac.jp)
• Pei-Wen Li (pwli@nycu.edu.tw)
• Zhou Xing (EXZHOU@ntu.edu.sg)
• Albert Chin (albert_achin@hotmail.com)
• Mansun Chan (mchan@ust.hk)
• Chao-Sung LAI (cslai@mail.cgu.edu.tw)
• Wladek Grabinski, MOS-AK, EU (wladek@grabinski.ch)

Register NOW

[webinar] Power WBG Semiconductor Technology Opportunities

"Power WBG Semiconductor Technology Opportunities"

webinar hosted by 

Dr. Victor Veliadis, 

Executive Director and CTO of PowerAmerica, 

a WBG semiconductor power electronics consortium

Event by Łukasiewicz - Institute of Microelectronics and Photonics

Register now: https://lukasiewiczimif.clickmeeting.com/poweramerica/register

Silicon power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low-cost volume production, and proven reliability. However, they’re approaching their operational limits primarily due to their relatively low bandgap and critical electric field that results in high conduction and switching losses, and poor high-temperature performance. So what can we do? Well, let’s talk about the favorable WBG material properties, their volume application opportunities, and last but not least let's highlight the respective competitive advantages of SiC and GaN.

You will additionally learn about:

• the lateral and vertical power device configurations that will be analyzed in the context of bidirectional switching
• specific applications and needs for bidirectional switches
• key topologies, enabled by bidirectional switches
• PowerAmerica’s work to accelerate WBG power electronics commercialization

About Dr. Veliadis: Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars. Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).

[paper] Special Topic on Materials and Devices for 5G Electronics

Nathan D. Orloff¹, Rick Ubic², and Michael Lanagan³

Special topic on materials and devices for 5G electronics

Appl. Phys. Lett. 120, 060402 (2022); 

DOI: 10.1063/5.0079175

1 NIST, Colorado, USA
2 Boise State University, Idaho, USA
3 Penn State University, Pennsylvania, USA

Abstract: Next generation communications are inspiring entirely new applications in education, healthcare, and transportation. These applications are only possible because of improvements in latency, data rates, and connectivity in the latest generation. Behind these improvements are new materials and devices that operate at much higher frequencies than ever before, a trend that is likely to continue. Beyond these exciting applications, higher frequency millimeter waves (mmWaves) may also address a growing problem with capacity. Today, most capacity problems occur when large numbers of wireless connections or applications access the network at the same time at any single location. As wireless internet connections far surpass wired connections and wireless data usage has grown exponentially for more than 10 years,3 many believe that capacity problems will spread without access to new bandwidth.

FIG: A plot of the peak data rates vs the operating frequency 

where the diameter of the circle is the bandwidth.

Acknowledgement: Our [the editors] special thanks to Lesley Cohen, Editor-in-Chief, Susan Trolier-McKinstry, Associate Editor, and Jessica Trudeau and Emma Nicholson Van Burns for their technical assistance with publishing.

My Story of Raja Manickam, CEO of OSAT, Tata Electronics

For the November issue, Electronicsforu.com Network shares My Story of Raja Manickam who is CEO of OSAT, Tata Electronics.

CLICK HERE to read it.

Rahul Chopra Editor,

Electronicsforu.com Network | EFY Group | New Delhi | India |

[book] Future Ultra Low Power Electronics

Semiconductor Devices and Technologies for Future Ultra Low Power Electronics (1st ed.)

Nirmal, D., Ajayan, J., & Fay, P.J. (Eds.)

CRC Press. (2021).

DOI: 10.1201/9781003200987

Abstract: This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided. 

Contents:

Preface vii

Editors ix

Contributors xi

Chapter 1: An Introduction to Nanoscale CMOS Technology Transistors: A Future Perspective; pp: 1

Kumar Prasannajit Pradhan

Chapter 2: High-Performance Tunnel Field-Effect Transistors (TFETs) for Future Low Power Applications; pp: 29

Ribu Mathew, Ankur Beohar, and Abhishek Kumar Upadhyay

Chapter 3: Ultra Low Power III-V Tunnel Field-Effect Transistors; pp: 59

J. Ajayan and D. Nirmal

Chapter 4: Performance Analysis of Carbon Nanotube and Graphene Tunnel Field-Effect Transistors; pp: 87

K. Ramkumar, Singh Rohitkumar Shailendra, and V. N. Ramakrishnan

Chapter 5: Characterization of Silicon FinFETs under Nanoscale Dimensions; pp: 115

Rock-Hyun Baek and Jun-Sik Yoon

Chapter 6: Germanium or SiGe FinFETs for Enhanced Performance in Low Power Applications; pp: 129

Nilesh Kumar Jaiswal and V. N. Ramakrishnan

Chapter 7: Switching Performance Analysis of III-V FinFETs .; pp: 155

Arighna Basak, Arpan Deyasi, Kalyan Biswas, and Angsuman Sarkar

Chapter 8: Negative Capacitance Field-Effect Transistors to Address the Fundamental Limitations in Technology Scaling; pp: 187

Harsupreet Kaur

Chapter 9: Recent Trends in Compact Modeling of Negative Capacitance Field-Effect Transistors; pp: 203

Shubham Tayal, Shiromani Balmukund Rahi, Jay Prakash Srivastava, and Sandip Bhattacharya

Chapter 10 Fundamentals of 2-D Materials; pp: 227

Ganesan Anushya, Rasu Ramachandran, Raj Sarika, and Michael Benjamin

Chapter 11 Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field-Effect Transistor (FET) Devices for Low Power Applications; pp 253

R. Sridevi and J. Charles Pravin

Index pp: 289

IJHSES Special Issue Volume 29, Issue 01n04, 2020

IJHSES Special Issue on Nanotechnology for Electronics, Biosensors, 

Additive Manufacturing and Emerging Systems Applications 

Guest Editors: F. Jain, C. Broadbridge, M. Gherasimova and H. Tang

Volume 29, Issue 01n04 (March, June, September, December 2020) 

This Special issue on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications comprises peer reviewed articles selected from the 29th annual symposium of the Connecticut Microelectronics and Optoelectronics Consortium (CMOC), virtually held on October 2, 2020 and hosted by Information Technology Staff, University of Connecticut (Storrs Campus).

Organized by a team of seven academic institutions and about eighteen companies across the United States, this symposium sign-posted the progress and development of state-of-arts research in high-speed electronics over the last 30 years.

Articles include keynote presentations by three experts in their field:

• Dr. H. Lee, Electronic and IR Sensing in Forensics, U. New Haven, and Henry Lee Center for Forensic Research
• Dr. E. Fossum, Quanta Image Sensor, Dartmouth College
• Dr. J. Chow, Quantum Computing, IBM Thomas J. Watson, Research Center

The papers presented span from novel materials and devices, biosensors and bio- nano- systems, artificial intelligence, robotics and emerging technologies, to applications in each of these fields, Systems for implementing data with security tokens; single chemical sensor for multi-analyte mixture detection; RF energy harvesters; additively manufactured RF devices for 5G, IoT, RFID and smart city applications are also included in this special issue on high performance materials for implementing high-speed electronic systems.

In the area of material synthesis, modeling of dislocations behavior in various II-VI and III-V heterostructures and their gettering at sidewall bringing novel approaches are also featured

Coming hot on the heels, are recent developments on high performance devices include equivalent circuits models at room and 4.2K; quantum dot nonvolatile memories, 3D- confined quantum dot channel (QDC) and spatial wavefunction switched (SWS) FETs for high-speed multi-bit logic and novel system applications.

In summary, the papers selected for this special issue cover various aspects of h performance materials and emerging devices for implementing high-speed electronic systems. We would like to take this opportunity to express our thanks to the authors, participants, and reviewers for their contributions and active participation, networking, and knowledge sharing on a variety of research areas.

[PhD] Printed Inorganic Materials Electronics

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials

PhD Dissertation

Gabriel Cadilha Marques

Veröffentlicht am 30.04.2020

DOI: 10.5445/IR/1000118801

Abstract - The goal of this thesis is therefore to develop an inorganic printed electronics technology with corresponding modeling methodologies to capture device behavior for industry standard circuit simulators as well as circuit designs as building blocks for future applications. To reduce the high supply voltage requirements (~5V) in PE, alternative gating approaches for FETs are considered. One approach is to replace the dielectric with an electrolyte. Due to the formation of a Helmholtz double layer (HDL), a FET with a high gate-capacitance (~5 μFcm-2) is expected, reducing the voltage requirements to ~1V. By combining the indium oxide channel with the electrolyte-gating approach, high performance devices with low voltage requirements are available in PE.

Innovations in Electronics and Communication Engineering

Proceedings of the Fifth ICIECE 2016

Volume 7 of Lecture Notes in Networks and Systems

H. S. Saini, R. K. Singh, K. Satish Reddy

Springer, 8 Nov 2017 - Technology & Engineering - 596 pages

ISBN 9811038120, 9789811038129

The book contains high quality papers presented in the Fifth International Conference on Innovations in Electronics and Communication Engineering (ICIECE 2016) held at Guru Nanak Institutions, Hyderabad, India during 8 and 9 July 2016. The objective is to provide the latest developments in the field of electronics and communication engineering specially the areas like Image Processing, Wireless Communications, Radar Signal Processing, Embedded Systems and VLSI Design. The book aims to provide an opportunity for researchers, scientists, technocrats, academicians and engineers to exchange their innovative ideas and research findings in the field of Electronics and Communication Engineering [read more...]

VI Regional Seminar MNE & MS 2014

VI Regional Seminar on Computer Modeling and Designing in Micro- and Nanoelectronics and in Microelectromechanical Systems (MNE & MS 2014),

Orel, Russia, March 28 2014

1. С.И. Матюхин¹, Welcome and Seminar Openning,
   ¹Госуниверситет-УНПК
2. Турин В.О.¹, Кильчицкая М.В.², Герасимов К.А.², Simulation of power bipolar transistor,
   ¹Госуниверситет-УНПК, ²БГТУ, г. Брянск
3. Ващенко В.А., The physical ESD design for integrated circuits and electronic devices,
   Maxim Integrated Corp., г. Сан Хосе, Калифорния, США
4. Цырлов А.М., Development of CMOS optocoupler,
   ОАО «Протон», г. Орёл
5. Студенников А.С., Development of CMOS ICs,
   ОАО «Протон», г. Орёл
6. Малый Д.О.¹, Матюхин С.И.², Ставцев А.В.¹, "Proton-Elektroteks" IGBT-devices JSC: basic approaches of production and quality assurance,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
7. Макулевский Г.Р., Матюхин С.И., Current-voltage characteristics of laser diodes based on AlGaAs,
   Госуниверситет-УНПК
8. Матюхин С.И., Гришин В.О., Radiation effects of on the current-voltage characteristic of power diodes and thyristors,
   Госуниверситет-УНПК
9. Писарев А.А.¹, Матюхин С.И.², Сурма А.М.¹, Черников А.А.¹, Electrical characteristics of fast diodes with soft recovery,
   ¹ЗАО «Протон-Электротекс», г. Орёл, ²Госуниверситет-УНПК
10. Koziol Z., Aestimo quantum mechanical software for modeling quantum wells in nanoelectronics,
    TU Rzeszow, Polska