Tuesday, November 27, 2018

Analysis of #DIBL Effect and Negative Resistance Performance for }NCFET Based on a Compact #SPICE #Model https://t.co/nPHYOs9Kwk


from Twitter https://twitter.com/wladek60

November 27, 2018 at 06:19PM
via IFTTT

Explicit #Model of Channel Charge, Backscattering, and Mobility for #Graphene #FET in Quasi-#Ballistic Regime https://t.co/lpR01Q50eg


from Twitter https://twitter.com/wladek60

November 27, 2018 at 04:44PM
via IFTTT

Sunday, November 25, 2018

An Illustrated Subway Map of Human Anatomy https://t.co/viL7vi1dDV #modeling


from Twitter https://twitter.com/wladek60

November 25, 2018 at 07:07AM
via IFTTT

Friday, November 23, 2018

Compact #Terahertz #SPICE #Model: Effects of Drude Inductance and Leakage https://t.co/EilnJUx4tD


from Twitter https://twitter.com/wladek60

November 23, 2018 at 09:13PM
via IFTTT

Optimization and #Scaling of #Ge-Pocket #TFET (#paper) https://t.co/yJlBGPCPH6


from Twitter https://twitter.com/wladek60

November 23, 2018 at 04:49PM
via IFTTT

#Mobility Calculation of Ge Nanowire #Junctionless and Inversion-Mode Nanowire NFETs With Size and Shape Dependence (#paper) https://t.co/6hlQOts03n


from Twitter https://twitter.com/wladek60

November 23, 2018 at 04:47PM
via IFTTT

High-k Spacer Consideration of Ultrascaled Gate-All-Around #Junctionless Transistor in Ballistic Regime (#paper) https://t.co/kZdPay7S4J


from Twitter https://twitter.com/wladek60

November 23, 2018 at 03:20PM
via IFTTT

Thursday, November 22, 2018

[mos-ak] [Final Program] 11th International MOS-AK Workshop; Silicon Valley, December 5, 2018

11th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 5, 2018

Together with Sivaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 11th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 11th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/silicon_valley_2018/>

Venue:
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara,  California  95054

Online Registration is still open
(any related enquiries can be sent to registration@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

W.Grabinski on the behalf of International MOS-AK Committee

WG22112018










--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

The Experimental Side of #Modeling - Read online https://t.co/m883tQBNI3


from Twitter https://twitter.com/wladek60

November 22, 2018 at 06:43PM
via IFTTT

Monday, November 19, 2018

A Path to Energy #Efficiency and #Reliability for ICs: Fully Depleted Silicon-on-Insulator (#FDSOI) Devices Offer Many Advantages - in IEEE Solid-State Circuits Magazine, vol. 10, no. 4, pp. 24-33, Fall 2018 https://t.co/cnPoHeQHIu #paper


from Twitter https://twitter.com/wladek60

November 19, 2018 at 12:10AM
via IFTTT

Friday, November 9, 2018

7 reasons I love #opensource and you should too https://t.co/YwtVU50Wts https://t.co/XAvfO6kHve


from Twitter https://twitter.com/wladek60

November 09, 2018 at 05:01PM
via IFTTT

Wednesday, November 7, 2018

#Franz is made in Vienna, Austria with lots of by Stefan Malzner & the amazing community. https://t.co/pUfl4P1ng0 #opensource


from Twitter https://twitter.com/wladek60

November 07, 2018 at 07:32PM
via IFTTT

Friday, November 2, 2018

Device #Modeling of MgO-Barrier Tunneling Magnetoresistors for Hybrid Spintronic-CMOS https://t.co/sHrPJQm09t


from Twitter https://twitter.com/wladek60

November 02, 2018 at 09:41PM
via IFTTT

ISDCS 2019 in Hiroshima


The International Symposium on Devices, Circuits and Systems & Workshop on Nanoelectronics will take place in Hiroshima (Japan), on March 6-8 2019.

http://www.isdcs2019.hiroshima-u.ac.jp/

The ISDCS is a premium international forum for scholars, scientists, educators, students and engineers to exchange their latest findings and technological advances in the field of devices, circuits and systems. 

One of the topics is Physics, Analysis and Modeling of Devices. 

Other topics;


Photonics and Optoelectronics of Advanced Materials
Digital and Analog Circuits and Their System Applications
Neural Networks & Neuromorphic Circuits and Systems
Circuit Testing and Verifications
IoT Circuits and Systems
AI Circuits for Machine Learning Systems
Beyond CMOS Circuits and Hybrid systems
Intelligent Systems and Robotics
Environment Electronics and
Their Applications
Visual Communications & Multimedia Signal Processing




This symposium is initiated by IIEST Shibpur in collaboration with Hiroshima University, which will be held annually in India and in Japan alternatively. The first event was held at IIEST Shibpur. The 1st ISDCS-2018 conference proceedings are published in IEEE-explore.  

Deadline: November 15 2018.