Tuesday, January 26, 2010

A paper in the Feb. issue of IEEE TED

A Physically Based Accurate Model for Quantum Mechanical Correction to the Surface Potential of Nanoscale MOSFETs
Karim, M. A.   Haque, A.  
Department of Electrical and Electronic Engineering, United International University, Dhaka;

This paper appears in: Electron Devices, IEEE Transactions on
Publication Date: Feb. 2010
Volume: 57,  Issue: 2
On page(s): 496-502
ISSN: 0018-9383
Digital Object Identifier: 10.1109/TED.2009.2037453
First Published: 2009-12-28
Current Version Published: 2010-01-19

We present a physically based explicit analytical model for the quantum mechanical (QM) correction to the surface potential of nanoscale metal–oxide–semiconductor (MOS) devices. The effect of wave function penetration into the gate dielectric is taken into account. Instead of using the band-gap widening approach, which indirectly includes QM correction, the proposed correction term is directly added to the semiclassical surface potential. Under accumulation bias, charges in extended states and quantized states contribute to the surface potential in different ways. The proposed QM correction considers this difference in contributions. Comparison with two existing analytical QM correction models and two self-consistent QM numerical models show that the proposed correction is more accurate than the existing analytical models. The improvement achieved under the accumulation bias is particularly significant. The gate $C$$V$ characteristics of a number of different MOS devices have been simulated using the proposed correction. Excellent agreement with published experimental data has been observed.

Analog FastSpice RF delivers noise analysis for RF circuits

By Rick Nelson, Editor-in-Chief -- EDN, 12/22/2009

Berkeley Design Automation Inc has announced AFS RF (Analog FastSpice radio frequency), which Chief Operating Officer Paul Estrada calls the industry’s first true Spice-accurate noise-analysis tool for RF circuits. AFS RF accurately analyzes nanometer-scale device noise impact for all types of prelayout and postlayout circuits, ensuring early insight into its impact on performance, power, and area.
 Before the emergence of AFS RF, designers had to use limited-spectrum RF tools that can only approximate device noise impact on RF circuits, Estrada explains. Such approximations are increasingly inaccurate with decreasing process geometries, often becoming grossly inaccurate in nanometer-scale circuits. Circuits with sharp transitions, such as switched-capacitor filters, charge pumps, and dividers; high-frequency circuits, such as RF front-end blocks; and oscillators are especially sensitive to these inaccuracies. Without accurate analysis, designers must include expensive design margin or risk missing specifications in silicon.
 Using the industry’s first full-spectrum device-noise-analysis engine, Analog FastSpice RF provides true Spice accuracy for every run. For complex circuits, it is five to 10 times faster than traditional RF tools that can only approximate device-noise effects. AFS RF features the DNA (device noise-analysis) Advisor to characterize DNA requirements, high-capacity periodic-steady-state analysis for greater than 100,000-element postlayout circuits, full-spectrum periodic-noise analysis with true Spice accuracy, full-spectrum total oscillator-device-noise analysis capability with phase and amplitude noise, and harmonic balance for fast single-tone analysis of moderately nonlinear circuits.

You can read the full post here...

Monday, January 25, 2010

EAMTA 2010 / CAMTA - CUMTA 2010

EAMTA 2010 [www.eamta.com.ar]
The fifth School of Micro and Nanoelectronics will take place from October 1 - 9, 2010, in the facilities of Instituto de Ingeniería Eléctrica of Universidad de la República del Uruguay and Departamento de Ingeniería Eléctrica Universidad Católica del Uruguay.

CAMTA - CUMTA 2010 [www.eamta.com.ar]
The Conference section of the School will take place on Thursday October 7 and Friday October 8, 2010. All papers will be presented in poster format, to stimulate discussion and feedback. Tutorials will be in charge of distinguished lecturers.

Contact Information: For the 2010 edition of EAMTA, Dr. Fernando Silveira and Dr. Alfredo Arnaud will be the General Chairs: [eamta.ar (at) gmail.com]

Sunday, January 24, 2010

ISSCC 2010 Preview: Assessing '05 predictions

A couple of safe ISSCC'05 bets reviewd by Don Scansen. Have ISSCC organizers learned something by looking back?

Agilent Technologies Announces YouTube Channel for Agilent EEsof EDA

Agilent Technologies Inc. has announced the launch of the Agilent EEsof EDA channel on YouTube. The channel features more than 100 informational videos with subtitles in 50 different languages. The videos offer detailed application information on the Advanced Design System, Genesys, SystemVue, and other electronic design automation software from Agilent EEsof. The channel is designed to provide tutorial information to Agilent’s large installed base of users, or to anyone wanting to learn more about Agilent EEsof’s design software and high-frequency design applications. [more]

Thursday, January 21, 2010

Some papers

I've seen five interesting papers in the current issue of the International Journal of Numerical Modelling: Electronic Networks, Devices and Fields (Volume 23, Issue 2, 2010.):
Pages: 88-106
Implementation of the symmetric doped double-gate MOSFET model in Verilog-A for circuit simulation
Joaquín Alvarado, Benjamin Iñiguez, Magali Estrada, Denis Flandre, Antonio Cerdeira

Published Online: 30 Jul 2009
DOI: 10.1002/jnm.725

Pages: 107-126
New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors
J. C. Tinoco, J.-P. Raskin

Published Online:  1 Sep 2009
DOI: 10.1002/jnm.726

Pages: 127-139
Modelling CoolMOSC3 transistor characteristics in SPICE
Krzysztof Górecki, Janusz Zar?bski

Published Online:  1 Sep 2009
DOI: 10.1002/jnm.727

Pages: 140-150
The compact d.c. electrothermal model of power MOSFETs for SPICE
Janusz Zar?bski

Published Online:  1 Sep 2009
DOI: 10.1002/jnm.728

Pages: 151-163
Simple and accurate approaches to implement the complex trans-conductance suited for time-domain simulators for small-signal and large-signal table-based models
Seyed Majid Homayouni, Dominique Schreurs, Bart Nauwelaers

Published Online: 15 Jan 2010
DOI: 10.1002/jnm.740

Wednesday, January 20, 2010

MIXDES 2010 paper submission deadline

The deadline for the MIXDES paper registration passes in approximately in 6 weeks (Feb 28th, 2010). The most current information about the conference, regular and special sessions invited talks etc. can be found at the in the Final Call for Papers.

This year the conference will be organized in Wroclaw, one of the oldest and most beautiful cities in Poland. It is located in southwestern Poland, 160 km from Germany and 120 km from the Czech Republic. It is well equipped with communication facilities: international airport, railways and highways, so is quite easy to get there.

As in previous years the papers should be prepared following the paper formatting requirements, however the format may be corrected till the final paper versions deadline (May 15th, 2010). The paper registration and updates should be proceeded by your personal account at the conference web page after log on.

With further questions please contact Dr. Mariusz Orlikowski, the MIXDES 2010 Conference Secretary.

MIXDES Invited Talk

Let me inform you, that the invited talk "/Ultra-thin Body SOI and Nanowire Transistors for 22nm Technology Node and Below/ " by Thierry Poiroux (Commissariat à l'Énergie Atomique, France) is announced to be held at the MIXDES'2010 Conference (http://mixdes.org/Invited_papers.htm). It could (will) be very interesting.

Saturday, January 16, 2010

Open Positions for Doctoral/Master Students on Particle Simulations of Nanostructures

at the Institute for Microelectronics, Vienna University of Technology.

Send your CV to apply@iue.tuwien.ac.at. The call is open until filling the positions.

ERC Advanced Grant an Siegfried Selberherr für Spin-Forschung

Siegfried Selberherr, Professor am Institut für Mikroelektronik der Technischen Universität (TU) Wien, wird als erster Ingenieur Österreichs mit dem „Advanced Grant“ des Europäischen Forschungsrats ERC (European Research Council) ausgezeichnet. Diese prestigeträchtige Auszeichnung ist mit einem Preisgeld von 1,7 Mio. Euro verbunden. Mit den Advanced Investigator Grants hat der ERC eine Förderschiene geschaffen, die sich an bereits etablierte WissenschafterInnen wendet. Mit den Mitteln sollen außergewöhnlich erfolgreiche ForscherInnen dazu ermutigt werden, ambitionierte Projekte mit interdisziplinärem Charakter in Angriff zu nehmen. Es gibt insgesamt sechs österreichische Staatsbürger, die mit einem Advanced Grant ausgezeichnet wurden, wobei nur vier davon in Österreich forschen. Weiters haben drei ausländische Forscher, die in Österreich tätig sind, einen Advanced Grant erhalten. [mehr]

Thursday, January 14, 2010

7th International Workshop on Compact Modeling Advance Program

Taipei International Convention Center (TICC)
Taipei, Taiwan
January 18, 2010
Advance Program available on-line

Tuesday, January 12, 2010

Job offer (PhD grant)

Title: Integrated circuit behaviour optimization based on predictive test
    - Duration three years ( it could be extended to a fourth year)
    - Salary 1300 € per month plus medical insurance
    - Support for attending conferences
    - Free registration in the Electronic Engineering Master courses, shared between the UIB and the UPC (see the web)
Requirements of the candidates:
    - Graduate on Electronic Engineering, Physics or equivalent.
    - Interested in developing a career in research
Contact: Prof. Eugenio Garcia Moreno (eugeni.garcia in the server uib.es)

The call is expected to occur in January 2010, but you can find information about the previous call (2009) about deadlines, conditions, requisites, etc. in this page.

Advances in manufacturing technologies of CMOS integrated circuits have enabled obtaining the shrinkage of the device dimensions together with higher working frequencies at the expense of a greater dispersion in their characteristics. The impact of process variations specially affects the performance specifications of the analog and RF sections.
The main objective of this project is to develop design methods that allow to construct inherently robust circuits against manufacturing process variations. We intend to approach the problem from previous results already obtained by our group in predictive test. This test strategy consists in estimating the circuit performance parameters from indirect measurements, an approach easier to implement than by means of the standard methods.
The proposed solution consists, first, in implementing the elements to carry out the test process on the own chip; this is the well-known Built in Self Test technique. Then, the results of the predictive test are used to modify, either the value of a circuit element or the own structure of the circuit, with the aim of optimizing some of their performance specifications. Hence, self-adjustable or reconfigurable circuits are obtained.
Although the concept can be applied to any anlog circuit, its implementation has to be tailored for each kind of circuits. Initially it will be applied to two circuits: a low pass filter for a RF receiver (self-tuning) and a pipeline analog to digital converter (reconfiguration). Nevertheless, all through the project we will seek new objective circuits.

Monday, January 11, 2010

The Children of Cyberspace

"The Children of Cyberspace: Old Fogies by Their 20s" By Brad Stone:
My 2-year-old daughter surprised me recently with two words: “Daddy’s book.” She was holding my Kindle electronic reader [continue reading]

Saturday, January 9, 2010

Ph D student fellowship in semiconductor device modeling

There is an open call for international fellowships to pursue a Ph D in Spain (the so-called "Becas MAE-AECID" from the Spanish Ministry of Foreign Affairs and Cooperation).

We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular III-V transistors. It will be related to two European projects in which the hosting group participates.

The duration of the grant will be 4 years. The monthly salary will be 1000 Euro/month.

Candidates cannot be Spanish citizens nor residents in Spain. However, it is required that they
have at least a basic knowledge of the Spanish language.

The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

Applicants must send to my e-mail address (benjamin.iniguez@gmail.com), and by January 17 2010, a CV together with
a copy of the academic certificates indicating the grades obtained for all subjects during their studies.

Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We are leading one European project on compact modeling of semiconductor devices (in which a total of 15 European universities and companies participate).

Additional information about the University and the department can be found at: http://www.urv.cat/ and sauron.etse.urv.es.

Friday, January 8, 2010

Semiconductors: Today & Tomorrow

Semiconductors: Today & Tomorrow is a cycle of seminars, running from January to June 2010, that bring a closer insight about trends, challenges and opportunities in semiconductor technology. Presented by expert, industry professionals the seminars seek to inspire and motivate students and professors alike into new areas of research and development, and to foster an entrepreneurial spirit that looks at emerging opportunities in the industry.

Registration on-line

Thursday, January 7, 2010

[mos-ak] C4F MOS-AK/GSA Rome Workshop

C4F MOS-AK/GSA Workshop: http://www.mos-ak.org/rome/

The IEEE Electron Devices Society is sponsoring coming MOS-AK/GSA
Workshop to be held in cooperation with the Faculty of Engineering,
Sapienza Università di Roma. The MOS-AK/GSA Workshop is HiTech forum
to discuss the frontiers of the electron devices modeling with
emphasis on simulation-aware models. Original papers presenting new
developments and advances in the compact/spice modeling and its
Verilog-A standardization are solicited. Suggested topics include (but
are not limited to):
* Compact Modeling (CM) of the electron devices
* Verilog-A language for CM standardization
* New CM techniques and extraction software
* CM of passive, active, sensors and actuators
* Emerging Devices, CMOS and SOI-based memory cells
* Microwave, RF device modeling, high voltage device modeling
* Nanoscale CMOS devices and circuits
* Technology R&D, DFY, DFT and IC Designs
* Foundry/Fabless Interface Strategies

On-line abstract submission is open with the deadline on Feb. 15, 2010

Selected best MOS-AK papers will be published in a special issue of
the Microelectronics Journal:

Further details and updates: http://www.mos-ak.org/rome/

* Tarragona: June'10 www.compactmodelling.eu
* Wroclaw: June 24-26 www.mixdes.org/Special_sessions.htm
* Seville: Sept. 18 www.mos-ak.org

Monday, January 4, 2010

RF CMOS: Oxymoron or Mainstream

Will be the RF CMOS an oxymoron or the mainstream in 2010?

(read and predict)