Sunday, 26 November 2017

[paper] Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s
Mike Brinson, and Vadim Kuznetsov
International Journal of Microelectronics and Computer Science
2017, Volume 8, Number 1 
ISSN 2080-8755 / eISSN 2353-9607

Abstract—The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It’s inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice [read more...]

Fig: EKV2.6 Qucs-S long channel static I/V model test bench and typical simulated I/V output characteristics as Qucs-S Equation-Defined Model



Saturday, 25 November 2017

Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper


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November 26, 2017 at 12:25AM
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#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf


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November 25, 2017 at 06:09PM
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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper


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November 25, 2017 at 04:31PM
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TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9


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November 25, 2017 at 06:04PM
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Friday, 24 November 2017

A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH


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November 24, 2017 at 09:39PM
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A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr


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November 24, 2017 at 09:39PM
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Tuesday, 21 November 2017

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper https://t.co/RYLH3fSGhg


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November 21, 2017 at 11:54PM
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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper


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November 21, 2017 at 11:18PM
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[mos-ak] [Final Program] 10th International MOS-AK Workshop in the Silicon Valley

10th International MOS-AK Workshop 
(co-located with the CMC Meeting and IEDM Conference) 
Silicon Valley, December 6, 2017 

Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.

Scheduled,10th subsequent MOS-AK modeling workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
<http://www.mos-ak.org/silicon_valley_2017/>

Venue: 
Cadence Design Systems 
2655 Seely Ave
San Jose, CA 95134
Building 5 (map)

Online Workshop Registration is still open
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
WG211117

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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC


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November 21, 2017 at 04:49PM
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2


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November 21, 2017 at 04:48PM
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Thursday, 16 November 2017

#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ


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November 16, 2017 at 12:54PM
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Innovations in Electronics and Communication Engineering

Proceedings of the Fifth ICIECE 2016
Volume 7 of Lecture Notes in Networks and Systems
H. S. Saini, R. K. Singh, K. Satish Reddy
Springer, 8 Nov 2017 - Technology & Engineering - 596 pages
ISBN 9811038120, 9789811038129

The book contains high quality papers presented in the Fifth International Conference on Innovations in Electronics and Communication Engineering (ICIECE 2016) held at Guru Nanak Institutions, Hyderabad, India during 8 and 9 July 2016. The objective is to provide the latest developments in the field of electronics and communication engineering specially the areas like Image Processing, Wireless Communications, Radar Signal Processing, Embedded Systems and VLSI Design. The book aims to provide an opportunity for researchers, scientists, technocrats, academicians and engineers to exchange their innovative ideas and research findings in the field of Electronics and Communication Engineering [read more...]

Tuesday, 14 November 2017

The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM


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November 14, 2017 at 10:45PM
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3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X https://t.co/V68oi64jF3


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November 14, 2017 at 10:38AM
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7th All-Russian Workshop on CAD of IC Design

7th All-Russian Workshop on computer aided design (CAD) of integrated circuits (IC) to be held at NRNU MEPhI on December 12-14, 2017. The free workshop is organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information about the Workshop is available via site cad.mephi.ru.

Program 
(with timetable and detailed information in pdf format)
12 December 2017
08:45 - 09:15Registration (University entrance)
09:30 - 13:00Conference hall 3rd floor of the main lecture building
- Synthesis in Genus (28nm technology)
- Introduction to Joules
- Innovus 17.1 Topical Introduction
13:00 - 14:00
Lunch break
14:00 - 18:15Conference hall 3rd floor of the main lecture building
- Introduction to Stylus
- Physical verification with the help of PVS
- A new generation of verification software - Xcelium and Indago
- The history and future of megatrends in EDA
13 December 2017
9:00 - 18:00
Laboratory V-315 of the Department of Electronics
(Practical classes)
- Behavioral modeling
- Logical synthesis
- Simulation of a Verilog modules with element delays
- Physical design of the digital modules
- Verification of the digital modules
14 December 2017


10:00 - 12:00Laboratory V-315 of the Department of Electronics
- Working discussions, summarizing

Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597

Saturday, 11 November 2017

#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2


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November 11, 2017 at 07:15PM
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#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr


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November 11, 2017 at 09:39AM
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Tuesday, 7 November 2017

ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD


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November 07, 2017 at 08:36PM
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Monday, 6 November 2017

A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper


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November 06, 2017 at 08:26PM
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Friday, 3 November 2017

[paper] Validation of MOSFET Model Source–Drain Symmetry

Validation of MOSFET Model Source-Drain Symmetry
Colin C. McAndrew
IEEE TED, Vol. 53, No. 9, Sep. 2006
doi: 10.1109/TED.2006.881005

Abstract: Symmetry around Vds= 0 is a critical requirement for MOSFET models, e.g. as it affects the ability of a model to simulate distortion accurately for some RF CMOS mixers. The Gummel symmetry test (GST) has been the standard test used to evaluate the symmetry of MOSFET models. However, this test is only applicable to DC current, and is only valid when there is negligible gate or substrate current. This paper presents a DC symmetry test that is applicable in the presence of gate and substrate currents, and an AC symmetry test that is simple and effective in verifying symmetry of Cgs and Cgd.


FIG: Biasing scheme for dc symmetry testing. 

Thursday, 2 November 2017

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx


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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb


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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27


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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R


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November 02, 2017 at 10:04AM
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