eSim 2.6 Release

A Big Milestone for FOSSEE eSim - eSim 2.6 IS HERE!

The release of eSim 2.6 is bringing exciting improvements, enhanced workflows, and new capabilities to our open-source Electronic Design Automation (EDA) tool developed by the FOSSEE Project, IIT Bombay.

Download eSim 2.6: https://esim.fossee.in/downloads
Explore eSim 2.6 Release Notes: https://github.com/FOSSEE/eSim/releases/tag/v2.6

What's New in eSim 2.6?

• Refreshed User Interface
• Enhanced Simulation and Waveform Analysis
• Improved HDL Workflows and Icarus Verilog Support
• Compatibility with Newer KiCad Versions
• IHP OpenPDK Support
• Native Windows Installer
• Reduced Installer Size
• OpenROAD Integration (Work in Progress)

Celebrating the Team Behind the Release:

A special shout-out to Varadha RS, Akshat Sharma, and more than 100 hardworking interns for their dedication and contributions to eSim 2.6. From implementing new features and resolving issues to testing workflows and improving usability, their efforts have helped bring this release to life.

A heartfelt thank you to all eSim and FOSSEE team members for their invaluable contributions, technical expertise, guidance, and continued support. Every contribution matter, and milestones like this are the result of collaboration, persistence, and teamwork.

Acknowledging Our Supporters

Our sincere gratitude goes to the FOSSEE Project, Indian Institute of Technology Bombay, National Mission on Education Through ICT (NMEICT), and the Ministry of Education, Government of India, New Delhi, for their continued support in advancing open-source engineering tools and education.

Building the Future of Open-Source EDA

At FOSSEE, IIT Bombay, we are committed to making circuit design, simulation, PCB design, and semiconductor design more accessible through open-source technologies.

Thank you to everyone who has been part of this journey. Special thanks to our collaborators and the wider open-source community:

• Wladek Grabinski, 
• Steve Hoover, 
• Indira Iyer Almeida
• OpenPDK IHP - Leibniz Institute for High-Performance Microelectronics
• The OpenROAD Project

APCI Program: SBMicro Projects

APCI Program

Support for SBMicro Integrated Circuit Projects

TAB: Universities Involved in IC Design and EDA/CAD Tool Development

University	#Profs	#PhDs	#MSCs
CEFET-MG - Centro Federal de Educação Tecnológica de Minas Gerais	8	0	3
CEFET-RJ - Federal Center for Technological Education Celso Suckow da Fonseca	2	1	0
FEI - Centro Universitário da FEI	2	0	3
FURG - Universidade Federal do Rio Grande	3	1	1
IFSP - Instituto Federal de São Paulo	5	0	0
ITA - Instituto Tecnológico de Aeronáutica	10	0	5
PUCRS - Pontifícia Universidade Católica do Rio Grande Do Sul	8	15	9
UCPEL - Universidade Católica de Pelotas	3	0	6
UEA - Universidade do Estado do Amazonas	1	0	0
UERGS - State University of Rio Grande do Sul	5	0	0
UFABC - Federal University of ABC	6	0	2
UFAM - Universidade Federal de Manaus	4	4	0
UFBA - Universidade Federal da Bahia	5	13	8
UFC - Universidade Federal do Ceará	3	5	3
UFERSA - Mossoró	1	0	4
UFERSA - Pau dos Ferros	5	1	3
UFG - Federal University of Goiás	8	1	0
UFMG - Universidade Federal de Minas Gerais	6	3	9
UFPB - Universidade Federal da Paraíba	1	1	2
UFPEL - Universidade Federal de Pelotas	13	13	2
UFPR - Universidade Federal do Paraná	7	2	5
UFRGS - Universidade Federal do Rio Grande do Sul	17	32	45
UFRJ - Federal University of Rio de Janeiro	6	2	4
UFRN - Federal University of Rio Grande do Norte	4	3	2
UFS - Universidade Federal do Sergipe	3	0	1
UFSC - Universidade Federal de Santa Catarina	11	12	11
UFSM - Universidade Federal de Santa Maria	8	0	5
UFV - Universidade Federal de Viçosa	2	3	3
UNB - Universidade de Brasília	9	3	9
UNESP - Universidade Estadual Paulista	4	0	1
UNICAMP - Universidade Estadual de Campinas	8	16	21
UNIFEI - Universidade Federal de Itajubá	7	2	3
UNIFEI - Itabira	3	0	3
UNIPAMPA - Universidade Federal do Pampa	4	0	2
UNISANTOS - Universidade Católica de Santos	1	0	0
UNISINOS - Universidade do Vale do Rio dos Sinos	3	0	3
UNIVALI - Universidade do Vale do Itajaí	3	0	3
USP - Universidade de São Paulo	8	1	12
USP-EESC - Escola de Engenharia de São Carlos	3	1	2
UTFPR - Universidade Tecnológica Federal do Paraná	1	0	0

[REF] Report: Strengthening EU-Brazil bilateral know-how of semiconductor sector technologyand possibilities for cooperation on trade and R&D (July 2023)

[OpenPDK] GT2N

This the initial release for the GT2N PDK with 72 standard cells: <https://github.com/azadnaeemi/GT2N>.

It is based on 2nm GAAFET with BSPDN. All the device models are based on 3-stack nanosheets

Standard cell layouts can also be imported using the .gds file: GT2N/gds/gt2_6t_std_cells.gdsLVS and DRC rulesets for icvalidator are present in "GT2N/icv_runset".
Libraries are composed of 3 process corners (under development), 2 nanosheet width (W) flavors, and 5 threshold voltage (VT) flavors. (In the order of decreasing VT, HVT > SVT > LVT > ULVT > ELVT)

The collaterals required for synthesis and PnR are (depending on the process corner and W/VT flavor):

LIB: GT2N/lib/tt/gt2_6t_w31_lvt_tt_0p7v25c.lib
LEF: GT2N/lef/tt/gt2_6t_w31_lvt.lef
Techlef: GT2N/techlib/gt2_tech.lef
ICT: GT2N/qrc/GT2.ict
QRCTech: GT2N/qrc/GT2_qrc.tch
ITF: GT2N/nxtgrd/GT2.itf
NXTGRD: GT2N/nxtgrd/GT2.nxtgrd

The thermal-calibrated GAAFET (3-stack nanosheet) model card is (depending on the process corner and W/VT flavor):

GT2N/device/tt/gt2_w31_lvt_tt.sp

[ref] D. Jang, P. Kumar, M. N. H. Shazon, S. J. Ram, A. Svizhenko, V. Moroz, A. Ceyhan, N. A. Radhakrishn, and A. Naeemi, "GT2N: An Open-Source 2nm Nanosheet PDK Enabling Multi-Width/VT Benchmarking" in IEEE International Symposium on Circuits and Systems (ISCAS) 2026  

[ICTA2026 ] Special OpenPDK Session

IEEE International Conference on Integrated Circuits, Technologies & Applications

ICTA 2026 Special Session “OpenPDK - Global FOSS Scholar Platform"

21st - 24th (Wed - Sat) October 2026

Grand Copthorne Waterfront Hotel, Singapore

The OpenPDK initiative delivers a global FOSS Scholar Platform supporting analog/RF, mixed‑signal, and digital IC design. Central to this effort are accurate SPICE models for low‑power sensing MOSFETs, RF HBTs, and emerging RRAM devices, validated across cryogenic temperatures for space and quantum‑computing applications. The initiative also advances Verilog‑A compact‑model standardization, ensuring result reproducibility and seamless integration into open‑source design flows. Supported by the EU Chips JU, OpenPDK fosters collaboration among academia, startups, and industry, while providing FOSS IC‑design tools covering schematic capture, simulation, layout, and verification up to tape‑out. Similar to the EU Chips JU program, Zhejiang CoreXin in China offers an open‑source PDK together with tape‑out services for its 55nm CMOS process. To accelerate the semiconductor‑industry development across the Asia‑Pacific and Southeast‑Asia regions, semiconductor model development and parameter extraction techniques should be pursued in a more focused manner. This special session brings together experts to present and discuss advances in device characterization, compact modeling, simulation methodologies, and validation techniques for a broad range of solid‑state devices, including Si, III/V semiconductors, power devices, nanoscale structures, and emerging 2.5D/3D advanced packaging technologies [ read more...]

ICTA 2026 Special OpenPDK Session Presenters

• SPICE/Verilog-A standard models and OpenPDK practice
  Wladek Grabinski, GMC Consulting, Switzerland
• Open-Source Ecosystem Updates and Semiconductor Design Development Programs in Japan
  Jun-ichi Okamura, AIST Solutions, OpenSUSI, Japan
• Open-Source EDA Meets Industrial IC Design
  Ehrenfried Seebacher, ams-OSRAM AG, Austria
• Building an Open-Source Process Platform, Empowering VLSI Innovation and Development
  Da Zhang, Zhejiang University/CTO, Zhejiang Chuangxin Integrated Process Platform, China
• From Silicon to Design: Intelligent Measurement and Modeling for DTCO
  Yutao Ma, VP of R&D, Primarius Technologies. Ltd. China
• Beyond Moore, Application-Driven IC Innovation International Cooperation Opportunities at NICE
  Alex Gu, National Innovation Center Par Excellence (NICE), China
• 2.5D/3D IC: AI+EDA Reshaping the System-Design-Technology Co0ptimization (STCO) Paradigm for Advanced Packaging
  Alex Zhao, Founder/CEO Zhuhai SiChip Technology Co., Ltd., China
• Modelling of semiconductor devices: the heart of innovation bridging academia and industrial applications
  Fujiang Lin, University of Science and Technology of China (USTC), China

Special OpenPDK Session progeam include the panel discussion: 

How to have a close loop for PDK, EDA, PDA and ICS simulation?

[ read more...]

Schematic to Silicon with Mini MOSbius

Zero To ASIC Course and Tiny Tapeout by Matt Venn

Schematic to Silicon with Mini MOSbius 

https://www.youtube.com/watch?v=NM5cLWYWqG0

Take Matt Venn TT course: 

https://www.zerotoasiccourse.com/

Buy a copy of Mini MOSbius, part of the TT IP library, here: 

https://store.tinytapeout.com/products/TTSKY25b-Development-Kit-p849160072

Check the configurator: 

https://github.com/mattvenn/mini-mosbius-configurator

Mini MOSbius is available on these chips

• [OK] TTSKY25a - delivered July 2026 - available in the store
• [OK] TTSKY25b - delivered August 2026 - available in the store
• TTSKY26b - tapeout May 2026
• TTSKY26c - tapeout September 2026
• GF180 - will be taped out December 2026

and finally check out the original MOSBius: https://mosbius.org/ If you are interested to acquire MOSbius kits, review the express license and email Peter Kinget for kit availability before placing an order.

[paper] Open Source EZ130 8T standard cell library

Oscar Castaneda, Lavinia Recchioni, Tobias Senti, Flurin Cahenzli, Marco Ferroni, Thorben Heekenjann, Robert Kenter, Stefan Odermatt, Daniel Richner, Gabriel Altendorfer, Davide Cannone, Miguel Correa, Ivan Herger, Lars Kroger, Nicolas Nanzer, Darja Nonaca, Christopher Reinwardt, Lukas Winklhofer, Enrico Zelioli, Yiheng Zhang, Yingxue Zhang, Domenic Keller, Seyed Hadi Mirfarshbafan, Zerun Jiang, Beat Muheim, Arianna Rubino, Jeremy Guichemerre, Frank K. Gurkaynak, and Christoph Studer

An Open-Source Standard-Cell Library for IHP 130 nm Developed by Students

arXiv:2609.29965v1 [cs.AR] 24 Sep 2026

1. Department of Information Technology and Electrical Engineering, ETH Zurich, Switzerland

* The open-source EZ130 8T standard-cell library is available at https://ez.ethz.ch

Abstract: Standard-cell libraries form the critical interface between transistor-level circuit design and automated digital design flows, yet their design and characterization are rarely covered in depth in digital VLSI courses. This paper presents VLSI 5, a graduate-level course at ETH Zurich in which students design, lay out, characterize, and integrate their own standard cells using IHP’s open-source 130 nm SG13G2 process design kit. In the first course offering, 19 students developed EZ130 8T, an open-source eight-track standard-cell library comprising 220 cells. We evaluate successive library versions using eight synthesis benchmarks, across which EZ130 8T achieves significant area reduction compared to the SG13G2 library at competitive timing. For a postlayout 8×8 matrix-vector multiplier, EZ130 8T reduces cell area by 35% and energy by 39% while maintaining virtually the same clock period. The library has already been adopted in other ETH Zurich VLSI courses, enabling the creation of chips entirely designed by students down to the transistor level.

FIG: a.) ETH Zurich course series on digital VLSI design. By teaching students to create a standard-cell library, the new VLSI 5 course closes the gap between transistor-level and HDL-level IC design;
b.) and c.) Layout of two example standard cells from the EZ130 8T library.

Aknowlegements: This work has received funding from the Swiss State Secretariat for Education, Research, and Innovation (SERI) under the SwissChips initiative. The authors thank Cadence for their support by providing licenses to design and characterize the EZ library. The authors also thank H. Pretl, T. Benz, and P. Sauter for their feedback on preliminary versions of the EZ library.

[webinar] Colombia in OpenSilicon Age

IEEE SSCS: Colombia in OpenSilicon Age

• Date: Thursday, October 8, 2026
• Time: 1:00 PM – 2:30 PM (Colombia, GMT-5)
• Platform: Cisco Webex
• Access: Free/Open access

This open online event is the first IEEE SSCS Colombia session. It shares a vision for creating a strong microelectronics ecosystem in Colombia by bringing universities and industry together and helping develop highly skilled engineers. The event will review the current state of microelectronics in Colombia, discuss the future of integrated circuit (IC) design, present recent semiconductor policy initiatives, and explain the goals of the IEEE SSCS Colombia chapter. Speakers from Colombia and abroad will share their experience in IC design, open-source silicon, semiconductor education, and industry development. The session aims to encourage collaboration between academia, industry, and government to support the growth of the semiconductor sector in Colombia.

Featured Panelists and Keynote Speakers

• Made in Colombia: Review of Colombian Microelectronics
  Javier Ardila, Onsilicon, UIS and President, IEEE SSCS
• ColombiaThe Global Map of CI Design: Tools, Foundry and Methodology
  Hugo Hernández, Teradar, Boston, MA
• OpenSilicon Opportunities
  Fernando Guarín IEEE Division 1
• Bill for the promotion of the electronics and semiconductor industry
  Lorena García Founder, Colombian Network of Electronics and Semiconductors

[FOSS] AI IC Designs

Harald Pretl, Kevin Cameron, Jun‑ichi Okamura

FOSS AI IC Designs Examples

Intensive work over last three months was carried out by Prof. Harald Pretl together with an AI coding agent, thru which a substantial chip‑design knowledge base was built. At this stage, the AI agent is able to design, simulate, and layout a low‑noise, low‑voltage bandgap reference plus LDO with minimal manual intervention (along with many additional circuits that will be showcased later). The rapid progress in capability development is highly impressive.

The entire implementation was performed in OpenPDK 130nm CMOS using IIC‑OSIC‑TOOLS with almost no human involvement. The resulting layout is densely packed, the floorplan is coherent, and a manually created version would not differ significantly. Dummy structures were inserted for matching, and common‑centroid placement was applied to critical MOSFET devices.

Significant progress has also been achieved by Kevin Cameron, primarily on the simulation side, covering complete digital and AMS/RF domains. The work described in the linked repository has been developed and advanced accordingly, with sv2ghdl, which translates SystemVerilog RTL into VHDL for use with GHDL and NVC simulators. The generated VHDL leverages simulator extensions that go beyond what SystemVerilog offers, including multi‑UDN wires, bidirectional components, and improved unknown‑state handling

<https://github.com/kev-cam/sv2ghdl/blob/main/README.md>

A beta version of an automatic P&R tool for the OpenPDK TR‑1um was developed by Jun‑ichi Okamura using Claude AI and FOSS KLayout API and accompanying verification scripts. The flow is based on the newly updated standard‑cell library, incorporating both LEF and Liberty files, and STA analysis is now supported. Regression testing was carried out on three designs: I²C, SPI, and TD4

<https://lnkd.in/gMy3ThYm>

The synthesis and automatic P&R of TD4, an educational 4‑bit CPU, were completed by Jun‑ichi Okamura using Claude AI and the OpenPDK TR‑1um flow. A custom 8×16 register file was designed, the standard‑cell height was reduced, and a simplified Liberty (.lib) file was created to enable static timing analysis. The final chip implementation is made up of 4225 devices.

[ICMC] 2026 Award Winners

Thank you to all of the great paper and poster presentations at ICMC 2026!

Below the ICMC 2026 Best Paper Award Winners:

• Best Paper Award
  Zhengxing Zhang & Substitute Presenter Xu Wang
  Cadence Design Systems, Port Moody, Canada
  “Compact Time-Domain Modeling of Parameterized Frequency-Dependent Photonic Components in Verilog-A”
• Best Student Paper Award
  Tasnia Jahan
  Arizona State University, Tempe, USA
  “Physics-Informed Neural Networks for Predicting Characteristics of β-Ga2O3 based Devices”
• Best Poster Award
  Dylan Ma & Substitute Presenter Lan Wei
  University of Waterloo, Waterloo, Canada
  “Virtual-Source-Based Cryogenic FET Model”

and more ICMC2026 photos

[release] IHP Open ADK

IHP Open Assembly Design Kit 

(#OpenAKD)

https://github.com/IHP-GmbH/IHP-Open-ADK

is preview ready and officially available on the IHP GitHub. This release comes with several tools to enable the workflow, including the IHP open source interposer technology process (OpenIntM4TM2). It is Assembly-level Design Kit (OpenADK) for heterogeneous chiplet integration. The OpenADK operates one abstraction layer above all process‑specific PDKs, providing the rule set and assembly tooling that define chiplet placement, routing, and interposer‑level connectivity. The interposer and the chiplet dies remain ordinary PDKs.

Status Warning ADK is currently a preview release only! v0.2.0. The KLayout assembly DRC, its runner, the KiCad DRU generator, and the IHP interposer adapter are implemented and exercised by the regression suite.

● Current ADK documentation

https://ihp-open-adk-docs.readthedocs.io/en/latest/index.html

● Quick start ADK commands

https://ihp-open-adk-docs.readthedocs.io/en/latest/quickstart.html

[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[VACASK] device-level transient noise analysis

VACASK, a free and open-source analog circuit simulator, now does device-level transient noise analysis. As far as I know, this is a first among FOSS circuit simulators. Ngspice has had source-based transient noise for a while, but the user has to wire noise sources into the circuit by hand. In VACASK, every resistor, diode, and transistor contributes its own white (thermal and shot) and flicker (1/f) noise automatically during the transient run, the way Spectre and other commercial RF simulators do it.

Why it matters: this lets you actually see how noise shapes the behavior of oscillators, PLLs, mixers, and sampling circuits in the time domain, not just as an abstract spectral quantity.

Quick demo on an LC oscillator at fosc=245kHz:

Top: power spectral density of the output

Middle: single-sideband phase noise (SSB PSD)

Bottom: phase jitter accumulating over time

Having this in a FOSS tool opens the door for students, hobbyists, and researchers to run the same analyses that were previously gated behind five and six-figure licenses.

Árpád Bűrmen, the lead VACASK developer, would love to hear from anyone working on analog/RF simulation. 

What would you put it through first?

https://codeberg.org/arpadbuermen/VACASK

#OpenSource #AnalogDesign #CircuitSimulation #RFDesign #EDA

[OpenSUSI] Kicks off Five-Year Plan

Industry-Academia Collaboration Project Launches for Real Chip Manufacturing 

Using NDA-Free PDK - Tokai Rika, Kyushu University, AIST Solutions, 

OpenSUSI Kicks Off Five-Year Plan for FY2026

Tokai Rika Co., Ltd., Kyushu University, AIST Solutions Co., Ltd., and OpenSUSI have announced a joint project on a five-year plan to develop semiconductor human resources and verify their implementation through industry-academia collaboration to actually manufacture chips using PDK (Process Design Kit) that does not rely on NDAs (non-disclosure agreements). The 2026 launch ceremony was held. The biggest feature of this project is that it allows students to experience a series of processes from design to chip manufacturing under an open design environment using NDA-free PDKs #OpenPDKs

Positioning and future development in FY2026 as the first year that this project will be fully developed over a five-year span. Based on an open design and manufacturing environment utilizing NDA-free PDK #OpenPDK, we will continue and develop the following initiatives:

• Continuation and advancement of hands-on semiconductor human resource development
• Providing opportunities for actual chip manufacturing and verification using NDA-free PDK
• Building a practical and highly reproducible education and implementation model through industry-academia integration
• In exchange for the cost support for this program, we will embed the company's logo on the prototype chip to spread awareness of semiconductor design human resource development as a social contribution activity

(From left) Junichi Okamura, Representative Director of OpenSUSI, 

Haruichi Kanaya, Professor of Kyushu University, 

Taketoshi Sakurai, Executive Officer of Tokai Rika, 

and Seiji Osaka, President and CEO of AIST Solutions

If you are interested or interested in this matter, please contact us at:

OpenSUSI Secretariat <secretary@opensusi.org>

 

[DATE2026] Open Source Related Talks

DATE 2026 Verona, Italy

Open Source Related Talks

Monday, 20 April - Wednesday, 22 April 2026

<https://date26.date-conference.com/programme>

Label	Title	Authors
TS02.8	ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA	Quinten Norga; Suparna Kundu; Ingrid Verbauwhede
LK03	Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap	Luca Benini
TS10.1	PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration	Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang
TS16.1	Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform	Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai
LBR01.4	Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators	Katharina Ruep, Manfred Schlaegl and Daniel Grosse
LBR01.7	Hybrid Virtual Platform + FPGA Co-Emulation Framework	Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari
TS20.1	Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware	Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao
TS21.4	Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators	Rahul Kumar; Rohan Kumar; Borivoje Nikolic
SD03	Open-Source Hardware Landscape
SD03.1	Open Silicon Fabrication – Made in Europe	Gerhard Kahmen, IHP GmbH, DE
SD03.2	From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows	Harald Pretl, JKU Linz, AT
SD03.3	Bringing Software Design Thinking To Chip Design	Tomi Rantakari, ChipFlow, GB

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen

[mos-ak] [OpenPDK] IHP Analog Academy

IHP Analog Academy

https://lnkd.in/eQnNX4ug

We, IHP Analog Academy, are excited to present this deep dive into analog, RF, and mixed-signal IC design, powered by open-source FOSS CAD/EDA tools and the IHP Open PDK.

This hands-on course is designed for engineers, researchers, and students eager to gain practical experience with the SG13G2 process at the 130nm technology node. Originally hosted on-site at IHP in Frankfurt (Oder), participants spent five intensive days exploring everything from fundamental analog simulation to advanced RF, 3D EM modeling, and mixed-signal integration. And now we're excited to release it to the open-source community!

The course covers:

- Bandgap reference design and simulation using the gm/Id methodology

- RF design of a 50 GHz Medium Power Amplifier with EM simulation

- Mixed-signal integration and verification of an 8-bit SAR ADC

Each module emphasizes a real-world design flow using tools like:

ngspice, Xyce, KLayout, OpenEMS, QUCS, and Python for data analysis.

Over time, we will expand the repository with:

- More modules

- Updated toolchain support

- Improvements to existing flows

Explore the IHP Open PDK:

- Open PDK GitHub Repository https://github.com/IHP-GmbH/IHP-Open-PDK 

- Interactive Help via ChatGPT https://chat.openai.com

Note: This is not an introductory IC design course. A basic understanding of electronics and microelectronics is assumed. We're proud to contribute this initiative to the community to help lower the barrier to IC design using open-source tools. We encourage contributions via GitHub Issues or Pull Requests! Your feedback and contributions, are welcome!

Lead Author: Phillip Ferreira Baade-Pedersen

Co-Author: Christian Wittke

The Development of this course is funded by the public German project FMD-QNC (16ME083) from BMFTR (Federal Ministry of Research, Technology and Space / Bundesministerium für Forschung, Technologie und Raumfahrt): https://www.elektronikforschung.de/projekte/fmd-qnc

#opensource #analog #mixedsignal #rf #design

[paper] FOSS support for CM with Verilog-A

Bűrmen, Árpád, Tadej Tuma, Iztok Fajfar, Janez Puhan, Žiga Rojec, Matevž Kunaver

and Sašo Tomažič

Free software support for compact modelling with Verilog-A

Informacije MIDEM 54, no. 4 (October 9, 2024)

<https://ojs.midem-drustvo.si/index.php/InfMIDEM/article/view/1999>

Abstract: Verilog-A is the analog subset of Verilog-AMS - a hardware description language for analog and mixed-signal systems. Verilog-A is commonly used for the distribution of compact models of semiconductor devices. For such models to be usable a Verilog-A compiler is required. The compiler converts the model equations into a form that can be used by the simulator. Such compilers have been supplied with commercial simulators for many years now. Free software alternatives are much more scarce and limited in the features they offer. The paper gives an overview of Verilog-A, Free software Verilog-A compilers, and Free software/Open source simulators that can simulate compact models defined in Verilog-A. Advantages and disadvantages of individual compilers and simulators are highlighted.

Tab: Comparison of Free software simulators

Asterisk denotes a feature under development as of Sep. 2024

Acknowledgements: This research was funded in part by the Slovenian Research Agency within the research program ICT4QoL—Information and Communications Technologies for Quality of Life, grant number P2-0246.

[FOSSEE] Better Education

FOSSEE (Free/Libre and Open Source Software for Education) project promotes the use of free open source software (FOSS) tools in academia and research. The FOSSEE project is part of the National Mission on Education through Information and Communication Technology (ICT), Ministry of Education (MoE), Government of India. 

Below is the list of projects which are promoted by FOSSEE.

• Scilab 
  free/libre and open source software for numerical computation developed by Scilab Enterprises, France. Scilab also includes Xcos which is an open source alternative to Simulink.
• Python 
  general-purpose, high-level, remarkably powerful dynamic programming language that is used in a wide variety of application domains. It supports multiple programming paradigms.
• eSim 
  (formerly known as Oscad/FreeEDA) is an EDA tool for circuit design, simulation, analysis and PCB design. It is developed by the FOSSEE team at IIT Bombay 
• Osdag 
  free/libre and open-source software which allows the user to design steel structures using a graphical user interface. The GUI also provides 3D visualization of the designed component and images
• DWSIM 
  free/libre and open source CAPE-OPEN compliant chemical process simulator. Helps understand the behavior of Chemical Systems by using rigorous thermodynamic and unit operations models.
• OpenFOAM 
  free/libre and open source CFD toolbox useful to solve anything from complex fluid flows involving chemical reactions, turbulence and heat transfer, to solid dynamics and electromagnetics.
• OpenModelica 
  free/libre and open source environment based on the Modelica modelling language for modelling, simulating, optimising and analysing complex dynamic systems.
• OpenPLC 
  free/libre and open source Programmable Logic Controller creating opportunities for people to study its concepts, explore new technologies and share the resources.
• FLOSS-Arduino
  control of Arduino using Free/Libre Open-Source Software. The interface helps the user to perform embedded systems experiments on the Arduino Uno board.
• SBHS
  (Single Board Heater System) is a lab-in-a-box setup useful for teaching and learning control systems.
• R 
  programing language and environment for statistical computing and graphics.
• QGIS
  (Quantum GIS) is a free and open-source desktop Geographic Information System (GIS) application.
• FOCAL 
  an initiative by FOSSEE to promote Open Source Software in computer graphics.
• SOUL
  (Science OpensoUrce Software for Teaching Learning) is a collection of ICT software that can be used as teaching/learning tools by the community of educators and the learners to teach/ learn the basic as well as the advanced concepts in science subjects

SSCS April Technical Webinar

SSCS April Technical Webinar

Getting Started with Open Source Silicon, Presented By: Matthew Venn

Abstract: In this presentation, Matt Venn will share his experience of getting started with chip design using the free and open source tools. Going from zero to 20 chips in 3 years, there are plenty of successes and failures to share. Matt will then move on to sharing the best resources, inspirational example projects, and showcase some of his own tools. The presentation will finish with a demonstration showing just how easy and cheap it is to get your own chip manufactured today.

Biography: Matt Venn is a science & technology communicator and electronic engineer. He has been involved with open source silicon for the last 3 years and has sent 20 chips for manufacture. He has helped over 600 people learn the tools, with 300 people taking part in manufacturable designs:

• https://zerotoasiccourse.com/
• https://tinytapeout.com

Date: 2024-04-19 Time: 11 AM ET

Location Webinar - Online

Contact Aeisha VanBuskirk – a.vanbuskirk@ieee.org

Register Here

[paper] Open-source design of integrated circuits

Patrick Fath, Manuel Moser, Georg Zachl. Harald Pret

Open-source design of integrated circuits

Elektrotech. Inftech. (2024)

DOI: 10.1007/s00502-023-01195-5

* Institute for Integrated Circuits, Johannes Kepler University Linz, Austria

Abstract: This paper presents the design of a self-clocked 12-bit non-binary fully differential SAR-ADC using the SKY130 open-source PDK. The entire mixed-signal circuit design and layout were created with free and open-source software. The ADC reaches a sample rate of up to 1.44MS/s at 1.8V supply while consuming 703μW of power on a small 0.175mm area. A configurable decimation filter can increase the ADC resolution up to 16 bits while using an oversampling factor of 256. A 9‑bit thermometer-coded and 3‑bit binary-coded DAC matrix using a 448 aF waffle-capacitor results in a total capacitance of 1.83pF per input. Realizations of configurable analog functions using the form factor of SKY130 high-density standard cells allow the parametrization of an analog circuit in a hardware description language and hardening of the macro in an intentionally digital workflow.

FIG: Block diagram of the proposed open-source design flow,

including the essential tools and used/generated files

Acknowledgements: The authors thank Johannes Kepler University for funding the open-access publication, Google and SkyWater Technologies for igniting this recent wave of open-source IC design, and the large crowd of enthusiasts spending their time on developing and maintaining an extensive array of exciting open-source EDA projects. Open access funding provided by Johannes Kepler University, Linz.