Wednesday, March 19, 2008
Charge transport in boron-doped nano MOSFETs: Towards single-dopant electronics
Applied Surface Science, In Press, Accepted Manuscript, Available online 12 March 2008
Y. Ono, M.A.H. Khalafalla, K. Nishiguchi, K. Takashina, A. Fujiwara, S. Horiguchi, H. Inokawa and Y. Takahashi
Tuesday, March 18, 2008
Quoting Rudy Lauwereins, Vice President Nomadic Embedded Systems at IMEC:
"Up to now, most variability characterization work is done internally at IDMs on own technology and IP blocks. However, with the move to fabless and fablite companies, we want to bridge the gap between foundry and fabless companies on design-level impact of using most advanced semiconductor technologies. To this end, we invite IDMs, fabless system companies, fabless digital IP providers and foundries to collaborate within our Technology-Aware Design program to develop the necessary tools for designing reliable systems with variable and unreliable components. IMEC’s program is compatible with confidentiality constraints for high value proprietary IP blocks."
Monday, March 17, 2008
Drift mobility and the frequency response of diode connected organic transistors, Brian Cobb, Yeon Taek Jeong, and Ananth Dodabalapur
Effects of substrates on photocurrents from photosensitive polymer coated carbon nanotube networks, Yumeng Shi, Hosea Tantang, Chun Wei Lee, Cheng-Hui Weng, Xiaochen Dong, Lain-Jong Li, and Peng Chen
Determining the interfacial density of states in metal-insulator-semiconductor devices based on poly(3-hexylthiophene), N. Alves and D. M. Taylor
Carrier trapping and scattering in amorphous organic hole transporter, K. K. Tsung and S. K. So
Thursday, March 6, 2008
Title: New Challenges in MOS Compact Modeling for Future Generation CMOSPresenter: Xing Zhou
School of Electrical & Electronic Engineering
Nanyang Technological University
50 Nanyang Avenue,
Where: EPFL, Building CO, Room CO016 (http://plan.epfl.ch)
When: Tuesday, March 11, 2008, 17h00
Abstract: As bulk-MOS technology is approaching its fundamental limit, non-classical devices such as multiple-gate (MG) and silicon-nanowire (SiNW) transistors emerge as promising candidates for future generation device building blocks. This trend poses new challenges to developing a compact model suitable for these new device structures and requires a paradigm shift in the core model structure. Conventional bulk-MOS models are based on four-terminal unipolar conduction in a doped channel with ideal symmetrical PN-junction source/drain contacts. In MG/NW MOSFETs, however, the device becomes three-terminal with undoped channel and possible bipolar conduction, and source/drain contacts become an integral part of intrinsic channel. Source/drain asymmetry, either intentional or unintentional, in a theoretically symmetric MOSFET also becomes important to capture in a compact model, which is nontrivial in a model that depends on terminal source/drain swapping at the circuit level. In this talk, after a brief review of the history of compact model development and various approaches, we discuss these new challenges and demonstrate solution methods based on the unified regional modeling (URM) approach.
Bio: Xing Zhou received the B.E. degree from Tsinghua University, Beijing, China, in 1983, and the M.S. and Ph.D. degrees in electrical engineering from the University of Rochester, Rochester, NY, in 1987 and 1990, respectively. From 1990 to 1991, he was a research associate in the Department of Electrical Engineering, the University of Rochester, where he worked on hot-carrier injection phenomena in MOS devices, as well as development of CAD tools for mixed-signal circuit simulation. From 1992 to 1995, he was a research fellow in the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, where he worked on Monte Carlo and numerical modeling of semiconductor and optoelectronic devices as well as mixed-signal circuit modeling and simulation. He is currently a tenured associate professor in the same school at NTU, as well as program director and lab supervisor of the computational nanoelectronics group. His current research focuses on development of compact models for circuit simulation for conventional and emerging nanoscale MOS devices. In November and December of 1997 as well as in February and March 2001, he was a visiting fellow at the Center for Integrated Systems, Stanford University, California. In January 2003, he was a visiting professor at Hiroshima University, Japan. In May 2007, he was a visiting professor at Universiti Teknologi Malaysia. He is the founding chair of the Workshop on Compact Modeling (WCM) in association with the Nano Science and Technology Institute (NSTI) Nanotech Conference since 2002. He was the recipient of the 2006 NSTI Fellow award.
Dr. Zhou is an elected member of the IEEE Electron Devices Society (EDS) Administrative Committee, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters, a member of the EDS Compact Modeling and VLSI Technology and Circuits technical committees as well as the Membership, Publications, and Educational Activities committees, and an EDS newsletter editor for Region 10 (Australia, New Zealand & South Asia). He has served as an EDS distinguished lecturer since 2000. Since 2007 Dr. Zhou is an editor of the IEEE Electron Device Letters.
Monday, March 3, 2008
The candidate should be a person who holds a PhD as awarded within the three years prior to the date when the period for presentation of application forms closes. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution in the Ministry of Education and Science web site.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the European projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by these European projects. In the case of NANOSIL Network of Excellence, the targeted devices are mostly: Schottky Barrier SOI MOSFETs, strained Si SOI MOSFETs, and Si Nanowires. In the case of the Compact Modeling Network the devices addressed are : multi-gate MOSFETs (FinFETs, DG MOSFETs,...), High Voltage MOSFETs and advanced HEMTs.
The postdoc position, which will be a contract, will have a duration of up to 3 years. The net salary will be around 1900 Euro/months. Researchers from many European countries will have tax exemption during the first two years, so they will be able to have much higher net salaries.
Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: March 11 2008
MY E-MAIL ADDRESS IS: firstname.lastname@example.org
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.
Tarraco (the Roman name for
Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage,
Those interested, please contact Eugenio Garcia: eugeni.garcia(_at_)uib.es (substitute _at_ by @)
"Creating device-simulation models for advanced process technologies is problematic because physical wafers that meet specifications with acceptable yield often are not produced for months to years," said Roberto Tinti, product marketing manager with Agilent's EEsof EDA division. "Our Target Modeling Package addresses this by providing an easy way to extract CMOS device models from a reduced set of Process Control Monitor data before wafers from a new process are produced. Our customers tell us that extracting simulation models before a process matures can save them several months in a typical design cycle."
You can have a look to the full press release here.