Jul 30, 2008

Papers on IEEE Trans on Electron Devices (Aug 2008)

Well, it seems that this has been a very productive issue:

Accurate Statistical Description of Random Dopant-Induced Threshold Voltage Variability
Millar, C. Reid, D. Roy, G. Roy, S. Asenov, A. (link)

Analytical Threshold Voltage Model for Double-Gate MOSFETs With Localized Charges
Kang, H. Han, J.-W. Choi, Y.-K. (link)

Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs
Asenov, A. Cathignol, A. Cheng, B. McKenna, K. P. Brown, A. R. Shluger, A. L. Chanemougame, D. Rochereau, K. Ghibaudo, G. (link)

A Charge-Based Model for Long-Channel Cylindrical Surrounding-Gate MOSFETs From Intrinsic Channel to Heavily Doped Body
Liu, F. He, J. Zhang, L. Zhang, J. Hu, J. Ma, C. Chan, M. (link)

Drain Current Model Including Velocity Saturation for Symmetric Double-Gate MOSFETs
Hariharan, V. Vasi, J. Rao, V. R. (link)

A Unified Analytic Drain–Current Model for Multiple-Gate MOSFETs
Yu, B. Song, J. Yuan, Y. Lu, W.-Y. Taur, Y. (link)

A Quasi Two-Dimensional Conduction Model for Polycrystalline Silicon Thin-Film Transistor Based on Discrete Grains
Wong, M. Chow, T. Wong, C. C. Zhang, D. (link)

Simulation of the Impact of Process Variation on the Optimized 10-nm FinFET
Khan, H. R. Mamaluy, D. Vasileska, D. (link)

Investigation of the Transport Properties of Silicon Nanowires Using Deterministic and Monte Carlo Approaches to the Solution of the Boltzmann Transport Equation
Lenzi, M. Palestri, P. Gnani, E. Reggiani, S. Gnudi, A. Esseni, D. Selmi, L. Baccarani, G. (link)

A Physical Model of High Temperature 4H-SiC MOSFETs
Potbhare, S. Goldsman, N. Lelis, A. McGarrity, J. M. McLean, F. B. Habersat, D. (link)

3C-Silicon Carbide Nanowire FET: An Experimental and Theoretical Approach
Rogdakis, K. Lee, S.-Y. Bescond, M. Lee, S.-K. Bano, E. Zekentes, K. (link)

Characterization, Modeling, and Application of 10-kV SiC MOSFET
Wang, J. Zhao, T. Li, J. Huang, A. Q. Callanan, R. Husna, F. Agarwal, A. (link)

Jul 18, 2008

Nice papers (July, 2008)

No, we're not dead, but overworked... Here you have some nice papers, from various sources, including one which is unexpected...

A simple analytical model for the front and back gate threshold voltages of a fully-depleted asymmetric SOI MOSFET
Chung Ha Suh, Solid-State Electronics (abstract)

Analysis and Modeling of Threshold Voltage Mismatch for CMOS at 65 nm and Beyond
Jeffrey B. Johnson, Terence B. Hook, and Yoo-Mi Lee, IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 7, JULY 20 (abstract)

An Analytical Model Based on Surface Potential for a-Si:H Thin-Film Transistors
Yuan Liu, Student Member, IEEE, Ruo-he Yao, Bin Li, Member, IEEE, and Wan-Ling Deng, JOURNAL OF DISPLAY TECHNOLOGY, VOL. 4, NO. 2, JUNE 2008 (abstract)