Thursday, April 30, 2020

#paper: W. E. Muhea, G. U. Castillo, H. C. Ordoñez, T. Gneiting, G. Ghibaudo and B. Iñiguez, "Parameter Extraction and Compact Modeling of 1/f Noise for Amorphous ESL IGZO TFTs," in IEEE J-EDS, vol. 8, pp. 407-412, 2020.

from Twitter

April 30, 2020 at 03:13PM

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020.

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS, vol. 8, pp. 396-406, 2020

— Wladek Grabinski (@wladek60) April 30, 2020 from Twitter

#Spanish and #French governments turn to Jitsi Meet #opensource video-conferencing platform

from Twitter

April 30, 2020 at 10:05AM

Wednesday, April 29, 2020

#paper: K. Xia, "New C∞ Functions for Drain–Source Voltage Clamping in Transistor Modeling," in IEEE TED, vol. 67, no. 4, pp. 1764-1768, April 2020.

from Twitter

April 29, 2020 at 04:16PM

#paper: E. A. Gutiérrez-D., J. Méndez-V., J. C. Tinoco, E. T. Rios and O. V. Huerta-G., "DC and 28 GHz Reliability of a SOI FET Technology," in IEEE J-EDS, vol. 8, pp. 385-390, 2020.

XXII ESCOLA SUL DE MICROELETRÔNICA: EMicro 2020 XXXV SIMPÓSIO SUL DE MICROELETRÔNICA: SIM 2020 27-30 April 2020 Virtual Event: Recordings: #paper

from Twitter

April 29, 2020 at 09:21AM

Tuesday, April 28, 2020

#paper: H. Cortes-Ordonez et al., "Parameter extraction and compact drain current model for IGZO transistor from 210K up to 370K," 2020 IEEE Latin America Electron Devices Conference (LAEDC), San Jose, Costa Rica, 2020, pp. 1-5.

from Twitter

April 28, 2020 at 05:01PM

Monday, April 27, 2020

#paper: X. Lu, M. Law, Y. Jiang, X. Zhao, P. Mak and R. P. Martins, "A 4um Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65nm CMOS," in IEEE TED, vol. 67, no. 5, pp. 2223-2225, May 2020.

from Twitter

April 27, 2020 at 11:37AM

Sunday, April 26, 2020

#paper: Y. Hernández-Barrios, A. Cerdeira, M. Estrada and B. Iñíguez, "Analytical Current–Voltage Model for Double-Gate a-IGZO TFTs With Symmetric Structure for Above Threshold," in IEEE TED, vol. 67, no. 5, pp. 1980-1986, May 2020.

from Twitter

April 26, 2020 at 03:49PM

Friday, April 24, 2020

#paper: L. Liu, W. Chen, X. Liu and G. Du, "Photoelectric Characteristic Evaluation of Different Structured UTBB MOSFETs," in IEEE TED, vol. 67, no. 5, pp. 1919-1923, May 2020

from Twitter

April 24, 2020 at 05:49PM

Online Classes on The Principle of Semiconductor Devices

Professor Mansun Chan, UST (HK), has developed a 13 weeks online class on the principle of semiconductor devices.  Unlike tradition lectures, the class use extensive animations to help students to visualize the actions of carriers in a device.  The classes was divided into two part, part I on semiconductor carrier statistics, PN Junction, BJT and part II on MOSFET and advanced FET.

Meet your instructor:

Mansun Chan
Chair Professor, Department of Electronic and Computer Engineering
The Hong Kong University of Science and Technology

conference FOSS paper reached 200 reads

D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73.

Abstract - A GNU Octave - based application for device-level compact model evaluation and parameter extraction has been developed. The applications main features are as follows: experimental I–V data importing, generating input data for different circuit simulation programs, running the simulation program to calculate I–V characteristics of the specified models, calculating model misfit and its sensitivity to selected parameter variation, and the comparison of experimental and simulated characteristics. Measured I–V data stored by different measurement systems are accepted. Circuit simulations may be done with Ngspice, Qucs and LTSpiceIV © . Selected aspects of the application are presented and discussed.

Monday, April 20, 2020

Pokit PRO. Multimeter, Oscilloscope & Logger #paper

from Twitter

April 20, 2020 at 02:23PM

#paper: J. Li, Z. Chen, Y. Qu and R. Zhang, "Traps Around Ge Schottky Junction Interface: Quantitative Characterization and Impact on the Electrical Properties of Ge MOS Devices," in IEEE J-EDS, vol. 8, pp. 350-357, 2020

from Twitter

April 20, 2020 at 10:49AM

#paper: D. Arbet, L. Nagy, V. Stopjakova "Ultra-Low-Voltage IC Design Methods" Integrated Circuits/Microchips, 2020 | IntechOpen

from Twitter

April 20, 2020 at 09:21AM

Wednesday, April 15, 2020

#paper: W. Cheng et al., "Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current," in IEEE J-EDS Society, vol. 8, pp. 336-340, 2020

from Twitter

April 15, 2020 at 05:30PM

Fwd: "It is forbidden to spit on cats during plague-time"

-------- Forwarded message FYI ---------
From: John Cooley <>
Date: Wed, Apr 15, 2020 at 5:10 PM
Subject: users on Empyrean XTop ECOs, and Cadence Tempus vs. PrimeTime

  "It is forbidden to spit on cats during plague-time."

       - Albert Camus, French philosopher (1913 - 1960)

 Empyrean XTop fills PrimeTime ECO hole is Best of EDA 2019 #8a

 Cadence Tempus fast ECOs, sign-off, and MMMC is Best of EDA #8b
 STMicroelectronics: RDC signoff on CPU subsystem & Real Intent RDC
Mentor whitepaper Calibre faster through DRC deck optimization

#paper: Lin, P., Li, C., Wang, Z. et al. Three-dimensional memristor circuits as complex neural networks. Nat Electron (2020)

from Twitter

April 15, 2020 at 02:51PM

#paper: Darsen D. Lu, Sourav De, Mohammed Aftab Baig, Bo-Han Qiu and Yao-Jen Lee; A computationally efficient compact model for ferroelectric FETs for the simulation of online training of neural networks; arXiv preprint arXiv:2004.03903, 2020

from Twitter

April 15, 2020 at 10:27AM

Tuesday, April 14, 2020

#paper: Meng Zhang and Dragan Damjanovic; Quasi-rayleigh model for modeling hysteresis of piezoelectric actuators; Smart Materials and Structures; DOI:

from Twitter

April 14, 2020 at 02:24PM

ICMTS2020 #paper: Cutoff Frequency Fluctuation in RF-MOSFETs

2020 ICMTS, April 6-9, Edinburgh (UK)
Novel Statistical Modeling and Parameter Extraction Methodology
of Cutoff Frequency for RF-MOSFETs
Chika Tanaka, Yasuhiko Iguchi, Atsushi Sueoka, and Sadayuki Yoshitomi
Memory Division, Kioxia Corporation
2-5-1, Kasama, Sakae-ku, Yokohama, 247-8585, Japan

Abstract: The cutoff frequency fluctuation in RF-MOSFET has been investigated. Detailed analysis for capacitance fluctuation as well as the extraction of an intrinsic MOSFET parameter were performed. The extracted process parameters were verified by the framework of effective mobility. The global statistical model of cutoff frequency was successfully developed in terms of capacitance fluctuation, considering intrinsic (channel and bulk charge) and extrinsic (overlap and fringe) capacitance components separately and identifying the major variability sources for cutoff frequency by using extracted parameter.
Fig: Calculated σfT is plotted against σfT obtained from measured data.

Saturday, April 11, 2020

Fwd: MIXDES 2020 moves online

------- Forwarded message ---------
From: MIXDES 2020 Organising Committee <>
Date: Thu, 9 Apr 2020 at 22:03
Subject: MIXDES 2020 moves online
To: <>

Dear Colleagues,

As the Covid-19 disease is spreading worldwide and we have not yet seen
the peak, we have decided to move current edition of MIXDES to the
Internet. Hopefully next year we will be able to meet face to face. In
the meantime please keep your calendars blocked for the original
conference dates (June 25-27), and prepare to join us online. We will
inform you about the details later.

We are planning to reduce the conference fee to the level of ca. 100 Euro.

As in the previous years, the Conference Proceedings containing all the
presented papers will still be published on IEEE Xplore, so you do not
have to worry about visibility of your papers.

Wishing you Happy Easter and hoping that you stay safe,

Mariusz Orlikowski

Sent from Wladek's iPhone

Fwd: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble

------- Forwarded message ---------
From: Andreia CATHELIN <>
Date: Thu, 9 Apr 2020 at 17:11
Subject: Immediate changes for ESSCIRC-ESSDERC 2020 in Grenoble
To: Andreia CATHELIN <>
CC: Andreia CATHELIN <>, Sylvain CLERC <>, Maud VINET <>, ANDRIEU François 200489 <>, Dominique THOMAS <>, ERNST Thomas 175262 <>, <>, <>

Grenoble, April 9th, 2020


Dear TPC members of ESSCIRC-ESSDERC conference,


First of all, we truly hope this email finds you in good health, together with family and friends!


Together with our sponsoring IEEE Societies, SSCS and EDS, ESSCIRC-ESSDERC is closely monitoring developments related to the rapidly evolving COVID-19 pandemic. The health and safety of our members is the number one priority of our societies. As of today April the 9th, 2020, more than one third of the Global population is under severe confinement, as a result of the protective public health measures imposed by the different governments, states or provinces. The situation is still evolving rapidly and dramatically, unfortunately in an unpredictable way.


Given this uncertain situation, we, the organizing committee of ESSxxRC2020 Grenoble and the ESSCIRC-ESSDERC Steering committee, have decided to propose a new format for our conference:


From a practical point of view:

For all the authors who have been or were about to prepare papers for this version of ESSCIRC-ESSDERC, we strongly encourage you to submit your publications directly to the following IEEE journals:

  • For ESSCIRC, please see
    • IEEE SSC-L, Solid-State Circuits Letters (same 4-pages format as ESSCIRC)
      • The SSCS has just created a Special Section on ESSCIRC 2020, inside the SSC-Letters:
      • When submitting their manuscript, authors need to select: Special Section on ESSCIRC 2020. It is open for submissions from April 9, 2020 to May 4, 2020.
      • The authors having accepted papers through this path will be kindly invited in September 2021 to present this same work in a Special Oral Session of ESSCIRC2021.
    • IEEE JSSC, Journal of Solid-State Circuits
    • IEEE O-JSSC, Open-Journal of Solid-State Circuits (open access)

  • For ESSDERC, please see :
    • IEEE EDL, Electron Devices Letters (same 4-pages format as ESSDERC) 
    • IEEE TED, Transactions on Electron Devices
    • IEEE JEDS, Journal of Electron Devices Society (open access)
    • We are actively working with EDS to propose a similar Special Section for ESSDERC together with ED-L.


In 2021, we are planning to resume to a usual conference development schedule with tentative dates of: 

  • paper submission deadline on April 19th, 2021,
  • the conference in Grenoble, September 6-9, 2021.

All the topology of the conference with regards to the different tracks and TPC members stays exactly the same for 2021. You might as well be solicited by the different IEEE journals for anonymous reviews, please do provide all your support, as they will get a much larger volume of publications than regular.


The 2022 version of ESSCIRC-ESSDERC will take place in September 2022 in Milano. We thank very much to Andrea Baschirotto&team for their immediate proactivity, flexibility and cooperation.


This information shall be posted as well on our website within the hour, and we will massively announce it also on social media. Please do not hesitate to spread this information to your personal network.


Thank you very much for your continued trust, and stay safe!


Kind regards,


Andreia Cathelin, TPC chair ESSCIRC

Francois Andrieu, TPC chair ESSDERC

Sylvain Clerc, TPC co-chair ESSCIRC

Maud Vinet, TPC co-chair ESSDERC

Thomas Ernst, Conference Chair

Dominique Thomas, Conference Co-Chair

Qiuting Huang, ESSCIRC-ESSDERC Steering Committee Chair



Andreia Cathelin | Tel: +33 476926603 | Mobile: +33 607649918

Technology & Design Platform | Strategy & Innovation/Ecosystem | Technology R&D Fellow


STMicroelectronics Crolles2

850 rue Jean Monnet | 38926 Crolles Cedex | France


Knowledge is proud that he has learned so much,
Wisdom is humble that he knows no more.

The Task, Book 6, 'The Winter Walk at Noon' (published 1785). William Cowper




Sent from Wladek's iPhone

Thursday, April 9, 2020

#Resignation of Mauro Ferrari – Statement by the #ERC's Scientific Council #paper

from Twitter

April 09, 2020 at 09:53AM

Tuesday, April 7, 2020

Monday, April 6, 2020

#paper: T. Joshi, Y. Singh and B. Singh, "Extended-Source Double-Gate Tunnel FET With Improved DC and Analog/RF Performance," in IEEE TED, vol. 67, no. 4, pp. 1873-1879, April 2020

from Twitter

April 06, 2020 at 11:05AM

#paper M. Ba, A. K. Diallo, E. H. B. Ly, J. Launay and P. Temple-Boyer, "Numerical Modeling of Glucose Biosensor With pH-Based Electrochemical Field-Effect Transistor Device," in IEEE TED, vol. 67, no. 4, pp. 1787-1792, April 2020.

from Twitter

April 06, 2020 at 10:21AM

Thursday, April 2, 2020

#SI2 adopts #L-UTSOI compact #model for #FDSOI

from Twitter

April 02, 2020 at 04:04PM

Non-invasive #brain #pressure #measurement treats brain as a tuned circuit #paper

from Twitter

April 02, 2020 at 02:24PM

#paper Y. Liao et al., "A Compact Model of Analog RRAM With Device and Array Nonideal Effects for Neuromorphic Systems," in IEEE TED, vol. 67, no. 4, pp. 1593-1599, April 2020

from Twitter

April 02, 2020 at 11:41AM

EDS Newsletter [April 2020 Vol. 27, No. 2 Issn: 1074 1879]

EDS Newsletter [April 2020 Vol. 27, No. 2 Issn: 1074 1879]
Delivered by Newsletter Editorial Staff led 
by Dr. Daniel Tomaszewski, ITE, Editor-In-Chief
— Wladek Grabinski (@wladek60) April 2, 2020
from Twitter

April 02, 2020 at 09:37AM via IFTTT

Wednesday, April 1, 2020

Time to #OpenSource #Ventilators from Digital and Cyberspace Policy Program and Net Politics

from Twitter

April 01, 2020 at 08:28PM

[C4P] ESSDERC TRACK3 Compact Modeling

European ESSDERC/ESSCIRC conference will be organized in Grenoble (F) on Sept.14-18, 2020 with its integral TRACK3: Compact Modeling and Process/Device Simulation which is open for submissions, now. You and all your R&D partners are welcome to submit a modeling paper. The paper submission deadline is April 17, 2020

TRACK3: Compact modeling and process/device simulation (including TCAD and advanced simulation techniques and studies)  focuses on following domains among other R&D topics:
  • Compact/SPICE modeling of electronic, optical, organic, and hybrid devices and their IC implementation and interconnection. 
  • Verilog-A models of the semiconductor devices (including Bio/Med sensors, MEMS, Microwave, RF, HV and Power, emerging technologies and novel devices)
  • Compact/SPICE parameter extraction
  • Performance evaluation and open source (FOSS) benchmarking/implementation methodologies
  • Modeling of interactions between process, device and circuit design, 
  • Foundry/Fabless interface strategies
  • Numerical TCAD, analytical, statistical modeling and simulation of electronic, optical and hybrid devices, interconnect, isolation and 2D/3D integration
  • Aspects of materials, fabrication processes and devices e.g. advanced physical phenomena (quantum mechanical and non-stationary transport phenomena, ballistic transport, ...)
  • Optical, mechanical or electro-thermal modeling and simulation
  • DfM, ageing, reliability of materials and devices
Please share our TRACK3 C4P with all your academic and industrial R&D partners active in the compact/SPICE modeling, Verilog-A standardization and TCAD/EDA simulations. Of course, your and your research team proactive contribution to our TRACK3 is more than welcome. I do hope that despite of a last minute notice, with your help, we will be able to draw even more attention to the ESSDERC/ESSCIRC Conference and, in particular, our modeling TRACK3