Monday, February 25, 2013

[mos-ak] Live webcast - MQA: The Golden Standard for Device Model Validation


MQA: The Golden Standard for Device Model Validation 


Register now




Agilent Technologies invites you to our live webcast so that you can stay up to date with the latest technologies and solutions.

When: 19th March 10:30 (CET)

Where: Online




Why is this webcast important?

Whether you are a Foundry or IDM creating models, or a design house using device models, it is important to understand model behaviour and asses quality. Foundries/IDMs need to comprehensively and effectivley asses the quality of device models, and take steps to assure their behaviour for the technology of interest. Design houses need to validate device models, and understand their behaviour in the regions of interest, prior to indroducing to the design teams. It is important for Design Houses to understand where errors exist in Foundry supplied libraries, model and document their behaviour, and assure operation in the simulation environment. MQA provides this functionality for Foundries, IDMs and fab-less Design Houses, and provides a sophisticated automated Report Generation feature to document results.




Who should view this webcast?

Modeling teams that create device models at Foundries/IDMs, foundry interface groups at Design Houses, IC designer & manger who need to evaluate new Foundry technology. 

Register Now






Presenter: Janice Deng





Janice Deng graduated from Peking University in Microelectronic, and went on to get an Engineering diploma at ESIEE, France. In 2008, she joined Accelicon , as an application engineer supporting MBP and MQA worldwide.










Presenter: Cedric Pujol





Cedric Pujol received his Electronic Diploma at Engineering School INP Grenoble France in 1997. He has worked 7 years at ST Microelectronics, in Central R&D. He developed his skills on Device Modeling through various positions : Design Kit development for Analog and RF, Design tool strategy choice for ST. Cedric joined Xpedion then Agilent where he is now leading the RFIC pre-sales activity in Europe as well as Device Modeling solution.







You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to
To post to this group, send email to
Visit this group at
For more options, visit

Friday, February 22, 2013

Fully depleted silicon technology to underlie energy-efficient designs at 28 nm and beyond

From EDN:

Industry Need for Continued Scaling
Technological advances in transistor scaling have had a dramatic effect on consumer electronics and their corresponding use cases. In 1973, Motorola developed the first mobile phone, which weighed 2.5 pounds, was 9 inches long, had limited battery life and only allowed users to make and receive calls. Fast forward to today's mobile devices that fit in the palm of your hand, with batteries that last all day and more computing power than ever thought possible.
While it has taken 40 years to come this far, innovation has been exceptionally rapid over the course of the past 10 years, and consumer expectations have accelerated at a similar pace. What sort of features and computing capabilities will we expect of our mobile devices five years from now? How about in 10 years? Future improvements largely hinge on the industry's ability to continue on the path of Moore's Law by producing ever-smaller transistors with ever-greater performance. Satisfactory scaling fulfills two core requirements: the need for smaller transistors that reduce costs and a parallel need for improved performance and lower power consumption.
To date, transistor scaling has continued in accordance with Moore's Law down to 32 nm. Engineering challenges, however, are forcing chipmakers to compromise performance and power efficiency in order to reach smaller nodes - unless they switch to new technologies that help better solve these challenges. Today, the semiconductor industry is starting to deploy such new technologies, largely relying on "fully-depleted" transistors for continued scaling and performance gains.
Fully Depleted Silicon Technology
A fully depleted (FD) transistor can be planar or tri-dimensional. In each case, in direct contrast with other technologies commonly used today, the current between source and drain is allowed to flow only through a thin silicon region, defined by the physical parameters of the transistor.
In the planar design of fully depleted technology, transistors are built flat on the silicon. For the three-dimensional alternative, manufacturers fabricate thin vertical "fins" of silicon in which current will flow from source to drain. Additionally, FD transistors can eliminate the need for implanting "dopant" atoms into the channel. These improvements help chipmakers secure gains in both energy efficiency and performance that are required from scaling silicon technology.
Figure 1: Top Left (1a): Cross-section of a conventional MOS transistor on bulk silicon, Top right (1b): Cross-section of a planar fully-depleted transistor (FD-SOI), Bottom (1c): Perspective view of a FinFET (one fin shown here), silicon-on-insulator and bulk silicon flavors. (*) Note: PTS in the bottom right diagram is Punch Through Stopper, which is a heavily doped barrier layer at the bottom of the fin. S is Source, G is Gate, D is Drain of CMOS transistors. Notional views only; dimensions are not to scale.

READ MORE in the original post.

Monday, February 11, 2013

IBM, GF, and Samsung offer a glimpse of chipmaking's future

Below is a slide showing GF' process tech roadmap for the next little while:

Friday, February 8, 2013

13. ITG/GMM-Fachtagung Analog 2013

13. ITG/GMM-Fachtagung Analog 2013
4. - 6. März in Aachen
Entwicklung von Analogschaltungen mit CAE-Methoden

Die Registrierung ist eröffnet!