What TI’s Little Professor Can Teach Us https://t.co/WP22l0RpFe #semi https://t.co/kyZyKyfNF3
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Mar 31, 2022
What TI’s Little Professor Can Teach Us https://t.co/WP22l0RpFe #semi https://t.co/kyZyKyfNF3
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[https://t.co/W7wbdkjwM3] Study shows how superconductivity can be switched on and off in superconductors https://t.co/7HZsCxZk4V #quantumtechnology, #quantumcomputing #superconductivity #superconductors #nanowires #semi https://t.co/DAOlfz7ghi
[https://t.co/W7wbdkjwM3] Study shows how superconductivity can be switched on and off in superconductors https://t.co/7HZsCxZk4V #quantumtechnology, #quantumcomputing #superconductivity #superconductors #nanowires #semi https://t.co/DAOlfz7ghi
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[paper] Junctionless pH Sensing BioFET
Nawaz Shafi, Aasif Mohamad Bhat, Jaydeep, Singh Parmar, Chitrakant Sahu, C. Periasamy
Effect of geometry and temperature variations on sensitivity and linearity
of junctionless pH sensing FET: An experimental study
Superlattices and Microstructures, p. 107186, Mar. 2022,
doi: 10.1016/j.spmi.2022.107186
* Malaviya National Institute of Technology Jaipur, India
Abstract: Here-in this work, boron doped poly-silicon based dimensional variants of thin film planar junctionless field effect transistors are fabricated through CMOS compatible process for pH detection. The dimensional variants are classified into two sets as set-1 (channel length, L = 100 μm) and set-2 (channel length, L = 120 μm) with widths of 3 μm, 5 μm, 10 μm, and 20 μm. Sensitivity of the fabricated devices is analyzed using phosphate buffer saline solutions of pH 3.1, 5.2, 7, 9 and 11.2 and is computed in terms of relative shift in threshold voltage (VTh) and maximum drain current (IDS). The reference VTh and IDS are taken at neutral pH 7. Here we have experimentally analyzed the effect on pH sensitivity by varying the device widths and temperatures from 30 °C to 50 °C. It is observed that varying the device width from 3 μm to 20 μm, VTh sensitivity reduces from 19.08% to 9.17% and from 16.03% to 8.5% for set-1 and set-2 devices respectively. Increasing temperature from 30 °C to 50 °C causes reduction of VTh sensitivity from 18.68% to 13.52% for device with W/L = 3μm/100 μm and 16.78%–10.99% for device with W/L = 3μm/120 μm. The reduction in width causes average VTh sensitivity to roll-off by 0.49%/μm and 0.26%/μm for L = 100 μm and L = 120 μm respectively. Also the increase in operating temperature from 30 °C to 50 °C leads VTh sensitivity to roll-off by 0.17%/°C and 0.2%/°C for W/L = 3μm/100 μm and W/L = 3μm/120 μm respectively.
Fig: Junctionless pH sensing BioFET
Acknowledgment: This work was supported by Center of Nano Science and Engineering, Indian Institute of Science, Bangalore under Indian Nanoelectronic Users Program. Authors express gratitude to Materials Research Center MNIT-Jaipur for characterization support.
[paper] Power VDMOSFET as X-ray Dosimeter
Goran S. Ristić1, Stefan D. Ilić1,2, Sandra Veljković1, Aleksandar S. Jevtić1, Strahinja Dimitrijević1, Alberto J. Palma3, Srboljub Stanković4 and Marko S. Andjelković5
Commercial P-Channel Power VDMOSFET as X-ray Dosimeter
Electronics, vol. 11, no. 6, p. 918, Mar. 2022
doi: 10.3390/electronics11060918
1 University of Niš, Serbia
2 University of Belgrade, Serbia
3 University of Granada, Spain
4 “Vinča” Institute of Nuclear Sciences, Belgrade, Serbia
5 IHP, Frankfurt an der Oder, Germany
Abstract: The possibility of using commercial p-channel power vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOSFETs) as X-ray sensors is investigated in this case study. In this aspect, the dependence of sensitivity on both the gate voltage and the mean energy for three X-ray beams is examined. The eight gate voltages from 0 to 21 V are applied, and the dependence of the sensitivity on the gate voltage is well fitted using the proposed equation. Regarding X-ray energy, the sensitivity first increases and then decreases as a consequence of the behavior of the mass energy-absorption coefficients and is the largest for RQR8 beam. As the mass energy-absorption coefficients of SiO2 are not found in the literature, the mass energy-absorption coefficients of silicon are used. The behavior of irradiated transistors during annealing at room temperature without gate polarization is also considered.
Fig: Block diagram of experimental setup.
Acknowledgement: This research was funded by the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 857558, and the Ministry of Education, Science, and Technological Development of the Republic of Serbia under the project No. 43011.
Japan Looks to Revive Semiconductor Industry
[@RobertQ84643496] Japan Looks to Revive Semiconductor Industry Source: https://t.co/F1mfLCCS1e #semi #semiconductorindustry #manufacturing #technology #computerchips #taiwan #europe #engineering https://t.co/WtAHUzChwj
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Analysing Wide-Bandgap Semiconductors for Power Electronics
[https://t.co/N3ZtoszlKm] Analysing Wide-Bandgap Semiconductors for Power Electronics - Power Electronics News #widebandgap #GaN #SiC #semi https://t.co/tzk8cFQjac
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[book] Marco Tartagni; Electronic Sensor Design Principles
[book] Marco Tartagni; Electronic Sensor Design Principles; Cambridge University Press, 6 Jan 2022; ISBN 1107040663, 9781107040663 #sensors #electronics #electronicdesign #design #semi https://t.co/sM6RQgeYao
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Mar 30, 2022
[mos-ak] [rescheduled] Spring MOS-AK Workshop on April 29, 2022 (online)
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop
rescheduled for April 29, 2022 (online)
Rescheduled Event
Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
W.Grabinski for Extended MOS-AK Committee- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based memory
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
- Technology R&D, DFY, DFT and reliability/aging IC designs
- Foundry/Fabless Interface Strategies, eg: Free 130nm Skywater PDK.
Online Abstract Submission to be open (any related enquiries can be sent to absttracts@mos-ak.org)
Online Event Registration to be open (any related enquiries can be sent to registration@mos-ak.org)
Important Dates:
- Call for Papers: Feb. 2022
- 3nd Announcement: April 5, 2022
- Final Workshop Program: April 19, 2022
- Spring MOS-AK Workshop: April 29, 2022
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[Mannerisms] #Top10 #Chip Companies https://t.co/2RtxrD7Tdu #semi https://t.co/J39Zj89uIM
[Mannerisms] #Top10 #Chip Companies https://t.co/2RtxrD7Tdu #semi https://t.co/J39Zj89uIM
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Qubits made by advanced semiconductor manufacturing; Nature Electronics, Published online: 29 March 2022; doi:10.1038/s41928-022-00727-9 https://t.co/2lcUWlBEea #semi https://t.co/a17oW3AaVt
Qubits made by advanced semiconductor manufacturing; Nature Electronics, Published online: 29 March 2022; doi:10.1038/s41928-022-00727-9 https://t.co/2lcUWlBEea #semi https://t.co/a17oW3AaVt
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Mar 29, 2022
E. Catapano et al., “Modeling and simulations of FDSOI five-gate qubit MOS devices down to deep cryogenic temperatures,” Solid-State Electronics, p. 108291, Mar. 2022, doi: 10.1016/j.sse.2022.108291. https://t.co/WffsujnId2! #semi https://t.co/lGM4cVr3hr
E. Catapano et al., “Modeling and simulations of FDSOI five-gate qubit MOS devices down to deep cryogenic temperatures,” Solid-State Electronics, p. 108291, Mar. 2022, doi: 10.1016/j.sse.2022.108291. https://t.co/WffsujnId2! #semi https://t.co/lGM4cVr3hr
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[https://t.co/we1zOo94rc] Support for researchers from Ukraine topped up to 9M CHF #ScienceForUkraine #ScholarsAtRisk #standwithukraine #ukraina #semi https://t.co/QzdGnmEaZI
[https://t.co/we1zOo94rc] Support for researchers from Ukraine topped up to 9M CHF #ScienceForUkraine #ScholarsAtRisk #standwithukraine #ukraina #semi https://t.co/QzdGnmEaZI
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[Mehdi Saligane] Call for Proposals: 2022 #SSCS #PICO #Open-Source #Chipathon
[Mehdi Saligane] Call for Proposals: 2022 #SSCS #PICO #Open-Source #Chipathon! #semi https://t.co/UP6vluVZtc
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H.-C. Han et al., Performance 22nm FDSOI Down to Cryogenic Temperatures
H.-C. Han et al., “Back-gate Effects on DC Performance and Carrier Transport in 22nm FDSOI Technology Down to Cryogenic Temperatures,” Solid-State Electronics, p. 108296, Mar. 2022, doi: 10.1016/j.sse.2022.108296. https://t.co/cfF03FZrfx! #semi https://t.co/8KTHal8GLY
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[paper] Andre Zeumault, Shamiul Alam, Md Omar Faruk, and Ahmedullah Aziz , "Memristor compact model with oxygen vacancy concentrations as state variables", Journal of Applied Physics 131, 124502 (2022) https://t.co/dUQEoitB03 #semi https://t.co/Epv6mW660y
[paper] Andre Zeumault, Shamiul Alam, Md Omar Faruk, and Ahmedullah Aziz , "Memristor compact model with oxygen vacancy concentrations as state variables", Journal of Applied Physics 131, 124502 (2022) https://t.co/dUQEoitB03 #semi https://t.co/Epv6mW660y
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[paper] Leon C. Camenzind et al, A hole spin qubit in a fin field-effect transistor above 4K
[paper] Leon C. Camenzind et al, A hole spin qubit in a fin field-effect transistor above 4 kelvin, Nature Electronics (2022). DOI: 10.1038/s41928-022-00722-0 https://t.co/g03WZcxi8k #semi https://t.co/UkLHDNA8AK
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Mar 28, 2022
Smart textiles for personalized healthcare
Smart textiles for personalized healthcare; Nature Electronics, Published online: 28 March 2022; doi:10.1038/s41928-022-00723-z https://t.co/2QKRnN4lgy #semi https://t.co/qUlBHJBB9l
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[C4P] 17th ITC at the University of Surrey
FIRST CALL FOR PAPER
The 17th International Thin-Film Transistor Conference (ITC2022) is dedicated to TFT related technologies for displays, sensors and general large area and flexible electronics. As TFT applications broaden and expand beyond traditional markets, the 17th ITC will provide a platform for sharing the research progress and discussing the challenges in this field. It will be between 14-16 September, hybrid format, online and on site at the University of Surrey (UK).
Areas of Interest include, but are not limited to:
- Semiconductor materials and processing for high performance TFTs
- Understanding and addressing instabilities of TFTs
- TFT based functional devices (e.g., sensors, memories, synapse)
- Scaling of TFTs for high resolution integration
- TFT compact models for circuit simulation
- TFT backplane integration for displays and sensors
- Flexible and stretchable TFT devices and circuits
- Circuit design and implementations of TFTs
Student Fee Waiver: Top student submissions will be awarded a full registration fee waiver (in person or online), supported by EPSRC Project ALPACA teamsporea.info/alpaca/. Visit the conference website for instructions on how to be considered
Important Dates:
- 17 May 2022 Two-page Abstract Submission Deadline
- 28 June 2022 Notification of Acceptance
- 19 July 2022 Registration Opens
- 14-16 September 2022 Conference dates
For further information, please visit: itc2022.net
[C4P] Organic and Inorganic Light Emitting Diodes
Call for Book Chapters
Organic and Inorganic Light Emitting Diodes:
Reliability Issues and Performance Enhancement
Scope of the Book: There has been a long-standing interest within the development of solid-state light-emitting devices (LED) as they need proved to be more efficient than the traditional tungsten filament light bulbs. For more than three decades, they have been utilized in various areas of applications like communication systems and lightning applications due to their longer life, higher efficiency, environmental sustainability and lower cost. These applications have placed stringent demands on improvements within the performance of LEDs. Specific expertise like understanding the materials, structure and composition thoroughly is required to get precise and reproducible results. This book covers a comprehensive range of topics on the physical mechanisms of LED, scattering effects, challenges in fabrication and efficient enhancement techniques in organic and inorganic LEDs. Nowadays, due to the due to the rapid growth of design and manufacturing technology, there are as many as consumer products with high reliability and high performance. This book deals with various reliability issues in organic/inorganic LEDs like trapping and scattering effects, packaging failures, efficiency droops, irradiation effects, thermal degradation mechanisms etc. This book also provides insights into the improvement of performance and reliability of LEDs.
Table of Content:
- Physical mechanisms that limit the LED's reliability
- Failure modes and mechanisms of LED packaging
- Trapping effects in LEDs
- Scattering effects on the optical performance of LEDs
- Efficiency droop in LEDs
- Neutron irradiation effects in LEDs
- Thermal degradation in LEDs
- Slow failure and catastrophic failure mechanisms in LEDs
- Challenges in fabrication and packaging of LEDs
- Thermal cooling packages in LEDs
- Light extraction efficiency improvement techniques in LEDs
- Efficiency droop minimization techniques
- Efficiency enhancement techniques in flexible LEDs
- Efficiency enhancement techniques in flexible LEDs
Important Dates
- Chapter proposal submission deadline
(Abstract + Chapter flow 1500 – 2000 words): 30th April 2022 - Notification of Acceptance: 10th May 2022
- Full Chapter submission: 10th June 2022
- Acceptance/Rejection Notification: 30th June 2022
- Revised Chapter Submission (if required): 10th July 2022
Prospective authors are requested to submit their chapter proposals/full chapters. All submitted chapters will be peer reviewed. There are no publication fees for a chapter submitted to this book publication. Submitted chapters should not have been published previously, not under considerations for publication elsewhere. Abstract and Chapters are written should be plagiarism-free. Please include Title, keywords, Name of author, co-authors, institutional affiliation and email address in abstract/proposals. Authors are requested to refer to the following link for detailed guidelines for chapter preparation:
https://www.routledge.com/our-customers/authors/publishing-guidelines
https://www.routledge.com/our-customers/authors/publishing-guidelines
lightemittingdiodesperformance@gmail.com
Editors
- Professor Lt. Dr. T.D. Subash; Mangalam College of Engineering, Kerala (IN)
- Professor Dr. J. Ajayan; SR University Telangana (IN)
- Dr. Wladek Grabinski; MOS AK (EU)
[@adapteva] Here's a list of awesome semiconductor startups
[@adapteva] Here's a list of awesome semiconductor startups. If you know of others or if you want to submit a tagline for a company that you work for, submit a PR. Collaboration for the win! #semi https://t.co/pnkUBxSJpe
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Mar 25, 2022
[Andrew Back] Efabless’ CLEAR, a Fully-Open RISC-V ASIC Built on chipIgnite
[Andrew Back] Efabless’ CLEAR, a Fully-Open RISC-V ASIC Built on chipIgnite, Nears its Goal with Days to Go. https://t.co/FPwpRsisjx #FOSSi #OSHW #OpenHardware #OpenSilicon #RISCV #SkyWater #eFPGA #FPGA #semi https://t.co/58Oir3ZW0s
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Retro computing museum in Ukraine destroyed by Russian bomb
Retro computing museum in Ukraine destroyed by Russian bomb https://t.co/wJ7W91U1kk #semi https://t.co/V2zFjeGwua
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[Mannerisms] Fable: The Game-Changer
[Mannerisms] Fable: The Game-Changer https://t.co/QU3QZ60wOC #semi https://t.co/Ep5PCyGbMa
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Mar 24, 2022
[mos-ak] [online registration] Spring MOS-AK Workshop on April 1, 2022
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop
April 1, 2022 (online)
Announcement and C4P
Online Abstract Submission is open (any related enquiries can be sent to absttracts@mos-ak.org)
List of MOS-AK invited speakers (tentative in alphabetic order) :
|
Online Event Registration is open; all registered participants will receive online access link 24h before the event (any related enquiries can be sent to registration@mos-ak.org)
Important Dates:
- Call for Papers: Feb. 2022
- 2nd Announcement: March 2022
- Final Workshop Program: March 28, 2022
- Spring MOS-AK Workshop: April 1, 2022
WG240322
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Mar 23, 2022
[paper] Review of AlGaN/GaN HEMTs Based Devices
Ahmed M. Nahhas
Review of AlGaN/GaN HEMTs Based Devices
American Journal of Nanomaterials. 2019, 7(1), 10-21
DOI: 10.12691/ajn-7-1-2
Department of Electrical Engineering, Umm Al Qura University, Makkah (SA)
Abstract: This paper presents a review of the recent advances of the AlGaN/GaN high-electron-mobility transistors (HEMTs) based devices. The AlGaN/GaN HEMTs have attracted potential for high frequency, voltage, power, temperature, and low noise applications. This is due to the superior electrical, electronic properties, high electron velocity of the GaN. These properties include the GaN wideband gap energy, electrical, optical and structural properties. The based structures of GaN such as AlGaN/GaN are driving the interest in the research areas of GaN HEMTs. Recently, the AlGaN/GaN HEMTs have gained a great potential in radio frequency (RF) and power electronics (PE) based devices and applications. The recent aspects of the AlGaN/GaN HEMTs devices are presented and discussed. The performance of different device demonstrated based on AlGaN/GaN HEMTs are reviewed. The structural, electrical, and optical properties of these devices are also reviewed.
Fig: Schematic of AlGaN/GaN HEMTs
Mar 22, 2022
Postdoctoral position on advanced semiconductor devices at URV, in Tarragona, Spain
The Nanoelectronic and Photonic Systems (NEPHOS) Group at the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV) in Tarragona, Spain, is looking for candidades for a Postdoctoral position funded by the Spanish Ministry of Science.
Candidates which obtained their Ph.D. between January 1, 2014 and December 31, 2019 can apply. The duration of this position is 3 years. Candidates must have performed significant contributions in the field of semiconductor devices during their Ph.D. or later, and this has to be demonstrated by a good number of publications.
Depending on the candidate's background, there are several options for the research project to carry out:
- Organic TFT technology: fabrication, characterization and modeling.
- Organic solar cells technology: fabrication, characterization and modeling.
- Modeling (in particular compact modeling) and electrical characterization of 2D semiconductor FETs.
- Modeling (in particular compact modeling) and electrical characterization of nanowire FETs.
The NEPHOS Group at URV is currently working on the physics, characterization and modeling (in particular compact modeling) of emerging devices, and also in the fabrication and characterization of nanostructured organic photovoltaic devices. Regarding emerging devices, the present interests of the group at URV are the characterization and modeling of nanowire MOSFETs, GaN HEMTs, Graphene and 2D semiconductor FETs and organic and oxide TFTs. Other interests are the fabrication of polymeric TFTs and the modeling of organic solar cells.
Candidates must send their CVs, by March 26 2022 to Prof. Benjamin Iñiguez (Fellow, IEEE)
Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.
Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
Mar 21, 2022
Build Your Own #OpenSource #Handheld #Linux PC with Raspberry Pi
Build Your Own #Handheld #Linux PC with Raspberry Pi and this #OpenSource Project - It's FOSS News https://t.co/O4EGxl3uEg #semi https://t.co/bQ7p6f235Y
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Andy Grove: Refugee, Tech Pioneer And Immigrant Entrepreneur
[https://t.co/Q7bVAGjIDF] Andy Grove: Refugee, Tech Pioneer And Immigrant Entrepreneur #tech #entrepreneur #semi https://t.co/0NlzVyQcvM
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Mar 18, 2022
Tso-Ping Ma (1945−2021)
Tso-Ping Ma (1945−2021) Nat Electron (2022) DOI: 10.1038/s41928-022-00737-7 https://t.co/KIPrHhK8tP #semi https://t.co/CdqeSYaRBY
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Transistor qubits heat up - Nature Electronics, Published online: 18 March 2022; doi:10.1038/s41928-022-00736-8 https://t.co/TpDZiVWvCH #semi https://t.co/8EFVKCIjsD
Transistor qubits heat up - Nature Electronics, Published online: 18 March 2022; doi:10.1038/s41928-022-00736-8 https://t.co/TpDZiVWvCH #semi https://t.co/8EFVKCIjsD
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[paper] Compound-Semiconductor Memory on Silicon
Peter D. Hodgson, Dominic Lane, Peter J. Carrington, Evangelia Delli,
Richard Beanland, and Manus Hayne
Richard Beanland, and Manus Hayne
ULTRARAM: A Low-Energy, High-Endurance,
Compound-Semiconductor Memory on Silicon
Adv. Electron. Mater. 2022, 2101103
DOI: 10.1002/aelm.202101103
Department of Physics, University of Warwick (UK)
Abstract: ULTRARAM is a nonvolatile memory with the potential to achieve fast, ultralow-energy electron storage in a floating gate accessed through a triple-barrier resonant tunneling heterostructure. Here its implementation is reported on a Si substrate; a vital step toward cost-effective mass production. Sample growth using molecular beam epitaxy commences with deposition of an AlSb nucleation layer to seed the growth of a GaSb buffer layer, followed by the III–V memory epilayers. Fabricated single-cell memories show clear 0/1 logic-state contrast after ≤10 ms duration program/erase pulses of ≈2.5 V, a remarkably fast switching speed for 10 and 20 µm devices. Furthermore, the combination of low voltage and small device capacitance per unit area results in a switching energy that is orders of magnitude lower than dynamic random access memory and flash, for a given cell size. Extended testing of devices reveals retention in excess of 1000 years and degradation-free endurance of over 107 program/erase cycles, surpassing very recent results for similar devices on GaAs substrates.
Fig: ULTRARAM device concept. a) Schematic cross-section of a device with corresponding material layers. The floating gate (FG), triple-barrier resonant-tunneling structure (TBRT), and readout channel are highlighted. Arrows indicate the direction of electron flow during program/ erase operations. b) Scanning electron micrograph of a fabricated device of 10 µm gate length.
Acknowledgements: P.D.H. and D.L. contributed equally to this work. This work was supported by the Engineering and Physical Sciences Research Council, UK, via the 2017–2020 Impact Acceleration Account funding allocation to Lancaster University under grant EP/R511560/1, a scholarship under grant EP/N509504/1, equipment funding under grant EP/T023260/1, and the Future Compound Semiconductor Manufacturing Hub grant EP/P006973/1, by the ATTRACT project funded by the EC under Grant Agreement 777222 and by the Joy Welch Educational Charitable Trust.
[paper] Electron Mobility Distribution in FD-SOI MOSFETs
Nima Dehdashti Akhavana, Gilberto Antonio Umana-Membrenoa, Renjie Gua, Jarek Antoszewskia, Lorenzo Faraonea and Sorin Cristoloveanub
Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach
Solid-State Electronics; Available online 14 March 2022, 108283
DOI: 10.1016/j.sse.2022.108283
a The University of Western Australia, Crawley (AU)
b IMEP-LAHC, INP Minatec, Grenoble (F)
Abstract: Modern electronic devices consist of several semiconductor layers, where each layer exhibits a unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.
Fig: Qinv is defined as the electron density per unit length at the maximum
of the first subband (top of the barrier) often referred to as a “virtual source”
Acknowledgements: This work was supported by the Australian Research Council (DP170104555), the Horizon 2020 ASCENT EU project (Access to European Nanoelectronics Network – Project no. 654384), the Western Australian node of the Australian National Fabrication Facility (ANFF), and the Western Australian Government’s Department of Jobs, Tourism, Science and Innovation.
An indium oxide-based (#In2O3) #transistor created using atomic layer deposition
An indium oxide-based (#In2O3) #transistor created using atomic layer deposition https://t.co/zv8cpLNPIv #semi https://t.co/sxk3n5Dw0I
— Wladek Grabinski (@wladek60) Mar 17, 2022
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March 17, 2022 at 11:38PM
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This #Diamond #Transistor Is Still Raw, But Its Future Looks Bright
This #Diamond #Transistor Is Still Raw, But Its Future Looks Bright https://t.co/7NbI1TRClJ #semi https://t.co/WH7qrm8DtV
— Wladek Grabinski (@wladek60) Mar 17, 2022
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March 17, 2022 at 11:36PM
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Mar 17, 2022
Prof. Mathieu Luisier appointed as Full Professor of Computational Nanoelectronics at D-ITET
Prof. Mathieu Luisier appointed as Full Professor of Computational Nanoelectronics at D-ITET.
Congratulations!
#ethzurich #electricalengineering #professor #semihttps://t.co/KBIxHhb8rp
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Mar 16, 2022
Zero to ASIC Course https://t.co/65Dy5oHGPD #semi https://t.co/TnON0j7M8h
Zero to ASIC Course https://t.co/65Dy5oHGPD #semi https://t.co/TnON0j7M8h
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[paper] Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs
Sujit K. Singh, Sumreti Gupta, Reinaldo A. Vega* and Abhisek Dixit
Accurate Modeling of Cryogenic Temperature Effects in 10-nm Bulk CMOS FinFETs Using the BSIM-CMG Model
in IEEE Electron Device Letters
DOI: 10.1109/LED.2022.3158495.
Indian Institute of Technology, New Delhi (IN)
*IBM Research, Albany, NY (USA)
Abstract: In this letter, we have proposed modifications to the existing BSIM-CMG compact model to enhance its ability to model the behavior of short channel bulk FinFETs (both n and p-type) from room temperature down to cryogenic temperatures (10K). The proposed model is highly accurate in capturing the subthreshold swing, threshold voltage, and effective mobility trends observed in FinFET cryogenic operation. For efficient optimization of the proposed model parameters, we have proposed an adequate modeling strategy. We have compared convergence time between the existing BSIM-CMG model and the proposed model by simulating a reasonably large circuit using pseudo-inverters.
Fig (a) TEM image of the fin cross-section (b) Measured device layout-related parameters
Mar 15, 2022
[paper] Ultra-Low-Power Imaging System
Andrea Bejarano-Carbo, Hyochan An, Kyojin Choo, Shiyu Liu, Dennis Sylvester,
David Blaauw and Hun-Seok Kim,
Millimeter-Scale Ultra-Low-Power Imaging System for Intelligent Edge Monitoring
inyML Research Symposium’22, March 2022, San Jose, CA
rXiv:2203.04496v1 [eess.SP] 9 Mar 2022
University of Michigan, Ann Arbor, Michigan, USA
ABSTRACT Millimeter-scale embedded sensing systems have unique advantages over larger devices as they are able to capture, analyze, store, and transmit data at the source while being unobtrusive and covert. However, area-constrained systems pose several challenges, including a tight energy budget and peak power, limited data storage, costly wireless communication, and physical integration at a miniature scale. This paper proposes a novel 6.7×7×5mm imaging system with deep-learning and image processing capabilities for intelligent edge applications, and is demonstrated in a home-surveillance scenario. The system is implemented by vertically stacking custom ultra-low-power (ULP) ICs and uses techniques such as dynamic behavior-specific power management, hierarchical event detection, and a combination of data compression methods. It demonstrates a new image-correcting neural network that compensates for nonidealities caused by a mm-scale lens and ULP front-end. The system can store 74 frames or offload data wirelessly, consuming 49.6μW on average for an expected battery lifetime of 7 days.
Fig: Imager system cross-section
Acknowledgments:The authors would like to thank Sony Semiconductor Solutions Corp./Sony electronics Inc. for supporting this work.
Mar 14, 2022
Faster #analog #computer could be based on mathematics of complex systems
Faster #analog #computer could be based on mathematics of complex systems https://t.co/A0iTUZK2U9 #semi https://t.co/Cn0cfGZHqZ
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Creating sub-1-nm gate lengths for MoS2 transistors
Creating sub-1-nm gate lengths for MoS2 transistors https://t.co/7E4V3Bp3Bz #semi https://t.co/1pwI2wUajO
— Wladek Grabinski (@wladek60) Mar 14, 2022
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Mar 9, 2022
[mos-ak] [2nd Announcement and C4P] Spring MOS-AK Workshop on April 1, 2022 (online)
Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
Spring MOS-AK Workshop
April 1, 2022 (online)
2nd Announcement and C4P
Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
W.Grabinski for Extended MOS-AK Committee- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based memory
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
- Technology R&D, DFY, DFT and reliability/aging IC designs
- Foundry/Fabless Interface Strategies
Online Abstract Submission to be open (any related enquiries can be sent to absttracts@mos-ak.org)
Online Event Registration to be open (any related enquiries can be sent to registration@mos-ak.org)
Important Dates:
- Call for Papers: Feb. 2022
- 2nd Announcement: March 2022
- Final Workshop Program: March 22, 2022
- Spring MOS-AK Workshop: April 1, 2022
WG090322
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Silicon Nitride PICs | March 21-22 | Onsite or Online
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