conference paper reached 400 reads

Bucher, M., J-M. Sallese, F. Krummenacher, D. Kazazis, C. Lallement, W. Grabinski, and C. Enz

EKV 3.0: An analog design-oriented MOS transistor model

In 9th International Conference on Mixed Design of Integrated Circuits and Systems

(MIXDES 2002)

Abstract:  The EKV 3.0 compact MOS transistor model for advanced analog IC design and simulation is presented. The model is based on the surface potential approach combined with inversion charge linearization. The ideal long-channel model is coherent  for  static  and  dynamic  aspects  including  noise.  The  ideal  model  is  extended  for  high-field  effects  in  deep submicron CMOS technologies. Scalability over channel length and width is achieved while retaining a reduced number of parameters. The EKV 3.0 model is applicable over a large range of CMOS technologies.  

Fig: Normalized source transconductance to current ratio (gm/ID) vs. normalized current, measured 

(markers) in saturation from various CMOS technologies, and analytical model.

[paper] Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries

Mike Brinson and Felix Salfelder 

Compact device modeling and simulation with Qucs/Qucs-S/Xyce modular libraries 

In 28th MIXDES (2021), pp. 35-40 

DOI: 10.23919/MIXDES52406.2021.9497545 

Abstract—The rapid development of new semiconductor materials and devices has highlighted the need for compact modeling and circuit simulation tools that can be easily adapted to accommodate emerging technologies. In most instances device modeling tools employ non-linear behavioural sources and Verilog-A modules for model prototype construction. This paper is concerned with the properties and application of modular user defined/plugin library toolkit that combines the best features of behavioural source and Verilog-A modeling practice while encouraging user extensions. The toolkit has been implemented as a Qucs/Qucs-S/Xyce modular library that is loadable on demand. To demonstrate its capabilities and flexibility a series of compact device models are introduced and their simulated performance presented and evaluated.

Fig: A Qucs-S/Xyce test bench for simulating and displaying BJT Ic/V ce

output characteristics with 1µA ≤ Ib ≤ 10µA in 1µA steps.