Saturday, November 30, 2019

#paper A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4. doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs https://t.co/8bzoxK27ru


from Twitter https://twitter.com/wladek60

November 30, 2019 at 06:12PM
via IFTTT

Friday, November 29, 2019

PhD Positions at Institute for Microelectronics/TU Wien

PhD Positions
on Characterization, Modeling and Circuit Simulation in Microelectronics
Institute for Microelectronics/TU Wien


The Institute for Microelectronics is a world leading research institute focused on the reliability of circuit components (especially transistors). In addition to conventional Si transistors, the behavior of SiC devices designed for high-power applications is also at the center of interest. The broad field of research conducted at the Institute of Microelectronics ranges from characterization, physical modeling and ab-initio simulations to compact modeling and circuit simulation. For the characterization of transistors, the Institute for Microelectronics has a modern laboratory equipped with commercial and custom-built measurement instruments. To explain the experimental data, elaborate physical models are developed and constantly improved. The models are directly incorporated into state-of-the-art device simulators, i.e. MinimosNT and Comphy. To perform computationally expensive simulations a modern computer cluster is while for circuit simulations Cadence and Synopsis spice simulators are available.

The institute is currently looking for highly talented and motivated young researchers to join the team in one of the following areas:
  • Physical modeling of silicon-carbide transistors
  • Single-defect characterization of low-noise silicon transistors
  • Development of custom-made measurement instruments
  • Circuit simulations using advanced implementation of reliability models in Verilog-A for SPICE
For the positions knowledge in one or more of the following areas is advantageous to complement our team:
  • C/C++ and Python
  • Semiconductor device physics
  • Circuit simulation
  • Implementation of new compact/physical models
  • Handling of device/circuit simulators
  • Design of discrete analog circuits and hardware/software solutions
  • Wafer probers and instruments for microelectronics
  • Keithley instruments and scripting language LUA
  • Measurement techniques in microelectronics (MSM, C(V), DLTS, charge pumping etc.)
As a teaching institution, knowledge transfer and close cooperation with students are very importance. The applicants should like to work together with students and supervise Master’s and Bachelor theses.

Starting Date: As soon as possible

Salary: Three-year positions (40hours/week) are in accordance with the salary regulations of the Austrian Science Fund. The gross annual salary is approximately EUR 40,300

Application Material: Please provide a detailed CV, your collective certificates, your Master’s thesis (weblink or PDF), and a single-page motivation letter (discussing relevant previous experience related to the desired skills and experiences) and summarize your motives for joining us.

Application: Please submit your application to jobs@iue.tuwien.ac.at.
Application Deadline: The positions will remain open until filled.

#paper J. A. D. Alamo, "Kudos to Our Golden Reviewers," in IEEE Electron Device Letters, vol. 40, no. 12, pp. 1891-1891, Dec. 2019. doi: 10.1109/LED.2019.2953249 https://t.co/dVuoduU4Di https://t.co/XAmjPMHry7

and some 2019 EDL Review Statistics:

from Twitter https://twitter.com/wladek60
https://t.co/dVuoduU4Di pic.twitter.com/XAmjPMHry7
— Wladek Grabinski (@wladek60) November 29, 2019

November 29, 2019 at 11:45AM
via IFTTT

Do want to do a #PhD with two of the best #companies in the #world and #receive highly #competitive salary package? More #information here: https://t.co/PyBHCi2z7y https://t.co/JXua7rZGAn #modeling https://t.co/2cd5mE3fJt


from Twitter https://twitter.com/wladek60

November 29, 2019 at 11:31AM
via IFTTT

Thursday, November 28, 2019

X-FAB 车规级特色工艺技术研讨会 诚挚邀请您参加在深圳举办的技术研讨会,共同发掘合作新契机! https://t.co/hhv4z3m9dE #modeling https://t.co/kELItLlPMC


from Twitter https://twitter.com/wladek60

November 28, 2019 at 01:42PM
via IFTTT

imec jobs Postdoctoral Researcher III-N MOCVD on Si https://t.co/S61MYHsymx #modeling https://t.co/nUH8nrjyUg


from Twitter https://twitter.com/wladek60

November 28, 2019 at 11:35AM
via IFTTT

#Opensource software on the rise in #Africa [DW | 27.11.2019] https://t.co/S5jwjQgJZt https://t.co/J9RBSdFd95


from Twitter https://twitter.com/wladek60

November 28, 2019 at 09:47AM
via IFTTT

Wednesday, November 27, 2019

Why do we contribute to #opensource software? https://t.co/Mygk0E4uPs https://t.co/J6TXnk7ZEz


from Twitter https://twitter.com/wladek60

November 27, 2019 at 11:40AM
via IFTTT

Open PhD/PostDoc positions at the University of Pisa

device and 2D materials modeling, analog circuit design, 
power electronics, wireless sensors design

We are in the process of opening a few positions for PhD students and for Post Docs at the University of Pisa, in the fields of modeling of nanoscale electron devices, 2D materials, analog circuit design, power electronics design and wireless sensors for harsh environments. We are now asking for expressions of interest from perspective candidates.

I would be very grateful if you could forward this information to whom you think could be interested in applying.

Expressions of interest must be submitted by email, together with a CV and contact information by 31 Dec 2019 to giuseppe.iannaccone@unipi.it.

The available research topics are listed below. They are typically performed in the framework of a larger project within a European collaboration or of a bilateral project with an industrial sponsor.

1. Theoretical investigation of ultra-low-power nanoscale transistors and memories for large scale integrated circuits. This will include devices based on heterostructures of 2D materials. We are looking for candidates with strong background in Electrical Engineering and/or Physics.

2. Quantum engineering of materials and devices based on heterostructures of 2D materials. This activity is based on materials modeling with quantum chemistry methods and quantum transport modeling. We are looking for candidates with strong background in Physical Chemistry and/or Physics.

3. Design of low-power analog integrated circuits for analog hardware  accelerators of artificial intelligence (deep learning) algorithms and for new computing architectures. We are looking for candidates with strong background in Electrical Engineering.

4. Design of low-power mixed signal circuits for security hardware, such as physical unclonable functions and hardware security signatures. We are looking for candidates with strong background in Electrical Engineering.

5. Modeling of power devices based on GaN and SiC for performance and reliability optimization and model development. We are looking for candidates with strong background in Electrical Engineering and/or in Physics.

6. Design of highly efficient power management circuits and systems based on switched capacitors. Both circuits based on silicon technology, on SiC and on GaN will be considered. We are looking for candidates with strong background in Electrical Engineering.

PhD positions are for three years, Post Doc positions are initially for one year and might be renewed for up to four years. Positions of shorter duration (for visiting students/scholars or for MS  thesis projects) might be considered depending on the expertise of the candidate and the definition of a suitable subproject.

For additional information and specific information on the projects, please send an email to
Prof. Giuseppe Iannaccone
giuseppe.iannaccone@unipi.it

Tuesday, November 26, 2019

#paper W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC, Krakow, Poland, 2019, pp. 190-193. doi: 10.1109/ESSDERC.2019.8901822 https://t.co/rONWC5mTQE https://t.co/Sw8iobvIai


from Twitter https://twitter.com/wladek60

November 26, 2019 at 09:13PM
via IFTTT

Friday, November 22, 2019

ADF Germany on Dec.4 | NI AWR Design Environment Seminar is FREE to attend. Lunch and refreshments are complimentary. https://t.co/NfuD8MRJFd #paper https://t.co/9uDP61kXwz


from Twitter https://twitter.com/wladek60

November 22, 2019 at 11:01AM
via IFTTT

#FOSS Portal: Free and open-source software - Wikipedia https://t.co/EK2xk0walv #paper https://t.co/yVjzu6xKFw


from Twitter https://twitter.com/wladek60

November 22, 2019 at 10:23AM
via IFTTT

Tuesday, November 19, 2019

[Conference Reports] 2019 Symposia on VLSI Technology and Circuits: Pushing the Limits of Semiconductors for a United and Connected World in IEEE SSC Magazine, vol. 11, no. 4, pp. 83-86, Fall 2019 doi: 10.1109/MSSC.2019.2939456 https://t.co/f51V2MT0S9 #paper https://t.co/pe9IUWra4X


from Twitter https://twitter.com/wladek60

November 19, 2019 at 08:47PM
via IFTTT

MOS-AK India #45395 is now published in IEEE Xplore

2019 IEEE Conference on Modeling of Systems Circuits and Devices 
(MOS-AK India) - #45395 
is now published in IEEE Xplore

Conference Record #45395

Dear Arifuddin Sohel, Desai UB, Govindacharyulu P.A, Wladek Grabinski, Venkatesh N

Congratulations! 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) has been posted to the IEEE Xplore digital library effective 2019-11-18.

Along with publication in IEEE Xplore, IEEE assures wide distribution of conference proceedings by providing abstracting and indexing information of all individual conference papers to worldwide databases. IEEE makes every reasonable attempt to ensure that abstracts and index entries of content accepted into the program are included in databases provided by independent abstracting and indexing services. Each abstracting and indexing partner makes its own editorial decision on what content to include. IEEE cannot guarantee entries are included in any particular database.

IEEE Meetings, Conferences & Events (MCE)
445 Hoes Lane, Piscataway, NJ 08854 USA
IEEE: Advancing Technology for Humanity

#paper J. Trommer, M. Simon, S. Slesazeck, W. M. Weber and T. Mikolajick, "Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs," ESSDERC 2019, Krakow, 10.1109/ESSDERC.2019.8901730 https://t.co/xGNhchlT24 https://t.co/RpSsxIkfe8


from Twitter https://twitter.com/wladek60

November 19, 2019 at 05:51PM
via IFTTT

#paper K. Harrouche, R. Kabouche, E. Okada and F. Medjdoub, "High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave Operation," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1145-1150, 2019. doi: 10.1109/JEDS.2019.2952314 https://t.co/jNkb9EJ9Zn https://t.co/eVGvTeltX5


from Twitter https://twitter.com/wladek60

November 19, 2019 at 02:54PM
via IFTTT

#paper Faber, H., Anthopoulos, T.D. Adding a new layer to ‘more than Moore’. Nat Electron 2, 497–498 (2019) doi:10.1038/s41928-019-0329-8 https://t.co/0DGQKfB8PA https://t.co/BvjI3yrezw


from Twitter https://twitter.com/wladek60

November 19, 2019 at 10:38AM
via IFTTT

#paper D. Mahajan, S. A. Albahrani, R. Sodhi, T. Eguchi and S. Khandelwal, "Physics-Oriented Device Model for Packaged GaN Devices," in IEEE TPE doi: 10.1109/TPEL.2019.2953060 https://t.co/fZEFBTrvHg https://t.co/aFN8iGGVDA


from Twitter https://twitter.com/wladek60

November 19, 2019 at 10:20AM
via IFTTT

Wednesday, November 13, 2019

Czochralski IEEE Milestone Event (Nov.15 2019) Hochschule für Technik und Wirtschaft Berlin University of Applied Sciences - HTW Berlin https://t.co/MzxFrFUbTf #paper https://t.co/4HZPQe4WeA


from Twitter https://twitter.com/wladek60

November 13, 2019 at 11:32AM
via IFTTT

Monday, November 11, 2019

#paper F. Ávila Herrera, et al., "Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization," in IEEE JEDS doi: 10.1109/JEDS.2019.2948648 doi: 10.1109/EDTM.2019.8731246 https://t.co/7E9755kTOW https://t.co/vh1Zy9BifJ


from Twitter https://twitter.com/wladek60

November 11, 2019 at 08:32PM
via IFTTT

8th International NRNU MEPhI Workshop

VIII Международный научно-методический семинар по средствам автоматизированного проектирования интегральных микросхем для физического эксперимента совместно с компанией Cadence

it is our pleasure to announce the 8th International Workshop and school on computer aided design of integrated circuits for physical experiments to be held at NRNU MEPhI on November 25-27, 2019. The Workshop and school are organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information are available via site cad.mephi.ru.

Participation in the event is free of charge but registration is necessary.

E. Atkin, NRNU MEPhI event secretary,

Thursday, November 7, 2019

#paper Tengteng Lu, Zhen Li, Chao Luo, Jun Xu, Weicheng Kong, and Guoping Guo Characterization and Modeling of 0.18µm CMOS Technology at sub-Kelvin Temperature IEEE TED 2018 https://t.co/4lkzLP9jvz https://t.co/4QUcjG94EY


from Twitter https://twitter.com/wladek60

November 07, 2019 at 03:27PM
via IFTTT

#paper Alam, M.N.K., Roussel, P., Heyns, M. et al. Positive non-linear capacitance: the origin of the steep subthreshold-slope in ferroelectric FETs. Sci Rep 9, 14957 (2019) doi:10.1038/s41598-019-51237-2 https://t.co/zWwduLz8pB https://t.co/6pXnXiXjW8


from Twitter https://twitter.com/wladek60

November 07, 2019 at 10:24AM
via IFTTT

Wednesday, November 6, 2019

#Google Is Helping Design an #OpenSource, Ultra-Secure #Chip. #OpenTitan is a so-called secure enclave based on open source that could shake up hardware security. https://t.co/Kaqgh5xTh0 https://t.co/CiL5HGuoJa


from Twitter https://twitter.com/wladek60

November 06, 2019 at 05:07PM
via IFTTT

N. Makris, M. Bucher, F. Jazaeri and J. Sallese, "CJM: A Compact #Model for Double-Gate Junction FETs," in IEEE JEDS. doi: 10.1109/JEDS.2019.2944817 https://t.co/3kba45imdB https://t.co/9WqLtmG2Jl


from Twitter https://twitter.com/wladek60

November 06, 2019 at 05:03PM
via IFTTT

Tuesday, November 5, 2019

Si2 Compact Model Coalition Releases #SPICE #Model for Advanced IC Designs Twenty #CMC Members Benefit from 18-Month Access to New Standard Model https://t.co/yQyblGXwuG https://t.co/nUX9XtQESq


from Twitter https://twitter.com/wladek60

November 05, 2019 at 04:42PM
via IFTTT

#paper A. Rassekh, F. Jazaeri, M. Fathipour and J. Sallese, "Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects," in IEEE TED, vol. 66, no. 11, pp. 4653-4659, Nov. 2019. doi: 10.1109/TED.2019.2944193 https://t.co/Ccg4wQtcG5 https://t.co/sBLZMVxcZo


from Twitter https://twitter.com/wladek60

November 05, 2019 at 02:41PM
via IFTTT

Monday, November 4, 2019

Futurehorizons Silicon Chip Industry Workshop Monday Nov 11 2019 Holiday Inn - Kensington Forum, 97 Cromwell Road, London https://t.co/YSQduuwVGn #paper https://t.co/AKkgonXxby


from Twitter https://twitter.com/wladek60

November 04, 2019 at 05:38PM
via IFTTT

#paper C. Prasad, "A Review of Self-Heating Effects in Advanced CMOS Technologies," in IEEE #TED, vol. 66, no. 11, pp. 4546-4555, Nov. 2019. doi: 10.1109/TED.2019.2943744 https://t.co/gAh4CAmDzu https://t.co/hyaCcsktDQ


from Twitter https://twitter.com/wladek60

November 04, 2019 at 04:55PM
via IFTTT

IEDM Panel Dec 10 Rest in Peace Moore’s Law, Long Live AI Moderator: Vijay Narayanan, IBM Panelists: Vivek De Intel Wilfried Haensch IBM Mike Henry Mythic Ron Ho Facebook Seongjun Park Samsung Dimitri Strukov UCSB Douglas Yu TSMC https://t.co/G3Yy5XpIPK #paper https://t.co/ffijI0TpMP


from Twitter https://twitter.com/wladek60

November 04, 2019 at 11:09AM
via IFTTT

BCICTS 2019: 2b. High Frequency Characterisation Tuesday 8:00 AM - Blackbird A/B Session Chair: Breandán Ó hAnnaidh, Analog Devices Co-Chair: Sadayuki Yoshitomi, Toshiba https://t.co/hghKdEx9ty #paper https://t.co/SbPScPM0ee


from Twitter https://twitter.com/wladek60

November 04, 2019 at 08:28AM
via IFTTT

6 remarkable features of the new #UN #opensource #initiative https://t.co/UCk0xLbtL5 https://t.co/uNGBipmWrx


from Twitter https://twitter.com/wladek60

November 04, 2019 at 09:29AM
via IFTTT

Friday, November 1, 2019

#paper: Versatile model for the contact region of organic thin-film transistors A.Romeroab J.Gonzáleza M.J.Deenc J.A.Jiménez-Tejadab https://t.co/9wJwjKlu69 https://t.co/rFCp02RFEF


from Twitter https://twitter.com/wladek60

November 01, 2019 at 03:56PM
via IFTTT

#Indian #startups have raised a record $11.3B this year – TechCrunch https://t.co/qiJE1BnlV1 #paper https://t.co/yDn1H7aiPJ


from Twitter https://twitter.com/wladek60

November 01, 2019 at 03:03PM
via IFTTT

Openings for Research Staff and PhD Scholarships Singapore-MIT Alliance for Research and Technology Low Energy Electronic Systems - Phase II 1 CREATE Way 09-01/02 CREATE Tower; 01-13 Enterprise Wing Singapore 138602 https://t.co/hUapbZCyAU #paper https://t.co/VNFXBjlxRY


from Twitter https://twitter.com/wladek60

November 01, 2019 at 02:01PM
via IFTTT

Program to convert Sandia’s Albuquerque, N.M.-based fab from 150mm (6-inch) to 200mm (8-inch) wafer sizes. As part of the move, Sandia is converting its 0.35-micron (350nm) rad-hard process from 150mm to 200mm. The process is called CMOS7 https://t.co/JrWmF8BV0a #paper https://t.co/FJasxsp3s1


from Twitter https://twitter.com/wladek60

November 01, 2019 at 01:55PM
via IFTTT