Dec 28, 2009

Download EUROSOI 2010 Final Programme

The final EUROSOI 2010 Programme is available for download.


Semiconductor-On-Insulator Materials, Devices and Circuits, Physics, Technology and Diagnostics

6th International SOI Conference and 1st Ukrainian-French Seminar

26-30 April 2010, Kyiv, Ukraine

The topics to be covered include the following:
· Semiconductor-on-Insulator (SOI) material technology
· Nanoscale CMOS devices and circuits
· New SOI materials and devices on its basis
· SOI sensors and new SOI systems
· Diagnostic techniques for nanoscale SOI materials and devises
· Technology and economics

Organized by
· Jean-Pierre Raskin
Universite Catholique de Louvain, Electrical Engineering Department, IMIC
· Alexei N. Nazarov
Inst. of Semiconductor Physics, NAS of Ukraine
· Yuri Gomeniuk
Inst. of Semiconductor Physics, NAS of Ukraine


Dec 23, 2009

[mos-ak] MOS-AK/GSA Baltimore meeting on-line publications

MOS-AK/GSA Baltimore meeting on-line publications are available:

I would like to thank all MOS-AK contributors, speakers and panelists
for sharing their compact modeling competence, R&D experience and
delivering valuable MOS-AK presentations. I am sure, that our modeling
event in Baltimore was beneficial to all MOS-AK Workshop attendees.

Organization of our modeling event would not be possible without our
generous sponsor: the IEEE EDS/SSCS Baltimore Chapter. I also would
like to personally acknowledge local organizers, in particular Prof.
Andreas G. Andreou for his dedication, commitment and providing smooth

I hope, we would have a next chance to meet all of you and your
academic and industrial partners at future MOS-AK/GSA modeling events
(listed below).

-- with my worm seasons greetings - WG (for the MOS-AK/GSA)
* Rome: April 8-9,
* Tarragona: June'10
* Wroclaw: June 24-26
* Seville: Sept. 18


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Dec 22, 2009

EDN: The top ten analog engineers

I've just seen this post at EDN. They are talking (yes, it's second-hand talk) about a list of the 10 top analog engineers. Do you think that we could make a similar list for the 10 top Compact Modelers?
Who would you put in such a list? I'd put names of people like Chenming Hu, Erik Vittoz, who are currently in active, but I'm probably too young (;-D) to put older names....
Anyway, actually, Compact Modeling is more about teamwork than about an isolated genius... so I guess that making lists maybe makes not a lot of sense... Or does it?

Dec 18, 2009

Compact Modeling Principles, Techniques and Applications

Gildenblat, Gennady (Ed.)
2010, Approx. 250 p., Hardcover
ISBN: 978-90-481-8613-6

The book includes chapters on the MOSFET noise theory, benchmarking of MOSFET compact models, modeling of the power MOSFET, and an overview of the bipolar modeling field. It concludes with two chapters describing the variability modeling including some recent developments in the field.

Table of contents

Student group works on designs for a fully integrated wireless receiver

The group, known as the Microelectronics Students’ Group, has quickly captivated new members and is now composed of more than 20 students. They are presently working towards the design of a fully integrated wireless receiver in sub-micron CMOS.


Dec 11, 2009

Job offer for Modelling Engineer

I copy a job offer I found:

EM Modeling Engineer

Company: Peregrine Semiconductor
Location: San Diego, CA
Please submit resumes to

Job Description:

Responsible for device and package modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process technology. Job functions include: Package model development, RF passive model development, parasitic analysis, test hardware/software setup, statistical modeling, model implementation on multiple EDA platforms. The candidate will work closely with senior modeling engineers to provide a comprehensive set of models to our design engineers as well as foundry customers.


Education Desired and Experience
PhD in Electrical Engineering or MSEE with 5 years experience in EM modeling.
Must have knowledge base in the following areas:
Strong understanding of electromagnetic theory.
Understanding of transmission line theory.
Experience using SPICE like circuit simulators.
Experience using EM simulators (HFSS, Sonnet, IE3D).
Basic understanding of semiconductor manufacturing.
Basic understanding of semiconductor packaging.
Demonstrated ability developing automation scripts using MATLAB, Perl, MathCad, UNIX scripting, etc.
Knowledge in one or more of the following areas is highly desirable:
EM simulation on semiconductor substrates
Package model or RF model development.
Large signal device or circuit characterization and modeling
Monte Carlo/ statistical modeling
Layout optimization for RF applications
Understanding of the following tools or similar:
Cadence Design System (Virtuoso, Analog Artist, Assura, etc)
Agilent Design System (ADS, Momentum, RFDE)
Good written and oral communication skills.
Must be able to work well in a team environment.

Dec 3, 2009

Controllable Molecular Modulation of Conductivity in Silicon-Based Devices

Tao He, David A. Corley, Meng Lu, Neil Halen Di Spigna, Jianli He, David P. Nackashi, Paul D. Franzon and James M. Tour
J. Am. Chem. Soc., 2009, 131 (29), pp 10023–10030


The electronic properties of silicon, such as the conductivity, are largely dependent on the density of the mobile charge carriers, which can be tuned by gating and impurity doping. When the device size scales down to the nanoscale, routine doping becomes problematic due to inhomogeneities. Here we report that a molecular monolayer, covalently grafted atop a silicon channel, can play a role similar to gating and impurity doping. Charge transfer occurs between the silicon and the molecules upon grafting, which can influence the surface band bending, and makes the molecules act as donors or acceptors. The partly charged end-groups of the grafted molecular layer may act as a top gate. The doping- and gating-like effects together lead to the observed controllable modulation of conductivity in pseudometal− oxide−semiconductor field-effect transistors (pseudo-MOSFETs). The molecular effects can even penetrate through a 4.92-μm thick silicon layer. Our results offer a paradigm for controlling electronic characteristics in nanodevices at the future diminutive technology nodes.

DOI: 10.1021/ja9002537

The International Winter School: Beyond Moore’s Law, 2010 (BML2)

The BML2 will be held in the Suites Hotel in Jeju island, Korea during the period of February 1-5, 2010. Jeju island is located at the southern end of the South Korea and is famous for its beautiful landscape and mild whether.

Recognizing the inevitability of the ultimate limit to the "downsizing" of Si feature size within the next 5 to 10 years (or the end of "Moore's Law"), as well as the ever-increasing need for denser, faster and less dissipative logic, memory and sensors, this school will examine several promising new nanoelectronic technologies that appear to respond to this need. To this end, the sponsoring agencies from Korea, Taiwan and the US have assembled an international group of distinguished lecturers who will provide guidance through formal lectures, as well as via informal workshops in which the attendees can ask questions and interact with those same lecturers. It is hoped that the school will help guide the selected attendees to follow careers in these emerging research areas and to become future leaders in advancing the field of information technology. The school also may help in establishing relations between young scientists from other countries, relations that it is hoped may lead to future international collaboration.

Detailed information regarding the venue and travel to the conference site can be found in the official website of the Winter School.

Dec 1, 2009

[mos-ak] Final Program: MOS-AK Workshop in Baltimore

--- The Final MOS-AK/Baltimore Workshop program is available on-line:

--- Workshop location:
* Johns Hopkins University at Homewood Campus in the Computational
Sciences and Engineering
* Building (CSEB) Room CSEB 17
* <

--- No registration fee thanks to our organizers and sponsors.
To help our local organizers with local logistic and other
arrangements, we would suggest to register on-line

--- MOS-AK/Baltimore Committee:
* Andreas G. Andreou, JHU; Technical Program Chair
* Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair
* Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair
* Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG
Europe Chair
* Chelsea Boone GSA; Senior Research Analyst
* Darryl Leavitt, GSA; Director of Events
* Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager


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Nov 30, 2009

Circuit Simulation with SPICE OPUS, Theory and Practice

Authors: Tadej Tuma, Árpád Bûrmen

The Complete Book on Contemporary Circuit Design
Series: Modeling and Simulation in Science, Engineering and Technology
ISBN: 978-0-8176-4866-4, 2009, Hardcover; A Birkhäuser book

Download simulation examples from chapter 7 ( 23KB)

More about the book ...

Visit also OPUS Spice web site.

Nov 18, 2009

[mos-ak] [Dec.9, 2009] MOS-AK Meeting at Baltimore // 2nd announcement

Please visit the MOS-AK/Baltimore Meeting web page

with updated:
* Speakers list:

* Extended Panel Session:

* To register, use available Free On-line Registration form:

* Important dates:
# Nov.30 Final program
# Dec.9, 2009 MOS-AK/GSA Workshop
# collocated with:
* IEDM Conference (Dec.6-9 <>)
* CMC Meeting (Dec.10-11 <>)
* ISDRS Symposium (Dec. 9-11 <>

* MOS-AK/Baltimore Committee:
* Andreas G. Andreou, JHU; Technical Program Chair
* Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair
* Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair
* Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG
Europe Chair
* Chelsea Boone GSA; Senior Research Analyst
* Darryl Leavitt, GSA; Director of Events
* Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager


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Touchstones of a Quality Compact Model

This paper appears in: Electron Devices, IEEE Transactions on; Nov. 2009; Vol. 56, No. 11; pp: 2374-2375

Authors frequently submit manuscripts to the Transactions in the area of Compact Modeling. It is a subject of much scholarly activity and one of widespread interest to our readers, many of whom are practitioners of semiconductor technology. The reasons for the popularity of this subject area are of course only known to the readers, but it is not unlikely that it is due to the popularity of the models themselves, which in turn may be due to the comparative ease of use which is a prominent feature of most compact models. Simulations using compact models are relatively quick and do not require powerful, high-speed computers to execute. Yet, because of their form, the underlying physics is easy to discern.
The Editorial Board of the Transactions intends to continue to encourage original submissions in this field, but as we do in all subject areas that fall within our scope, we are keenly interested in maintaining and even elevating the quality of the papers we publish in this area. One means of accomplishing this objective is to become more rigorous in rejecting papers that may be technically sound, but are not particularly original or may deal with a narrow, perhaps even trivial aspect of device physics. Conversely, another means is to encourage and stimulate more high quality submissions, which immediately begs the question "What is the definition of high quality?"
Defining quality is not a simple task. However, in may be sufficient to describe some of the attributes of a quality model and thereby prescribe the content of what might be a quality paper on the subject. To wit, a quality model ought to be usable in some way when applied to real devices. It should comprehend all relevant effects of realistic short channel devices. In general, models are more credible if they match experimental data. (An exception might be devices so new that neither samples nor data are readily available.) However, sometimes this is not sufficient since models with large numbers of fitting parameters are really more mathematical and empirical than physical. These types of models miss one of the key attributes of a good compact model viz. the ability to gain an insight into the physics that dominates the operation of the device under study. On the other hand, models that are too narrow in scope miss another key attribute, that is the ability to provide sufficient accuracy to obviate the need to conduct full-blown simulations with all of the concomitant resource demands.
Many compact modeling submissions are related to subthreshold analyses which can be very useful for threshold voltage analysis including quantifying of drain-induced barrier lowering effects and subthreshold slopes. Often, they are based upon idealized abstractions of devices that have the benefit of enabling analytic solutions and if the purpose is simply to elucidate the controlling mechanisms of the device, then this purpose is served. However, often the intent is not explicit and the reader is left with the impression that the model is predictive. Authors may unwittingly contribute to this impression by using TCAD simulations to "verify" the accuracy of the analytic solution, but the simulations are often of the same idealized devices. That is, a demonstration of consistency with TCAD simulations is not necessarily proof that the analytic solution is predictive; rather it may only be a proof that calculations can be used to match the results of numerical methods in specific cases. The question of predictive ability is still open and depends upon whether the simulation, and hence the matching analytic solution, is of a realizable device. This is especially true of modern devices such as multi-gate, three-dimensional MOSFETs where non-idealities have significant effects.
Obviously compact models should be analytical with no differentials, derivatives or integrals. Model parameters should be comparatively easy to extract and their relationship to other parameters should be physically justified. There are other characteristics, one or a few of which, a quality model should exhibit. As an aid to authors, reviewers and editors, we catalog some of these characteristics. A quality compact model should
  • incorporate new physics that improves the accuracy or predictive ability of existing models in a meaningful way, and/or
  • it should demonstrate a novel method or approach that improves the efficiency of the simulations without loss of accuracy, and/or
  • it should take an existing phenomenological or semi-empirical model and establish the physical foundations of the model and/or
  • it should provide new insight into the functioning, performance characteristics, reliability, or limits of conventional devices and ideally should even suggest a means of improvement, and/or
  • it should provide new insights into how existing models are related, and/or
  • it should be predictive of new behaviors which can be subsequently observed and/or,
  • it should clarify the domain of validity of existing models.
By no means is this meant to be a comprehensive list. Nevertheless, we anticipate that it is ample in aggregate to convey the sense of what the Editorial Board considers to be the key features of a quality manuscript on compact modeling.
Finally, we end with a few simple suggestions for authors that when followed could expedite the review process and may even improve the chances of acceptance of a manuscript dealing with compact modeling.
a) When presenting results that are compared with simulation results, authors should state which models were turned on in the simulations.

b) When presenting results that are compared with simulation results, authors should include a table that identifies the simulation parameters and the analytical model parameters (physical as well as fitting) used to generate the model traces. If the simulation parameters differ from the corresponding analytical physical parameters, authors should explain why.

c) When presenting results that are compared with simulation results, authors should only show relevant comparison plots with correct models turned on. For example if the compact model considers field-dependent mobility when reporting transport properties, then the corresponding TCAD plots should not be reported using constant mobility.

d) When reporting subthreshold voltages extracted from simulations, authors should state the method of extraction and if by constant current method they should state the current cut-off value used.

e) Authors should actually read and understand the references they cite. Specifically, cited references should actually substantiate the claims made by the author.
It is our passion to continuously improve the quality of the articles we publish. Our hope is that by describing its facets we can quicken the march.

Doug Verret
Electron Devices, IEEE Transactions on
Houston, TX

[1] D. Verret; "Touchstones of a Quality Compact Model" Electron Devices, IEEE Transactions on; Nov. 2009; Vo. 56, No. 11; pp: 2374-2375

Some humor

Original source: phdcomics (which is a page I strongly recommend!)

I wonder what are the figures for "Compact Model", "Physical Model", "Analytical model", etc...

Nov 17, 2009


Sixth Workshop of the Thematic Network on Silicon on Insulator technology, devices and circuits
Grenoble, France, 25-27 January, 2010
  • Keynote Talks
    • SOI- the next five years: The critical role that SOI will play in the semiconductor ecosystem and how it will happen – H. Mendez (SOI Consortium)
    • Germanium Integration on Silicon for High Performance FETs and Optical Interconnects – K. Saraswat (Stanford University)
  • Training Course
    • 3D integration – N. Sillon (CEA-LETI)
    • Electrical characterisation of SOI nanodevices – G. Ghibaudo (IMEP)
    • Piezoelectrical technology on SOI (RF Filter) – S. Ballandras (CNRS)
    • III-V nanoelectronic on insulator – S. Bollaert (CNRS)
    • SOI technologies and circuits – J. Hoentschel (Global Foundries)

Nov 15, 2009

Call for Papers: ICGCS 2010

Global warming, climate change, and sustainability have profound impacts on our lives. The grand challenge faced by circuits and systems communities is to design green electronic devices and systems that consume less energy, thus lead to the reduction of global CO2 emission. The annual International Conference on Green Circuits and System (ICGCS) is our response to this grand challenge. ICGCS aims to address issues in climate change and limited suppliers and become a major international forum for researchers and engineers to exchange their latest findings in technologies related to green circuits and systems. ICGCS is a meeting place for scholars, scientists, educators, students, engineers, entrepreneurs, and managers from different disciplinarians to foster collaborations and to solve complex read world problems. It covers a wide range of topics including, but not limited to, the followings:
  • Green Transistors and Devices
  • Low Power Low Voltage Techniques for Analog, Mixed-Signal, Digital Circuits
  • Sub-threshold Circuit Design
  • Energy Efficient Analog Signal Processing Techniques
  • Computationally Efficient Digital Signal Processing Techniques
  • Signal Processing for Communications
  • Visual Signal Processing Techniques and Multimedia Systems
  • Optimization Techniques
  • Self-Powered Circuits and Systems
  • Adaptive and Reconfigurable Circuits and Systems
  • Scalable and Power Aware Systems
  • Energy Harvesting
  • Energy and Power Management
  • Green Power Electronic Circuits and Systems
  • Renewable Energy
  • MEMS and Sensors for Energy Management
  • Environmental Sensing, Control and Protection
  • Circuits and Systems Technologies for Recycling and Pollution Control
  • Emerging Technologies for Green Circuits and Systems
The inaugural conference, ICGCS 2010, will be held in June 2010 in Shanghai, the city hosting World Expo 2010. The participants not only have the opportunities to share their new findings in green circuits and systems but also to witness latest development as showcased in World Expo 2010.

The deadline for submission of Papers is on February 22, 2010. For more details, please visit: We welcome you to contribute your work(s) to ICGCS2010 and hope to see you in Shanghai.

Contact: Yong Lian and Tor S. Lande; ICGCS 2010 Technical Program Chairs

Nov 13, 2009

Open, One year post doc position for development of HV transistor SPICE models

  • PhD or Master/Dipl. Ing. in Physics or Electronic Engineering
  • Experience in SPICE modeling (e.g. BSIM, EKV, PSP, HiSIM)
Place of Employment:
  • Unterpremstaetten/Graz , Austria
Job Description / tasks responsibilities:
  • Development of HV transistor SPICE models
  • Parameter extraction and measurements for SPICE models
  • Project management within the COMON project
  • Writing documents and deliverables
Contact: Dipl. Ing. Ehrenfried Seebacher
Senior Manager Process and Device Characterization - Modeling
austriamicrosystems AG
Operations - Process Developments
Schloss Premstaetten
8141, Unterpremstaetten, Austria
Tel: +43 3136 500 5487
Fax: +43 3136 500 5755

A CAD-compatible closed form approximation for the inversion charge areal density in double-gate MOSFETs

Venkatnarayan Hariharan, Juzer Vasi, V. Ramgopal Rao; Solid-State Electronics, Volume 53, Issue 2, February 2009, Pages 218-224

Abstract: In developing the drain current model of a symmetrically driven, undoped (or lightly doped) symmetric double-gate MOSFET (SDGFET), one encounters a transcendental equation relating the value of an intermediate variable β (which is related to the inversion charge areal density and also surface-potential) to the gate and drain voltages; as a result, it doesn’t have a closed form solution. From a compact modeling perspective, it is desirable to have closed form expressions in order to implement them in a circuit simulator. In this paper, we present an accurate closed form approximation for the inversion charge areal density, based on the Lambert-W function. We benchmark our approximation against other existing approximations and show that our approximation is computationally the most efficient and numerically the most robust, at a reduced but acceptable accuracy. Hence, it is suitable for use in implementing inversion charge based compact models.

DOI: 10.1016/j.sse.2008.11.006

Symmetric linearization method for double-gate and surrounding-gate MOSFET models

Gajanan Dessai, Aritra Dey, Gennady Gildenblat, Geert D.J. Smit; Solid-State Electronics, Volume 53, Issue 5, May 2009, Pages 548-556

Abstract: Symmetric linearization method is developed in a form free of the charge-sheet approximation present in its original formulation for bulk MOSFET. This leads to a core compact model of certain multiple-gate transistors that has the form almost identical to that used in a standard PSP MOSFET model. The accuracy of the proposed technique is verified by comparison with the exact results. The new core is compatible with the previous version of the double gate MOSFET model that has been found in agreement with the experimental data including short-channel effects and frequency response.

DOI: 10.1016/j.sse.2009.01.020

Nov 11, 2009

CEA-LITEN selects InfiniScale for Organic Electronic devices modeling

InfiniScale today announced that CEA-LITEN has selected InfiniScale’s TechModeler for its organic electronic devices modeling needs.
You can see by their public declarations that they are quite happy:

“InfiniScale’s modeling tool allowed us to shrink our development cycle by a large factor” commented Isabelle Chartier Organic Electroniv program manager at CEA-LITEN- “CEA-Liten is deeply involved in printing Organic Electronic devices and circuits, we target to demonstrate, before the end of 2009, a first all printed organic CMOS circuit. Modeling our devices versus design and technology parameters is critical for our technological developments. Therefore, fast prototyping and fast development cycles achieved with Infiniscale is key to stay on top of the Emerging and promising Organic Electronic market”

“We are pleased by CEA-LITEN commitment “said Dr Firas MOHAMED, CEO of Infiniscale “InfiniScale has taken position on this new industry where there is a need to grow at a fastest possible pace. After a close collaboration through an important R&D project on organic electronic (Printronics a Minalogic cluster project), CEA-LITEN decided to adopt our technology for its advanced organic devices modeling.

We are very pleased to see that our modeling technology, which is already recognized by major semi-conductor players, kept its promise for the organic ambitious industry”.

You can read the full press release here.

Nov 5, 2009

An interesting paper in the Intl. Jornal of Numercal Modelling (vol 22(6))

This is not exactly compact modelling, but it's a nice thing to see:

SPICE-aided modelling of dc characteristics of power bipolar transistors with self-heating taken into account

Janusz Zarbski, Krzysztof Górecki
Department of Marine Electronics, Gdynia Maritime University, Morska 83, 81-225 Gdynia, Poland

This paper deals with the problem of calculations of the dc characteristics of power bipolar transistors (BJTs) with self-heating taken into account. The electrothermal model of the considered devices dedicated for PSPICE is presented. The correctness of the model was verified experimentally in all ranges of the BJT operation. Two transistors - BD285 and 2N3055 - were arbitrarily selected for investigation. A good agreement between the measured and calculated characteristics of these transistors was observed.

You can access the online version here.

55th IEEE IEDM conference

The 55th annual IEEE IEDM conference will be held at the Hilton Baltimore on December 7-9, 2009 preceded by a day of Short Courses on Sunday, Dec. 6. The world¹s best scientists and engineers in the field of electronics will showcase their work in a program of papers, panels, special sessions, Short Courses and other events that will spotlight more leading work in more areas of the field than any other conference.

The advance registration deadline is November 16 and the deadline for hotel reservations is November 6. For registration and other information, visit the IEDM 2009 home page at

As a novelty, IEDM can be followed in twitter and facebook... which I think is a good move.

Nov 3, 2009


6th International Conference
Perspective Technologies and Methods in MEMS Design
Polyana, UKRAINE, 20 - 23 April 2010

Organized by:
  • Lviv Polytechnic National University, CAD Department, Ukraine
  • Warsaw University of Technology, Institute of Telecommunication, Poland
  • IEEE MTT/ED/AP/CPMT/SSC West Ukraine Chapter
Supported by Lviv Regional State Administration

Topics include, but not limited to:
  • Analysis, modelling, research and design methods of microsensors and microactuators
  • Software systems, models, algorithms, methods and strategies of embedded systems design
  • Field issues in embedded systems modelling and design
  • Issues of testing, verification, reliability and optimization in embedded systems modelling and design
  • Sensors and actuators systems, nanotechnology
  • Applications for electron device design
  • Information Technology. Engineering Application of Informatics. Engineering Education
Important Dates:
  • February 15, 2010
    • Deadline for abstract submissions (at least 400 words in plain text file, in English)
  • March 15, 2010
    • Notification of abstract acceptance
  • April 02, 2010
    • Deadline for final Camera-Ready Papers submissions (in English)

A paper in Thin Solid Films

I've found a paper that may interest you:

The quantum size effects on the surface potential of nano-crystalline silicon thin film transistors

Ling-Feng Mao

(Available online 29 October 2009)


The impact of the grain size of nc-Si (nano-crystalline silicon) on the surface potential of doped nc-Si TFTs (thin film transistors) is discussed. Quantum size effects cause the change in both band-gap and dielectric constant of nc-Si. Numerical calculation of the surface potential in nc-Si TFTs shows that the diameter of nc-Si has a larger effect on the surface potential of nc-Si TFTs. The results demonstrate that, for medium size (7 ~ 50 nm), the change in the band-gap of nc-Si should be considered, whereas, for small size (< 7 nm), the change in the dielectric constant of nc-Si should be considered. A simplified surface potential equation for nc-Si TFTs under strong inversion condition is proposed, and shows good agreement with the original equation via numerical calculation.

Have fun!

Oct 22, 2009

From EDN: sales are up!

SEMI: Bookings rise y/y for first time since May 2007, industry continues to improve

North America-based manufacturers of semiconductor equipment posted $732.8 million in orders last month and an improved book-to-bill ratio of 1.17, according to SEMI's September book-to-bill report.

By Suzanne Deffree, Managing Editor, News -- Electronic News, 10/21/2009

The semiconductor industry's overall situation continued to improve in September, according to the latest data from SEMI.

North America-based manufacturers of semiconductor equipment posted $732.8 million in orders in September and a book-to-bill ratio of 1.17, according to SEMI's September book-to-bill report.

A book-to-bill of 1.17 means that $117 worth of orders were received for every $100 of product billed for the month. The August book-to-bill ratio was 1.06.

The September bookings figure is 19.3% greater than the final August level of $614.5 million and 12.8% greater than the $649.9 million in orders posted in September 2008.

Meanwhile, billings in September were $624.6 million, a 7.7% improvement on the August level of $580 million but nearly 33% less than the August 2008 billings level of $927.3 million.

And you can access the full article at the original website.

Oct 19, 2009

Correction on ISFE'2010

I apologize, but I made a mistake on the entry about ISFE'2010. The correct dates when the Symposium will be held are April 12-14 2010. Please take this new dates into account!

Oct 15, 2009

[mos-ak] MOS-AK/GSA Workshop in Baltimore: 1st announcement

* Dec.9, 2009
* collocated with
o IEDM Conference (Dec.6-9 <
o CMC Meeting (Dec.10-11<
* Johns Hopkins University at Homewood Campus in the Computational
Sciences and Engineering
o Building (CSEB) Room CSEB 17
o free on-line registration
o General visitor information for JHU
o Map of the campus
* about 50+ (similar to
* 6-8 invited noted speakers presenting academia and industry
o plus a poster session
* panel discussion at the end of the workshop
o Compact models QA validation: Still a challenge?
* HiTech forum to discuss the frontiers of the compact/spice
* MOS-AK/GSA Meetings are organized with aims to strengthen a
network and discussion forum among experts in the field, enhance open
platform for information exchange related to compact/Spice modeling,
bring people in the compact modeling field together, as well as obtain
feedback from technology developers, circuit designers, and CAD tool
vendors. The topics cover all important aspects of compact model
development, implementation, deployment and standardization within the
main theme - frontiers of the compact modeling for nm-scale CMOS/SOI
circuit simulation.
* The specific workshop goal will be to classify the most
important directions for the future development of the compact models
and to clearly identify areas that need further research. This
workshop is designed for device process engineers (CMOS, SOI, BiCMOS,
SiGe) who are interested in device modeling; ICs designers (RF/Analog/
Mixed-Signal/SoC) and those starting in that area as well as device
characterization, modeling and parameter extraction engineers. The
content will be beneficial for anyone who needs to learn what is
really behind the IC simulation in modern device models.

* Topics (open list):
o electronic abstracts submission
* Advanced MOST compact models for the bulk/SOI and compound
* Alternative models for analog/RF and HV applications
* High level behavioral languages (Verilog/VHDL) for compact
models standardization
* CAD tools for model implementation
* Parameter extraction, model QA and lib generation and validation
* GNU/open source software support

* I. Angelov: "Fundamentals of FET Device Modelling for GaN, SiC,
GaAs and CMOS"
* A.G. Andreou: TBD
* G. Coram: "Verilog-A standardization and model validation"
* B. Iniguez: "COMON: EU compact modeling project"
* J. J. Liou: TBD
* M. Mierzwinski: "Practical Considerations for Developing,
Debugging, and Releasing Verilog-A Models"
* C.G. Montoro: "CMOS Analog Design Using All-Region MOSFET
* M. Reece: TBD
* J. Victory: TBD

* The MOS-AK presentation will be available on-line after the
* Selected papers will be recommended for further publications
o Solid-State Electronics
o International Journal of Numerical Modeling

* Andreas G. Andreou, JHU; Technical Program Chair
* Pekka Ojala, Exar; MOS-AK/GSA WG North America Chair
* Gilson I Wirth; UFRGS; MOS-AK/GSA WG South America Chair
* Ehrenfried Seebacher, austriamicrosystems AG; MOS-AK/GSA WG
Europe Chair
* Al Kordesch, Silterra Malaysia; MOS-AK/GSA WG Asia/Pacific Chair
* Chelsea Boone GSA; Senior Research Analyst
* Darryl Leavitt, GSA; Director of Events
* Wladek Grabinski, GMC Suisse; MOS-AK/GSA Workshop Manager
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Oct 1, 2009

[mos-ak] MOS-AK/GSA Athens meeting on-line publications

MOS-AK/GSA Athens meeting on-line publications are available:

I would like to thank all MOS-AK contributors, speakers and
presenters, for sharing their compact modeling competence, R&D
experience and delivering valuable MOS-AK presentations. I am sure,
that our modeling event in Athens was beneficial to all MOS-AK
Workshop attendees and the ESSDERC/ESSCIRC conference participants. My
extra "Thank You" goes to our special guest Larry Nagel, who has
kindly accepted our invitation to present vital live of the SPICE.

Organization of our modeling event would not be possible with our
generous sponsor: Accelicon, Helic, Tanner and Toshiba. I also would
like to personally acknowledge local ESSDERC/ESSCIRC organizers, in
particular Prof. Bucher for his dedication, commitment and providing
smooth logistics.

Selected MOS-AK presentations will be recommended for further
publication thru our Technical MOS-AK/GSA Program Promoters and
individual authors will be informed by a separate email.

I hope, we would have a next chance to meet all of you and your
academic and industrial partners at future MOS-AK/GSA modeling

-- with best regards - WG for the MOS-AK/GSA Group;
* Luzern: Oct. 18-20,
* Baltimre: Dec'09,
* Rome: April 8-9
* Wroclaw: June 24-26
* Seville: Sept. 18
GSA and MOS-AK Merge Efforts to Form the GSA Modeling Working Group

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Sep 29, 2009

new IEEE Senior Members (sep-2009)

Congratulations to the new Senior members of the IEEE EDS (September 2009):

Ahmadi, Vahid; Buehler, M; Feng, Lucia; Goel, Niti; Hales, Rex; Hirschman, Karl; Liu, Ming; Pratt, T; Selmi, Luca; Srinivasan, Purushothaman; Xue, Jie; Zhang, Zhaochuan

Sep 28, 2009

Second International Symposium on Flexible Electronics (ISFE)

The Second International Symposium on Flexible Electronics (ISFE) will be held in from April 12-14 2010 in Palma de Mallorca (Illes Balears, Spain). I will be the Chairman of this Symposium, together with Past Chair, Dr. Benjamin Iñiguez and Prof. Michael Shur. This Symposium will provide an opportunity to present and discuss recent advances in all topics related to flexible electronics, from the material to the circuit and system levels. The enormous increase of the applications of Flexible Electronics makes it necessary to create such a conference. The scientific program consists of invited and contributed presentations as well as one poster session.

Papers are solicited on the following topics (but without excluding others):
Materials for Flexible Electronics, Processing for Flexible Electronics, Device technologies, Physics and Characterization of TFTs on flexible substrates, Amorphous and polycristalline TFT, Transparent TFT, Organic and polymer TFT, OLED physics and characterization, Numerical and compact modeling of TFTs and OLEDs, TFT circuits on flexible substrates, Flexible AM-LCDs, Flexible AM-OLEDs, Flexible PVDs, Flexible large-area sensors and actuators...

The deadline for abstract submission will be November 15, 2009, but abstracts for posters are accepted until December 15, 2009.

ISFE is organized by the Engineering Conferences International Foundation, together with the Universitat de les Illes Balears (the university of Mallorca, to which the Chairman, that is, myself, belongs).

For those of you that do not know them, the Balearic Islands are located 200 km east from the coast of Spain, in the Mediterranean Sea. This privileged location, with flight time below than 30 minutes from Barcelona, or 2 hours from Berlin or London, make them a preferred touristic destination. Moreover, they enjoy a very nice climate, with temperatures that rarely go down 10ºC in winter, and are around 20-25º in springtime.

Mallorca, the biggest of the Balearic Islands, is an island where you can find anything nearby. You can go climbing in the Serra de Tramuntana, which are a set of mountains 100 km long, dominating the north-western part of the island, or you can go to the any of the fantastic beaches. You can choose among touristic destinations like Platja de Palma or S'Arenal, close to the airport, or you can go 30 km further and find yourself in near virgin beaches in Sa Rapita or Es Trenc. Swimming season in Balearic Islands starts usually around May 1st, and goes on up to the end of September or even October, so there is no need to hurry.

Palma, the capital of Balearic Islands, is a cultural city, an easily accessible city, where everything is close by. Beautifully arranged as a fan towards the sea, the city is marked by the cultures that have lived on the island along its history. Palma invites you to discover its buildings and the monuments that portray the evolution of aesthetic trends during the centuries, that are visible in more than 700 streets in its historic downtown. This is where you will find the footprint of all those civilizations that have contributed to its building. A city that invites you to display creativity, as so many artists have done in the past, inspired by its warm and magic light.

Transportation is another of the strong points of the Balearic Islands. Palma airport (Son Sant Joan) is one of the biggest airports in Europe. It is very well connected to all major cities in Europe through both regular and charter flights, and many low-cost companies also fly to and from Palma.

I truly encourage researchers on flexible electronics to submit abstracts to ISFE, and have good chances to get to know the most recent developments in the field, to make useful networking and also to enyoy some days in the beautiful city of Palma!

Sep 23, 2009

BBC News: Meeting the man behind Moore's Law

Chip future... But, Dr Moore says, the industry can only go on shrinking transistors for so long. Eventually, the features will become so small that the atomic structure of the materials will be a limitation, possibly spelling the end of Moore's Law.

So what does he think will happen in the next 40 years?

"I'm through with making predictions," Moore chuckles. "Get it right once and quit."


Sep 22, 2009

Technology Roadmap for 22nm and Beyond

[1] Iwai, H.; Technology roadmap for 22nm and beyond; IEDST '09; 1-2 June 2009

CMC Timeline for Multigate Compact Model Standardization

The CMC Subcommittee on Multigate Models has published timeline for multigate compact model standardization assuming resolution by 2Q11. Proposal: model freeze date would be after model evaluation
  • Would be justified by concurrent model and technology development
  • Model developers would have the ability to model changes during mod elevaluation
  • Must be done with subcommittee agreement (reasonableness check)
  • No additional time allowed in model evaluation
  • Code frozen at end of model evaluation

Sep 14, 2009

7th IWCM Taipei, Taiwan

Call for Papers:
7th International Workshop on Compact Modeling January 18 (Mon), 2010 Taipei International Convention Center, Taipei, Taiwan

The workshop provides an opportunity for the discussion and the presentation of advances in modeling and simulation of integrated circuits.

  • Compact modeling for all kinds of devices
  • Parameter extraction methodology and strategy
  • Circuit simulation techniques
Abstract Submission:
Authors should submit a camera-ready abstract with 2 to 10 pages including figures for inclusion in the Workshop Proceedings, and send the electronic file in PDF or MS-Word format to Paper templates in Tex and Word formats are downloadable from the ASP-DAC 2010 site. Deadline for the submission is November 30th, 2009.


TAL 2009

XII Scientific Conference and II School: "Optical Fibres and Their Applications" TAL 2009 October 14 - 17, Lublin and Krasnobród. The aim of the conference is enabling a direct contact and discussion between the teams dealing with:
  • Development of technology and fabrication of optical fibres, cables, planar waveguides and elements of integrated optics and micro-optics
  • Elements of optical fibres technique like couplers, connectors, optical fibres amplifiers, optical and optoelectronic devices for connecting optical fibres with light sources and detectors, multiplexers
  • Optical fibres applications especially those requiring a close cooperation with the optical fibres and optical cables, elements of optical fibres technique and optoelectronics manufactures
  • Education in the photonics in the universities and high schools

MOS-AK/GSA Workshop in Athens with special guest Larry Nagel

--- MOS-AK/GSA Workshop in Athens with special guest Larry Nagel
--- Friday, Sept. 18 2009 at Divani Caravel Hotel
--- (at the ESSDERC/ESSCIR Conference)

--- The Final MOS-AK/GSA Workshop program is available on-line:

--- Meeting location:
DIVANI CARAVEL HOTEL, 2 Meg. Alexandrou Aven. 161 21, Athens, Greece
For driving directions please visit: and

--- No registration fee thanks to our sponsors Accelicon, Helic, Tanner and Toshiba.
We would suggest to register on-line
to help our local organizers with local logistic and other arrangements.

Sep 8, 2009

Lectures on Numerical Linear Algebra in Computational Science and Engineering

September 12, 2009; ETH Zurich, Switzerland

Aims and scope: The lectures will discuss the importance and impact of Numerical Linear Algebra in CSE. Its usage in various areas of CSE will be exemplified. The event will also celebrate the retirement of Martin Gutknecht from ETH Zurich.


Related meetings

Sep 2, 2009

Spice Modeling Engineer

And another job offer....

GF-- SMTS Spice Modeling Engineer - Semiconductor Jobs
Posted Aug 07
Confidential, Sunnyvale, CA
Job Description:
As a member of SPICE modeling team, this position will drive active/passive model development and QA, assuring high quality SPICE model delivery to external design customers. The responsibilities include (but not restricted to) development of SPICE modeling infrastructure and methodologies; device characterization (DC/AC/Transient/RF); and test structure development.

Required Skills/Experience:
Must have MS/PhD in EE, Solid State Physics, or equivalent with 0-10 yrs experience.

Must also have in-depth device physics, RF knowledge, and good programming skills. Prior hands-on experiences on SPICE model extraction (Scalable Inductor, Varactor, Resistor, Capacitor, BJT, Diodes), RF measurement, modeling, and HFSS simulation are a big plus.

MS/PhD in EE, Solid State Physics, or equivalent with 0-10 yrs experience.

Post Doctoral Researcher - Device Physics

I post here another job offer...

Post Doctoral Researcher - Device Physics

Job ID
Job type
Full-time Complementary
Work country
Work city
Yorktown Heights
Job area
No travel
Job category
Business unit
Res Sci&Tech
Job role
Research Scientist

Job role skillset

Job description
The position is for a post-doctoral candidate to work on numerical model development for carrier transport in heterostructure tunneling transistors. Specifically the principle responsibilties will be to develop a computer program that self-consistently calculates band-to-band tunneling in a eterojunction tunneling diode, compare the calcuation results with xperiments, and to adjust the physical assumptions in the model to match experiment.

The responsibilities will also be to impelment and develop a 2D version of this code for inclusion into IBM internal device simulation software. Required skills for the position will be a detailed knowledge of semiconductor device physics and carrier transport in semiconductors, numerical modeling techniques, and computer programming. The candidate must be self-motivated and work well in a goal-oriented, team environment.

  • Basic knowledge in computer code development using a high-level programming language such as Fortran
  • Basic knowledge in numerical modeling of solid-state electronic systems
  • Basic knowledge in semiconductor device physics, with an emphasis on band structure and carrier transport
  • English: Intermediate

  • Doctorate Degree
  • At least 2 years experience in computer code development using a high-level programming language such as Fortran
  • At least 2 years experience in numerical modeling of solid-state electronic systems
  • At least 1 year experience in semiconductor device physics, with an emphasis on band structure and carrier transport
  • At least 1 year experience in designing experiments, and interpretting experimental data

Device Simulation Engineer - Solar IC Resources Ltd

I post here a job offer from:

  • Location: Surrey
  • Sector: Other
  • Job Hours: Full-Time
  • Job Position: Permanent
  • Job Role: Device Engineer
  • Company: IC Resources Ltd
  • Salary: Top-notch salary + bens
  • Job reference: J010691
  • Posted Date: 28 August 2009 13:01:32
They are currently searching for a Device Simulation Engineer (Solar) with the following key skills: Semiconductor, solar, solar cell, FORTRAN, Silvaco, modelling, device, III-V, simulation, manufacturing, jobs

The client is currently searching for a Device Simulation Engineer to be responsible for the modelling and simulation of solar cell devices. The role will involve working with FORTRAN code and upgrading the device modelling software. Performing day-to-day simulations will be required as well as looking into future requirements.

The successful candidate will have the following qualifications;

·Strong semiconductor device modelling experience (III-V)
·Modelling package knowledge (Silvaco, Synopsys, FORTRAN)
·Previous solar cell experience beneficial
·Excellent communication and leadership skills
·BSc in Physics, Electronics, Physics, Materials or equivalent

CMOS Device Modeling Engineer Job in IBM

Job description
IBM is seeking a CMOS Device Modeling Engineer to develop and maintain state of-the-art compact models. Included in this role are: DC and AC measurements, data integrity checking, model extraction, statistical model generation, corner model generation, model conversions, model to hardware checking, and integration in Design System model checking. You will be working on leading edge bulk and SOI technologies for digital, analog and CMOS RF applications interfacing with IBM and external circuit designers to define model requirements & providing leadership in the modeling area.
  • Doctorate Degree in Engineering
  • At least 2 years experience in Apply Knowledge of Semiconductor Device Physics
  • Basic knowledge in Apply Knowledge of Compact Model Generation
  • Readiness to travel up to 10%; travelling 1 day a week
  • English: Fluent

Aug 31, 2009

2009 IEEE International SOI Conference

Oct. 5 - 8 October, 2009, Foster City, California

Ever increasing demand and advances in SOI and related technologies make it essential to meet to discuss new gains and accomplishments, as well as to consider new developments introduced in original papers presented at the conference.

  • SOI device physics and modeling
  • Manufacturability and process integration of soi devices
  • Low-power SOI technology and circuit design infrastructure
  • SOI circuit applications (high-performance mpu, sram, asic, high-voltage, rf, analog, mixed mode, etc.)
  • SOI double & multiple gate/vertical channel structures; other novel SOI structures
  • New SOI structures, circuits, and applications (3d integration, displays, microactuators, novel memories, optics, etc.)
  • SOI reliability issues (hot-carrier effects, radiation effects, high-temperature effects, etc.)
  • SOI material science/modification, material characterization, manufacture, and substrate engineering.
  • SOI sensors, MEMS and RFIDs technology and applications

Aug 25, 2009


The International Conference Micro- and Nano-Electronics – 2009 (ICMNE-2009) including extended Session “Quantum Informatics” (QI-2009) will be held in October 5-9, 2009 at the holiday hotel “Lipki”, Zvenigorod, Moscow region, Russia. It will continue the series of All-Russian Conferences MNE-1999, MNE-2001, QI-2002, and International Conferences ICMNE-2003, QI-2004, ICMNE-2005, QI-2005. ICMNE-2007, QI-2007. Conference ICMNE is biannual event covering majority of area of micro- and nano-electronic technologies, physics and devices. ICMNE-2009 is focused on recent progress in that area. The Conference will include the exhibition on equipment for micro- and nano-electronics. Conference's scope:
  • Micro-, nano-electronic materials and films
  • Micro- and nano-electronic technologies and equipment
  • Metrology
  • Physics and technologies of micro- and nano-devices
  • Simulation and modeling
  • Quantum informatics

Aug 19, 2009

IRPS 2010

The 2010 IEEE International Reliability Physics Symposium (IRPS) will be held in Anaheim, California, Canada, on May 2-6 2010. The venue will be Hyatt Regency Orange County.
For over 40 years, IRPS has been the premier conference for engineers and scientists to present new and original work in the area of microelectronic device reliability. IRPS is now co-sponsored by the IEEE Reliability Society and the IEEE Electron Devices Society. This co-sponsored event has drawn participants from the United States, Europe, Asia and all other parts of the world. IRPS'10 promotes the reliability and performance of integrated circuits and microelectronic assemblies through an improved understanding of failure mechanisms in the user’s environment, while demonstrating the latest state-of-the-art developments in electronic reliability.
The focus of the symposium is the 3-day plenary/parallel sessions featuring original work that identifies new microelectronic failure or degradation mechanisms, improves understanding of known failure mechanisms, demonstrates new or innovative analytical techniques, or demonstrates ways to build-in reliability. Specific areas to be addressed during the 2010 IRPS are reliability concerns associated with silicon (integrated circuits, discrete devices, MEMS, TFTs), Compound Semiconductor & Optoelectronics (GaAs, GaN, LEDs, displays, photovoltaics), and emerging technologies including organic electronics and nanotechnology.The deadline for abstract submission is October 2 2009.
In the Call for Papers, it is said that IRPS can accept papers which "identify new or improve our understanding of the physics of failure and modeling of mechanisms in electronic and optoelectronic devices, materials, and systems".Therefore, IRPS is a very attractive conference to present results on modeling of failure mechanisms.

Global Plastics Electronics Conference 2009

The 5th Global Plastic Electronics Conference and Exhibition will be held in Dresden, Germany, on October 27-29 2009. The venue will be the Maritim Hotel and Hotel Centre, Dresden.

This year's event will run for three days. The agenda is the following:
Day 1 will see forums run in paralell covering Integrated Smart Systems and Smart Fabrics and Intelligent Textiles. Days 2 and 3 both start with the Plenary session in the morning, followed by 5 paralell symposia in the afternoon.

The Global Plastic Electronics Conference and Exhibition will be a very appropriate place to learn about the recent advances on plastic electronics, and also to do networking. The plenary speakers are leading authorities in the field, as well as some of the presenters.

The Call for Posters is still open! It is a good oportunity to present a scientific poster and have a chance to meet the leaders in plastic electronics.Besides, more than 30 companies will participate in the Exhibition. As said in the brochure, Science and Industry will meet in this conference.


The 2010 IEEE RFIC (Radio Frequency Integrated Circuits) Symposium will be held in Anaheim, California, on May23-25-9 in conjunction with the IEEE MTT-S International Microwave Symposium (IMS), as part of the Microwave Week 2010.The IEEE RFIC Symposium is one of the most important IEEE conferences dedicated to the latest innovations in RF and microwave integrated circuits.The technical areas of RFIC 2010 include RFIC design, RFIC circuits, wide-band system IC's, RFIC device technologies, RF testing... And I wish to hightlight that one of the topics explicitly mentioned in the Call for Papers is "Modeling and CAD: RFIC Modeling, Characterization of Active and Passive Devices".Certainly, RFIC'10, as well as IEEE MTT-S IMS, will allow an easy interaction between high-frequency compact model developers and their potential users.The deadline for paper submission is January 5 2009.


The IEEE MTT-S International Microwave Symposium 2010 (IMS 2010) will be held in Anaheim, California from May 23 to 28 2010. It will take place at the Anaheim Convention Center.

IMS is the largest conference in the field of RF and microwave theory and techniques.IMS'10 will include workshops, short courses, panels and special sessionsIn such a large conference, there are many parallel sessions. The scope of IMS is large, and papers on compact modeling of semiconductor devices in the RF and microwave regime can be presented at IMS. In fact, IMS is a very adequate forum for that, because of the presence of the potential users of the device models (designers of RF and microwave circuits). IMS will be part of the Microwave Week 2009, which will also include a microwave exhibition, the RFIC Symposium and the ARFTG Conference.The deadline for paper submission is November 30 2009.Last but not least, IMS'10 includes a very interesting social programme. And Disneyland is in Anaheim!


The 2009 Workshop on Frontiers in Electronics (WOFE) will be held in a very beautiful place: Rincon of the Seas Grand Caribbean Hotel, Rincón (Puerto Rico) from December 13 to 16 2009. WOFE is being held every two years.

It is a very special workshop devoted to bring together researchers who work at the frontiers of electronic devices and circuits. Therefore, it facilitates the interaction between researchers from different areas such as microwave power circuits, optoelectronics, emerging nanodevices, bioelectronics, nanotubes, teraherz and infrared electronics and photonics, TFTs and giant area electronics, nanoMEMs, or wide band gap technology, provided their targets are at the frontiers of present electronics.

Papers on modelling have also been usually accepted for WOFE, if they address advanced devices, or brand new modeling techniques.

We have to remark that the programme committee encourages to submit papers presenting discussions of controversial issues, rebuttals of theories, provocative or alternative views, and visionary outlooks.

The Chair of WOFE is Professor Michael S Shur, from the Rensselaer Polytechnic Institute (RPI), Troy, NY (USA). Very prestigeous researchers will be invited for plenary talks.The deadline for abstract submission is October 01 2009.

No doubt it should be very pleasant to spend several days in Puerto Rico enjoying nice weather in December. Every day the sessions end early in the afternoon, so there is plenty of time to enjoy the beach. As the WOFE schedule say, the afternoon is the time for "break and networking", what means beach, or networking on the beach. Furthermore, there is a wonderful social programme, which includes one very interesting excursion.I recommend researchers to go to WOFE. It is a very adequate event for networking in a very beautiful and relaxing place.

Aug 17, 2009


The 22nd IEEE International Symposium on Power Semiconductor Devices and ICs will take place in Hiroshima (Japan) on June 6-10 2010. The deadline for abstract submission is October 30 2009 .ISPSD is the main international conference on the areas of power semiconductor devices, power integrated circuits, their hybrid technologies, and applications.Topics include: processes, materials, CAD/Simulation, devices, power ICs, packaging and applications.For researchers interested in compact modeling of power semiconductor devices, ISPSD is a top event to present and get to know the last results in this field. "Device & circuit simulation" is explicitly mentioned as one of the subtopic in the "CAD/Simulation" topic. Compact modeling fits very well this subject. And of course, there is a subtopic of "Modeling" in the "Device" topic.

I imagine that the developers of the well known HiSIM models, who work in the Hiroshima University, will be around, so this conference can be a bussiness oportunity for compact model developers and users, including circuit designers.

Aug 15, 2009


The 2010 IEEE International Symposium of Circuits and Systems (ISCAS 2010) will be held in Paris (France), on May 30-June 3 2010. It will take place at the Convention Center at Disney’s Hotel New York, in Paris. It will be supported by the Institut Supérieur d’Electronique de Paris.

ISCAS is the largest conference in the area of Circuits and Systems. It is sponsored by the IEEE Circuits and Systems Society. Prestigeous speakers in this field are always invited. ISCAS 2010 will focus on on circuits and systems employing nanodevices (both extremely scaled CMOS and non-CMOS devices) and circuit fabrics (mixture of standard CMOS and evolving nano-structure elements) and their implementation cost, switching speed, energy efficiency, and reliability.

The scope of ISCAS 2010 includes all topics related to integrated circuits and systems. Papers on compact modeling for circuit design are considered to address some of the topic of the call. In fact, every year a number of interesting papers on compact modeling are presented at ISCAS.

The deadline for paper submission is October 9 2010.

It is important to mention that in ISCAS posters are very well considered, as important as oral presentations. Many authors choose poster as their presentation format. Besides, a student paper contest will be held at ISCAS 2010 and sponsored by the Circuits and Systems Society.

On the other hand, a "a very entertaining social program is planned. Special tours to tourist attractions will be available to the Symposium attendees and their guests." It Sounds promising, anyway.

ICMTS 2010

The IEEE 2010 ICMTS (International Conference Microelectronic Test Structures) has launched the final call for papers (deadline: Sept. 18, 2009). Authors are asked to submit a two or three page extended abstract in PDF file format (font-embedded) including a 500- to 1500-word summary, major figures, and data for review. ICMTS'10 will be held between March 22 – 25, 2010, in Hiroshima (Japan), and there is a suggested topic including "Device and Circuit Modeling, Parameter Extraction RF device modeling".

I imagine that the developers of the well known HiSIM models, who work in the Hiroshima University, will be around, so this conference can be a bussiness oportunity for compact model developers and users, including circuit designers.

The conference will be preceded by a one-day Tutorial Short Course on Microelectronic Test Structures on March 22, 2010. There will be an equipment exhibition relating to test structure measurements. A Best Paper award will be presented by the Technical Program Committee.

ICMTS has always an excellent social programme. There is always a very interesting excursion tour, and a wonderful gala dinner. And the Hiroshima cuisine is delicious...

Aug 14, 2009

Compact Modeling Job Vacancy at TU Ilmenau, Germany

The RF & Nano Device group at TU Ilmenau is seeking a candidate for a position in the frame of a European Marie Curie Project.
The candidate will work on compact modeling of high-frequency transistors, in particular HEMTs (High Electron Mobility Transistor). During several months he or she will also work at a semiconductor foundry in the UK in the frame of a secondment agreement between the foundry and TU Ilmenau.
Contract details: Temporary contract to carry out a Ph D, starting date January 2010.
Application deadline: 31 October 2009.
Contact: PD Dr. Frank Schwierz, email:
Requirements: Candidates should be a Ph.D. student having already earned a Master or Dipl.-Ing. degree in electrical engineering, preferably in semiconductor electronics. Good skills in written and spoken English are mandatory.
Desirable is experience in the areas of semiconductor device physics and device modeling and simulation.

Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation: Deadline extended

The Second International Workshop on Compact Thin-Film Transistor (TFT) Modeling for Circuit Simulation will be held at the University College London (UCL) in London (UK) on September 25 2009.

This workshop is intended to provide a forum for discussions and current practices on compact TFT modeling. The workshop is sponsored by IEEE EDS Compact Modeling Technical Committee in collaboration with IEEE UCL-Cambridge University EDS/LEOS Chapter joint chapter that is in the process of formation. Topics include include:

• Physics of TFTs and operating principles
• Compact TFT device models for circuit simulation
• Model implementation and circuit analysis techniques
• Model parameter extraction techniques
• Applications of compact TFT models in emerging products
• Compact models for interconnects in active matrix flat panels

Prospective authors should submit a 500-word abstract to:



If their abstract is accepted, the authors will be invited to submit of a 4-page paper to be included in proceedings. The deadline is September 14, 2009.

This is the only workshop especifically devoted to the compact modeling of TFT!

Aug 4, 2009

Q2 semiconductor sales up 17%, industry is 'returning to normal seasonal growth patterns,' SIA reports

I copy here an article originally published in EDN:(I mean, finally good news!)

Focused supply chain management by both producers and customers helped to moderate the impact of the global economic recession on the industry, SIA reports.

By Suzanne Deffree, Managing Editor, News -- Electronic News, 8/3/2009

Although sales numbers were a mixed bag of results, the SIA (Semiconductor Industry Association) this morning reported on Q2, June, and first half revenue with palatable optimism for a semiconductor industry recovery.

Q2 recorded a sequential worldwide sales increase of 17% and a 20% year-over-year decline for the quarter. Q2 sales of $51.7 billion were capped off by month of June sales at $17.2 billion, an increase of 3.7% from May when sales were $16.6 billion, but 20% lower than the $21.6 billion reported for June 2008.

While June continued a month-over-month sales growth trend that began in March when sales inched up 3.3% on February's numbers, total 2009 first half sales of $95.9 billion were still 25% below the first six months of 2008, when sales were $127.5 billion, SIA data showed.

Also see:

Top 20 semiconductor companies saw 21% sales surge in Q2

Q2 revenue grew 16% or more, researchers say

“The fourth-consecutive monthly increase in sales is one indicator the industry is returning to normal seasonal growth patterns,” said SIA President George Scalise in a statement.

Scalise said focused supply chain management by both producers and customers helped to moderate the impact of the global economic recession on the industry. “Inventories have been closely managed, encouraging us to believe that the sequential increase in quarterly sales represents a gradual recovery of demand,” he said.

Scalise and the SIA aren't the only optimistic parties in the semiconductor industry. Several industry analysts and market research companies including Gartner and iSuppli have recently become more positive in their forecasts for key demand drivers.

“Consensus estimates for unit sales of PCs are now in the range of minus 5% to flat compared to 2008, whereas earlier forecasts were projecting year-on-year unit declines of 9 to 12%," Scalise noted. "In cell phone handsets, analysts now believe the unit decline will be in the range of 7 to 9% compared to earlier forecasts of a decline of around 15%. PCs and cell phones account for nearly 60% of worldwide semiconductor consumption."

SIA credited economic stimulus programs in China, including incentives for purchasing consumer products and investment in 3G/TDSCDMA communications infrastructure, as having helped drive semiconductor sales in the world’s largest chip market.

“The global macroeconomic environment remains the key factor in determining the timing and rate of recovery for the semiconductor industry,” Scalise concluded.

According to SIA data, sales in the Asia Pacific were up 23.2% in Q2 on a sequential basis. Q2 sales in the Americas were up 11.8% sequentially, while sales in Japan were up 17.9% and sales in Europe were up 0.5%.

Aug 1, 2009


The biennial International Semiconductor Device Research Symposium will take place on December 9-11, at the University of Maryland, College Park, Maryland USA.

This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact Modeling, so it can be interesting to go there and have a look.

Extended abstracts from the conference are published online through IEEE Xplore.
Furthermore, presenters may optionally submit a full-length manuscript to be considered for publication in a special issue of Solid State Electronics.

Another interesting advantage of presenting a paper at ISDRS 2009 is that it is held just after IEDM, and very close to the IEDM venue (Baltimore, Maryland), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS.

In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.

The University of Maryland in College Park is located just 4 miles outside of Washington DC. It is inside of the Capital beltway, accessible by the Washington DC Metro System (green line), and can be reached from all three of the Washington and Baltimore airports.

Jul 26, 2009

Agilent, China University team up on LTE testing

Mike Kawasaki, education program manager at Agilent, said that the company sees the R&D collaboration with Southeast University as a continuation of Agilent's drive to be a key technology partner for innovative research in academia. "This collaboration enables Agilent to make a contribution to the future of wireless communication and gives the university access to our resources, empowering further success of scientists in academia," he said. Read more...