Thursday, January 31, 2019

#IJNM #paper Ye Yuan Zheng Zhong Yong‐xin Guo Shanxiang Mu A novel large‐signal FET model considering trapping‐induced dispersions https://t.co/UYndQ8cKK1” https://t.co/vu0WQtnRgr https://t.co/BiU9XDDiZc


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January 31, 2019 at 04:30PM
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Monday, January 28, 2019

Multiphysics Simulation of Biosensors

M. Madec, L. Hébrard, J. Kammerer, A. Bonament, E. Rosati and C. Lallement
Multiphysics Simulation of Biosensors Involving 3D Biological Reaction-Diffusion Phenomena in a Standard Circuit EDA Environmen
IEEE Transactions on Circuits and Systems I: Regular Papers.
doi: 10.1109/TCSI.2018.2885223

Abstract: The topic of this paper is the development of biological models for 3D reaction-diffusion phenomena that can be used in any circuit electronic design automation environment for the simulation of biosensors. Biological systems that involve such 3D phenomena are described by partial differential equations. Our approach consists in discretizing these equations according to the finite-difference method and converting the resulting ordinary differential equations into an assembly of elementary electronic equivalent circuits that are directly simulated with SPICE. The main interest of this approach is the ability to couple such models with third-party SPICE models of electronic circuits, sensors, and transducers, i.e., models from any physical domain ruled by Kirchhoff laws, allowing modeling and simulation of any multi-physics systems in a conventional circuit design environment, here CADENCE. The tool is validated on simple problems for which analytical solutions are known. Then, the interest of the approach is illustrated on the study of a biosensor.

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8602461&isnumber=4358591

Wednesday, January 23, 2019

E.A. Vittoz “CRYSTAL (and MEMS) OSCILLATORS" (course) November 2018 DOI: 10.13140/RG.2.2.25856.07689 https://t.co/NBz9JnZNSL #paper https://t.co/3A1AvRYHd9


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January 23, 2019 at 10:16AM
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Monday, January 21, 2019

#C4P for a Special Issue of IEEE #TED on Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices https://t.co/0Tcarn2xGC #paper


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January 21, 2019 at 05:58PM
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Saturday, January 19, 2019

A #SPICE Compatible Compact #Model for #Hot-Carrier Degradation in MOSFETs Under Different Experimental Conditions - IEEE Journals & Magazine https://t.co/W7w1zqzXnn


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January 19, 2019 at 06:15PM
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Wednesday, January 16, 2019

#Baidu Announces #OpenSource Edge Computing Platform #OpenEdge https://t.co/PvmANhazM4 https://t.co/7xlZzlMANX


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January 16, 2019 at 01:58PM
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Monday, January 14, 2019

Environment for #Modeling and #Simulation of #Biosystems, Biosensors, and Lab-on-Chips #LoC - IEEE Journals & Magazine https://t.co/GJpZySIRda


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January 14, 2019 at 04:58PM
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#Cryogenic Characterization of 22-nm #FDSOI CMOS Technology for #Quantum #Computing ICs - IEEE Journals & Magazine https://t.co/gg4mCXztz3 #paper


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January 14, 2019 at 04:56PM
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Sunday, January 13, 2019

What #Opening the #MIPS #Architecture Could Mean https://t.co/z43S9tOMNJ #opensource


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January 13, 2019 at 06:58PM
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Saturday, January 12, 2019

Postdoctoral positions in device modeling in Spain


As Professor in the in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain., I am going to apply for a postdoctoral position (funded by the Spanish Ministry) related to modeling (in particular compact modeling) and/or parameter extraction of emerging devices we are targeting, such as Multi-Gate MOSFETs, nanowire FETs ,GaN HEMTs, Tunnel FETs, organic and metal oxide TFTs and hyLEDs.

The candidate should be a person who holds a PhD as awarded after January 1 2014.

Contracts will have a duration of two years are expected to start after June 2019.
The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. 

The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.
 

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: January 24 2019

MY E-MAIL ADDRESS IS: benjamin.iniguez@urv.cat

Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat
 
Benjamin Iñiguez

 
 
 

Friday, January 11, 2019

How #OpenSource Makes Us Better #Human Beings and Brings Us #Together https://t.co/1fUaAVzIqw https://t.co/VHtYEpgD32


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January 11, 2019 at 09:44AM
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Thursday, January 10, 2019

An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model

Ravi Goel, Chetan Gupta, Yogesh S. Chauhan
EE Department, Indian Institute of Technology Kanpur, Kanpur, India
Published in: 2018 5th IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON)

Abstract: Recent enhancement in BSIM-BULK (formerly BSIM6) model is presented in this work. The industry standard models like BSIM4, PSP, BSIM-BULK etc. lack the parameters for tuning of transconductance to channel current ratio (gm/Id). gm/Id is also a critical figure of merit for analog applications. Here, we propose an empirical model to enhance the flexibility of gm/Id tuning behavior. The proposed model provides good fitting for different channel lengths and drain bias.

Paper Sections:
I. Introduction
II. An Empirical Model for gm/Id Tuning
III. Model Implementation
IV. Model Validation with TCAD
V. Conclusion

Source:
DOI: 10.1109/UPCON.2018.8597065

Wednesday, January 9, 2019

#NEXTS Europe secures Europractice services to European academia and industry until end #2021 https://t.co/HsOfzwOY5z #model https://t.co/hXVWSabx05


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January 09, 2019 at 02:57PM
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Compact Transcapacitance Model for Short Channel DG FinFETs

(Proceedings of the Int. Conference on Microwave and THz Technologies and Wireless Comm.)
Ashkhen Yesayan
Institute of Radiophysics and Electronics
Alikhanian Brothers str. 1, 0203 Ashtarak, Armenia
Received 15 November 2018

Abstract: A compact capacitance model is developed accounting for small-geometry effects in FinFETs. While decreasing the channel length, the transcapacitance model becomes very sensitive to all short channel effects, both in moderate and strong inversion regimes. In addition, for short channel devices, we need to take into account the inter-electrode capacitive coupling in the subthreshold regime, which is not significant for long channel devices. The quantum mechanical effects, which are very significant for thin Fins, are included in the model. The effect of mobility degradation on C-V characteristics is also demonstrated. The model was validated with numerical 3D Atlas simulations and a good accuracy of the model has been demonstrated in all operating regimes.

References:
[1] Tech. rep., International technology roadmap for semiconductor (ITRS). 2009.
[2] J.-M. Sallese, F. Krummenacher, F. Pregaldiny, C. Lallement, A. Roy, C. Enz, A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism, Solid-State Electron, vol. 49 no. 3, pp. 485–489. 2005.
[3] A Yesayan, F Prégaldiny, N Chevillon, C Lallement, JM Sallese, Physics-based compact model for ultra-scaled FinFETs, Solid-State Electronics, vol. 62, no1, pp. 165-173, 2011.
[4] Liang X, Taur Y., A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Dev 2004;51(9):1385–91.
[5] Ward D, Dutton R. ,A charge-oriented model for MOS transistor capacitances. IEEE J Solid-State Circ, 1978;13(5):703–8.
[6] Tang M. Etude et modélisation compacte du transistor FinFET. Ph.D. Thesis, University of Strasbourg; December 2009.
[7] Borli H, Vinkenes K, Fjeldly T., Physics-based capacitance modeling of short-channel double-gate MOSFETs. Phys Status Solidi (c) 2008;5(12):3643–6.
[8] Arora N., MOSFET models for VLSI circuit simulation. New York: Theory and Practice, Springer-Verlag; 1993, ISBN:3-211-82395-6

Source:

#Julia Co-Creators To Receive 2019 James H. Wilkinson #Prize for #Numerical #Software https://t.co/5oLiWnuDZL #opensource


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January 09, 2019 at 08:12AM
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Wednesday, January 2, 2019

IEEE TED SI on Compact Modeling for Circuit Design

Special Issue on Compact Modeling for Circuit Design
Benjamin Iñiguez, Wladek Grabinski, Slobodan Mijalković, Kejun Xia, Andries J. Scholten, Yogesh Singh Chauhan, Ananda S. Roy, Sadayuki Yoshitomi, Kaikai Xu

in IEEE Transactions on Electron Devices, vol. 66, no. 1, Jan. 2019.
doi: 10.1109/TED.2018.2884284

Abstract: This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.


This Special Issue is dedicated to recent research in the field of compact modeling for circuit design. The topics included all device structures, provided it was demonstrated that the presented compact modeling solutions were implementable in circuit design tools. The last Special Issue addressing compact modeling of all types of semiconductor devices was published in 2006. Since then, new device structures, and with different materials, have emerged, and significant and successful research in compact advance device modeling has been done, as well in the application of compact models to circuit design. Therefore, a new Special Issue was needed that could include high-quality papers in these topics.

A total of 60 regular papers were submitted to this Special Issue, of which 21 were accepted. Besides, the Special Issue includes four invited papers. All papers, including the invited ones, were subjected to thorough peer review. A high number of reviewers have participated in this process. This has resulted in a Special Issue containing very high-quality papers.

The published papers target compact modeling aspects for a wide number of devices: several MOSFET structures, tunnel FETs, HEMTs, nanowire FETs, TMD FETs, TFTs, OLEDs, solar cells, photodiodes, and so on.Besides, different operation regimes and analyses are addressed: dc, RF, HV, ballistic regime, variability, reliability, aging, and so on.

The four invited papers also target different topics. The paper by C. C. McAndrew is focused on the successes and challenges of MOS compact models. S. Dongaonkar et al. address the opportunities and challenges of circuit design methodologies ranging from process corners to statistical circuit design. P. Zampardi et al. discuss the industrial view of III–V device compact modeling for circuit design. Finally, Madec et al. target a quite different and challenging environment for the modeling of biosensors, biosystems, and lab-on-chips.

I would like to thank the work done by the rest of the Editors of this Special Issue and also by all the reviewers who participated in this process. And of course, I want to thank all the authors for their interest in submitting papers to this Special Issue. Thanks to authors, reviewers, and editors, this high-quality Special Issue has been possible.