[paper] Ultralow-Voltage NMOS-Only Voltage Reference

Francesco Gagliardi, Paolo Bruschi, Massimo Piotto, Soumaya Sakouhi, Michele Dei

Ultralow-Voltage NMOS-Only Voltage Reference with High-Frequency PSR Optimization 

via Decoupling Pseudo-Resistor

IEEE ACCESS • Vol. 14, 2026

DOI: 10.1109/ACCESS.2026.3707314

Dipartimento di Ingegneria dell’Informazione, University of Pisa, 56122 Pisa (I)

Abstract: The design of integrated circuits operating at minimal supply voltage and power levels is a key requirement for energy-harvested smart sensing devices. This paper presents a novel NMOS-only 4-transistor voltage reference (VR) that exploits a self-cascode technique with high-frequency power-supply rejection (PSR) optimization through a decoupling pseudo-resistor. Post-layout simulations of a 0.18‑μm CMOS design show low-supply compliance and robustness to process-voltage-temperature variations. The output voltage is 177 mV with line sensitivity of 54 ppm/V in the 0.4–1.8 V supply range, PSR lower than –40 dB down to 0.28 V supply, simulated current consumption of 223 pA, and a mean temperature coefficient of 24.44 ppm/°C from –20 °C to 80 °C. The compact area footprint is 115.2 μm². The results indicate potential for stable low-voltage and low-power voltage reference implementations.

Fig: Small-signal equivalent circuits of (a) the 2T-VR and (b) the 3T-VR. The high-frequency path highlighted in (b) causes a limitation of the 3T-VR topology discussed at the end of this section.

Acknowledgements: This work was supported in part by the National Recovery and Resilience Plan (NRRP) of Italian Ministry of University and Research (MUR) funded by the European Union (EU) NextGenerationEU with the Project HeMoWear under Grant 0004610/2022, and in part by the European Innovation Council (EIC) through the Project Green valorization of CO2 and Nitrogen compounds for making fertilizers (CONFETI) under Grant 101115182. The associate editor coordinating the review of this manuscript and approving it for publication was Poki Chen.

[paper] Reconfigurable Characteristics in MoS2 Transistors

Matteo Farronato, Fabio Carletti, Niccolò Garegnani, Anupam Jana, Matteo Porzani, Saverio Ricci, Augusta Ungarelli, Christian Monzio Compagnoni, Paolo Fantini, Innocenzo Tortorelli, Agostino Pirovano, Christian Rinaldi and Daniele Ielmini

Voltage-controlled reconfigurable characteristics in MoS2 transistors 

via ion migration for reprogrammable logic.

NPJ 2D Mater Appl (2026)

DOI: 10.1038/s41699-026-00720-2

1 DEIB, Politecnico di Milano and IU.NET, Milano, Italy

2 Dipartimento di Fisica, Politecnico di Milano, Italy

3 Micron Technology Inc., Vimercate (MB), Italy

Abstract: 2D semiconductors such as MoS2 offer a promising pathway for future logic and analog transistors and memories. These materials feature scalable channel size, back-end of the line compatibility, and high mobility for relatively small channel thickness approaching few atomic monolayers. An open issue for the development of mature 2D-based digital technology is the availability of both n- and p-type transistors, as well as the ability to control the transistor type in a reconfigurable way. This work presents a novel MoS2-based transistor exhibiting reconfigurable n- or p-type characteristics, namely switching from n-type to p-type and vice versa, which is attributed to ion-assisted doping from the gate dielectric layer. Extensive characterization of the device shows repeatable switching with relatively low cycle-to-cycle (C2C) and device-to-device (D2D) variability. A reconfigurable p-n junction is demonstrated via a junction-less multi-gate MoS2-based transistor. We also demonstrate various reconfigurable logic gates, including a complementary metal-oxide-semiconductor (CMOS) inverter, a fully n-type inverter and an XNOR logic gate based on MoS2 transistors, showcasing the generality and flexibility of channel reconfiguration for logic circuit applications. These results underscore the strong potential of reconfigurable MoS2 transistors for ultra-scaled, reconfigurable logic circuits.

Fig: Logic gates with reconfigurable MoS2 transistors. (a) SEM image of a logic inverter or CMOSNOT gate with two transistors in the same MoS2 flake. (b) Schematic of the inverter with reconfigurable MoS2 transistors and logic truth table.

Acknowledgments: This article has received funding from the European Research Council (ERC) under the EuropeanUnion’s Horizon Europe Research and Innovation Programme (grant 101054098). Authors want tothank all the Polifab (the micro and nano technology infrastructure of Politecnico di Milano) staff fortheir help in the fabrication of the MoS2-based devices.

[paper] Harmonic Distortion of GaN HEMT Varactors

Loukas Chevas 1,  Matthias Bucher 1,  Nikolaos Makris 1,2, Ioannis Spiridon Fosteris 1,  Nikolaos Fasarakis 1,  Antonios Stavrinidis 2,1, Maria Kayambaki 2,  Athanasios Kostopoulos 2 

and George Konstantinidis 2

Methodology for Harmonic Distortion Characterization and Modelling of GaN HEMT Varactors

Instruments 2026, 10(3), 37; 

DOI: 10.3390/instruments10030037

1 School of Electrical and Computer Engineering, Technical University of Crete, 73500 Chania, Greece
2 Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas, 70013 Heraklion, Greece

Abstract: The bias-dependent capacitance of varactors can introduce harmonic distortion into the circuits where they are utilized. A gate capacitance model valid through inversion–depletion has been presented for GaN HEMT varactors in the drive for their utilization in monolithic GaN ASICs. This work focuses on the circuit and the methodology employed to accurately measure on wafer the harmonic distortion caused by one such device. The circuit is presented and its design considerations and operation trade-offs are discussed, followed by a presentation of the measurements resulting from its use. Second- and third-order harmonic distortion is recorded and presented, with Verilog-A model simulations used to fit the measured data. The model consists of a charge-based expression of the HEMT varactor capacitance, with a minimal number of parameters. The good fit of the model is demonstrated, proving both the suitability of the circuit used for the measurements and the validity of the capacitance model for real-world applications.  

Fig: Measurement setup schematic for the harmonic distortion characterization of HEMT varactors and V(f) characterization of the HEMT varactor. Inset is the parallel impedance combination measured by the LCR meter. (a) Cgc(Vg) for fixed frequencies. (b) Cgc(f) for fixed Vg levels. (c) Rp(Vg) for fixed frequencies. (d) Rp(f) for fixed Vg levels.

Aknowlegements: This research was partially funded by the European Union under the project AGAMI_EURIGAMI (ID:101102983).

Data Availability Statement: The measurement data generated and analyzed during the present study are available from the corresponding author upon reasonable request.

[mos-ak] [Final Program] 23rd MOS-AK/ESSERC Workshop in Palma de Mallorca (SP) Sept. 7, 2026

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

MOS-AK FOSS OpenPDK Workshop
ESSERC, Palma de Mallorca, Sept. 7 2026

The 23rd MOS‑AK/ESSERC Compact Modeling Workshop in Palma de Mallorca brings together the international community advancing SPICE/Verilog‑A modeling, OpenPDKs, and open‑source IC design flows. Since 2002 ESSEDRC/ESSCIRC in Porto, MOS‑AK has been the leading forum connecting technology developers, circuit designers, and FOSS CAD/EDA contributors, supporting knowledge exchange and strengthening the open semiconductor ecosystem. This year’s program showcases cutting‑edge developments: GaN MOS‑HEMT compact models for emerging OpenPDKs, AI/ML‑driven modeling workflows replacing manual tuning, cryogenic FD‑SOI model libraries, fully open‑source RFIC design case studies using IIC‑OSIC‑TOOLS, reliability insights for advanced CMOS and RF technologies, and a new OpenPDK MOSFET matching matrix IC enabling fast mismatch characterization. The workshop organizers are inviting engineers, researchers, and students who want a clear, practical view of modern device models and open simulation frameworks. It directly supports global OpenPDK adoption and aligns with European ODE4EC‑AMS activities, promoting accessible, reproducible, and future‑ready IC design methodologies. The MOS-AK workshop program is available online as well as with the direct link:

<https://www.mos-ak.org/palma_2026/>

Venue: ESSERC, Palma de Mallorca (SP)
Online Registration is OPEN (Early: until FRIDAY July 17, 2026)

MOS-AK ESSERC W7 Workshop Agenda

9:30 - 11:00	W7 Workshop Opening
T_1	ODE4EC-AMS OpenPDK: the Status and Roadmap Wladek Grabinski IHP OpenPDK (D)
T_2	Advanced in Verilog-A Model Standardization Arpad Buermen Uni. Ljubljana (SL)
T_3	Compact Modeling of GaN MOS-HEMTs for Open PDKs Ashkhen Yesayan EPFL (CH)
T_4	From Manual Tuning to Agentic AI: Transforming Device Modeling with AI/ML Roberto Tinti Keysight (US)
11:00 - 11:30	Coffee Break
T_5	Development of Cryogenic Model Libraries for FD-SOI Transistors Phanish Chava AdMOS (D)
T_6	Open-Source RFIC Design: Case Studies Using IIC-OSIC-TOOLS Georg Zachl JKU Linz (A)
T_7	Reliability topics for the miniaturization and qualification in OpenSilicon perspective Fernando Guarin IEEE EDS D1 (US)
T_8	OpenPDK MOSFET Matching Matrix IC Juan Brito CEITEC (BR)
13:00-14:00	End of the W7 Workshop and Lunch Break

W.Grabinski for Extended MOS-AK Committee

WG060726

[mos-ak] [C4P] Submissions Now Open for IEDM 2026

Submit a Paper Meeting Info Contact Us Submissions Now Open Deadline: July 16, 2026 The IEEE International Electron Devices Meeting Committee is seeking paper submissions for the 2026 IEDM Conference, themed “Devices at the Hearth of the Intelligence Revolution” We invite contributions from various areas of expertise (view all suggested topics).  Format: Papers must be submitted electronically in a PDF format, compatible with IEEE Xplore Guidelines: Before preparing your paper, please review the paper preparation and submission guidelines on our website where you’ll find a paper template, sample paper and additional preparation details. Presentation: Accepted papers MUST be presented in person at the conference AND authors must submit a pre-recording of their presentation for OnDemand registrants. Call for Papers Info Student Papers We highly encourage student submissions. Papers presented by students based on their own work are eligible for the Best Student Paper Award. To be considered, the paper must be identified as a student paper during submission. The award will be judged on the paper's quality and its presentation, which must be delivered by the student. The winner of the award will be announced and honored at IEDM 2027. MEETING HIGHLIGHTS IEDM is the world’s preeminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference will feature: Three plenary presentations  Special focus sessions  Evening panel discussions  Tutorial sessions Short Courses  Mark your calendar for December 12-16, 2026, and join us in San Francisco, CA. Attendee:  For more information IEDM Online Email: info@ieee-iedm.org Social Networks (Info/Follow) IEDM | Canfield Event Management, LLC | +1 972 521-9902 | ieee-iedm@cemllc.com

IEDM | 445 Hoes Lane | Piscataway, NJ 08854 US

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[paper] SPICE-Q Quantum Chip Production

Ling Qiao Cai1,2, Bin Yang1,2, Fumin Luo1,2, Chang Liu1,2, WeiGui Guo1,2, GuoRong Zhang1,2, XueFei Liu1,2, Qinglang Guo1,2 and Bin Wu

SPICE-Q and Large-Scale Quantum Chip Production

[quant-ph] 16 Jun 2026 

arXiv:2606.17907v1  

1.) Yangtze Delta Industrial Innovation Center of Quantum Science and Technology, Suzhou, (CN)
2.) China Academy of Electronics and Information Technology, No. 11 Shuangyuan Road, Shijingshan District, Beijing, (CN)

Abstract: The historical analogy with SPICE is based on foundational reports, numerical methods, and experience from integrated circuit design. The requirements for quantum computing and scaling refer to established work in the field. The background on superconducting qubits, transmons, circuit quantum electrodynamics, microwave networks, material loss, and three‑dimensional interconnects draw from widely recognized literature. The background on parameter extraction, simulation frameworks, and manufacturability is informed by recent research and practical developments.

Table of Contents (Top‑Level Sections)

1. Abstract ... p. 4
2. The Emergence of SPICE and Large‑Scale Classical Circuits
   and Its Implications for Quantum Chips ... p. 5
3. SPICE‑Q Model Composition ... p. 24
4. SPICE‑Q Device‑Level Models ... p. 40
5. Standardized Manufacturing System ... p. 53
6. Integrating SPICE‑Q with Process Models ... p. 66
7. Design‑Technology Co‑Optimization (DTCO) ... p. 71
8. Large‑Scale Production Examples and Design Scenarios ... p. 75
9. Engineering Transition and Large‑Scale Quantum Chips ... p. 80
10. Summary ... p. 84
11. Acknowledgment ... p. 87
12. Reference ... p. 87
13. Appendix A ... p. 90

Acknowledgment The authors thank Jun Ye for helpful assistance. The authors also acknowledge the use

of AI tools for translation assistance and auxiliary text generation.

[paper] 130-nm CMOS tunnel p-bit cell

Ju-Young Yoon, Nuno Caçoilo, Advait Madhavan, Jabez J. McClelland, Shun Kanai, Hideo Ohno, Shunsuke Fukami, and William A. Borders, 

"130-nm CMOS-integrated superparamagnetic tunnel junction-based p-bit," 

in IEEE Electron Device Letters, 

DOI: 10.1109/LED.2026.3696800

Abstract: Probabilistic computers offer promising solutions for computationally hard problems in domains such as combinatorial optimization and machine learning. A key building block in these systems is the probabilistic bit (p-bit), which relies on superparamagnetic tunnel junctions (sMTJs) as its source of randomness. A challenging threshold to cross for scaling sMTJ-based p-bit systems is integration of sMTJs with CMOS technology. In this work, we present experimental results of a p-bit unit cell using sMTJs integrated with 130 nm CMOS technology and demonstrate that the sMTJ’s resistance fluctuations can generate a corresponding fluctuating digital output voltage which is tunable via the input voltage. These findings establish the feasibility of CMOS-compatible, sMTJ-based probabilistic circuits and mark a key step toward scalable hardware for real-world probabilistic computing applications. 

FIG: (a) Circuit diagram of the spintronic p-bit; b) Schematic cross-sectional structure of the spintronic p-bit. Transistors and lower interconnect layers were fabricated at SkyWater, followed by fabrication of the spintronic devices at Uni. Tohoku. (c,d) Cross-sectional and plan-view electron microscope images of the spintronic device designed to exhibit stochastic fluctuations.

Acknowledgements: This work was made possible by the NIST-led Nanotechnology Xccelerator program that distributes open-source circuit designs for integration of novel technologies on CMOS.

RevEDA v0.9.0 Has Arrived

Revolution EDA v0.9.0 Has Arrived The wait is over. Revolution EDA v0.9.0 is now available, delivering our largest feature update to date and taking another major step toward a complete open-source analog and mixed-signal IC design platform. This release introduces integrated verification workflows, expanded simulation support, AI-assisted design tools, a new plugin ecosystem, and important architectural improvements designed to help engineers move faster from concept to silicon. Why This Release Matters Version 0.9.0 brings together capabilities that traditionally require multiple disconnected tools. By integrating verification, automation, extensibility, and simulation workflows into a unified environment, Revolution EDA continues to make professional IC design more accessible to engineers, researchers, educators, and startups. Highlights of v0.9.0 Integrated LVS Verification Layout-versus-Schematic (LVS) checking is now built directly into Revolution EDA. Users can: Extract hierarchical netlists from layouts and schematics Compare extracted and reference netlists Review detailed mismatch reports Cross-probe errors between schematic and layout views This significantly reduces verification effort and helps catch issues earlier in the design cycle. Expanded Simulation Support Revolution EDA now includes support for Xyce netlist generation, providing greater flexibility for simulation workflows. In addition, support for Spectre and VACASK netlisting is actively under development, bringing us closer to a truly multi-simulator environment. Hierarchical netlisting has also been enhanced with support for buses and instance arrays, enabling more complex and scalable designs. AI-Powered Design Assistance The new AI Terminal allows designers to interact with Revolution EDA using natural language. From automating repetitive tasks to exploring design modifications and workflow assistance, AI capabilities are becoming a native part of the design experience. We're only at the beginning of what's possible, and future releases will continue expanding these capabilities. New Plugin & Library Registry One of the most requested features is finally here. The new Plugin Registry and Library Registry make it simple to discover, install, and manage extensions directly from within Revolution EDA. The underlying architecture has also been redesigned to support clean integration of: Process Design Kits (PDKs) Plugins Custom workflows Third-party extensions without requiring modifications to the core codebase. Foundations for Schematic-Driven Layout Version 0.9.0 introduces the first implementation of Schematic Driven Layout (SDL), creating the foundation for tighter synchronization between circuit intent and physical implementation. Future releases will continue building on this capability to further streamline analog layout development. Coming Soon: Expanded IHP PDK Support We're also excited to share that work on the IHP PDK continues at a rapid pace. New parametric cells (PCells) are currently being added and validated, expanding device coverage and improving layout productivity. These additions are expected to be released shortly, providing designers with a richer and more capable open-source design environment built around the IHP technologies. Stay tuned for a dedicated announcement in the coming weeks. Under the Hood Improvements Alongside the headline features, v0.9.0 includes substantial improvements to performance, stability, and usability: Improved file validation and project security Faster editor responsiveness Better thread management and application stability Enhanced project workflows Numerous bug fixes across netlisting, layout editing, and plugin management MPL-2.0 Licensing Beginning with v0.9.0, Revolution EDA is distributed under the Mozilla Public License 2.0 (MPL-2.0). This change supports broader commercial and academic adoption while preserving the collaborative spirit of open-source development. Download v0.9.0 Today Whether you're designing analog ICs, building custom design flows, developing plugins, or evaluating open-source EDA solutions, Revolution EDA v0.9.0 offers powerful new capabilities ready for exploration. Download the latest release, update your existing installation, and let us know what you build. As always, your feedback, bug reports, feature requests, and contributions help shape the future of Revolution EDA. Contact us! The Revolution EDA Team

ChipFoundry September Shuttle

The commitment deadline for our September shuttle is fast approaching on July 18th.   We want to remind you that this is not the final design submission date. Here is what you need to know to confirm your space:   A 50% payment is required by July 18th to hold your reservation. Your final design files are not due until September 16th. You only need to provide your user project wrapper, and we will handle the integration through our tapeout flow.   Our team is available if you have any questions about the submission process or need help with your invoice. Reserve Now We look forward to confirming your commitment and working with you on your September tapeout!   Best regards,   The ChipFoundry Team

[SwissChips] Annual Event 2026

On 4 June 2026, the SwissChips community gathered for this year’s Annual Event at the SwissTech Convention Center in Lausanne, EPFL. With over 270 attendees, more than 50 posters, and 14 talks, the day was packed with updates, talks, and networking. We heard from across the SwissChips work packages, welcomed contributions from the wider ecosystem, and had the pleasure of having a keynote by Prof. Alberto Sangiovanni-Vincentelli from the University of California, Berkeley. The first half of the keynote from the event is available Download here (PDF, 5.8 MB)

SwissChips program included a keynote by Prof. Alberto Sangiovanni-Vincentelli from the University of California, Berkeley. The first half of the keynote from the event is available  Download here (PDF, 5.8 MB)

Following are the SwissChips presentation highlights showcasing Swiss’ growing engagement and support of the IHP OpenPDK Initiative. It's a fast‑rising, community‑driven effort that is opening real pathways for education, research, and innovation in microelectronics.

Guest Speaker: Thanushan Kugathasan, University of Geneva, presented Pixel Chips for Radiation and Optical Sensing with Tape-out completed in December 2025 and the wafer fabrication at IHP Microelectronics using 130 nm SiGe BiCMOS process.

Pixel Chips for Radiation and Optical Sensing werw implemented using IHP 130 nm BiCMOS technology through Europractice R&D collaboration for process optimization and SiGe HBTs integration within a CMOS platform.

Arianna Rubino, ETHZ, has presented the EZ130V1 open-source standard-cell library, it's available as the improved open library SG13G2 for IHP130 process:

• EZ130V1 has 213 cells - ~3x than SG13G2

• 8-track height - 11% lower height than SG13G2

Some of the standard cells created during VLSI 5 EZ130V1 otimization are eg: 

• AND3X2

• XNOR3X2

• HAX2

Croc SoC-based designs realized through a joined VLSI 2 and VLSI 5 effort are:

• KOOPA EZ130v0 library 39 cells

• SKOLL EZ130v1 library213 cells

[FSiC2026] Open EDA · Open Silicon · Sovereign by Design

FSiC2026

Free Silicon Conference 2026

Open EDA · Open Silicon · Sovereign by Design

What is FSiC? The annual gathering of the free and open-source silicon community building open EDA tools, open PDKs, and free hardware. Three days of talks and tutorials about designing chips with software you can read, share, and modify.

Who should come? Chip designers, EDA developers, researchers, students, and anyone curious about building silicon without proprietary lock-in. All experience levels welcome.

When? 6–8 July 2026

Where? University of Ljubljana, 

Faculty of Electrical Engineering

Tržaška cesta 25

SI-1000 Ljubljana

Registration closes 22 June: https://pretix.eu/FSiC/2026/

FSiC2026 Program: https://wiki.f-si.org/index.php/FSiC2026

[IHP OpenPDK] Analog IC Design Using Open Source Tools

Analog IC Design Using Open Source Tools and IHP-Open-PDK

at TU Poznan prior to MIXDES 2026

June 24, 2026

<https://www.mixdes.org/Mixdes3/tekst/view/openpdk-analog>

It is interactive demonstration workshop format with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. with the possibility to work at stations prepared by the organizer. Personal computers are not required; however, participants may use their own laptops if they wish. The workshop is embedded into the IEEE EDS FET100 Anniversary celebration. Our workshop's expected outcome is successful integrated circuits (IC) design, submission, and fabrication (tapeout) of participants created ICs. To recognize excellence in hands‑on integrated‑circuit design, the IEEE EDS will present Student Open Silicon Prizes for outstanding student in IC design. The IEEE Electron Devices Society (EDS), together with other IEEE societies, covers complete flow from the electron devices to IC designs thru CAD/EDA software support:

• Devices (EDS): semiconductor physics, fabrication technologies
• Circuits (SSCS, CASS): analog, digital, mixed-signal, system-level design
• Design Automation (CEDA): CAD tools, verification, open-source flows

AGENDA

Start	End	Topic
8:00	8:30	Participant registration, organizational introduction
8:30	9:00	FET100 Inauguration Speech¹: Prof. K. Detka, IEEE EDS Poland
9:00	10:30	OpenSilicon DIY Integrated Circuits²: Dr. Krzysztof Herman, IHP (D) Introduction to analog design in an open-source environment (Tools overview: Xschem, Ngspice, IHP-Open-PDK, workflow basics)
10:30	10:45	Coffee break
10:45	12:30	Analog schematic design in Xschem best practices, parameterization, DC, AC, and transient simulations (live demo)
12:30	13:30	FET100 Luncheon Talk³: W. Grabinski, IEEE EDS R8 Chair
13:30	15:00	Design of a sample analog circuit operation analysis, Monte Carlo simulations, mismatch analysis, parameter verification (live demo)
15:00	15:15	Coffee break
15:15	17:00	Introduction to layout in KLayout, analog design principles (matching, symmetry, noise minimization), PyCells mask design automation (live demo)
17:00	18:00	Complete design flow: from schematic to verification (LVS/DRC process overview), fillers, chip finishing, sign-off (live demo)
18:00	18:30	Q&A session, workshop summary
18:30	>>	FET100 Celebration Appero

Workshop Tutors:

Dr. Krzysztof Herman, IHP (D); Organizer and Technical Expert Lead

Dr. Wladek Grabinski, IEEE EDS; Technical Assistant

[ICMC] Registration Reminder

Less Than 2 Months Until ICMC 2026 Save $50 if you register before June 30, 2026 Join the global compact modeling community this July at the International Compact Modeling Conference (ICMC 2026), taking place July 30–31, 2026, aboard the historic Queen Mary in Long Beach, California. ICMC brings together leaders in compact modeling, process technology, circuit design, and device development for two days of technical exchange, collaboration, and discussion around the future of semiconductor modeling and simulation. By attending ICMC 2026, participants will have the opportunity to: • Engage in discussions shaping the evolution of compact models • Learn from leading academic researchers and industry experts • Explore technical sessions focused on real-world applications and emerging technologies • Connect with peers across academia, foundries, EDA, and device engineering • Participate in poster sessions, networking opportunities, and collaborative discussions Hosted aboard the iconic Queen Mary in Long Beach, attendees will experience a venue unlike any other conference setting. Once a renowned transatlantic ocean liner and historic World War II troopship, the Queen Mary now serves as a floating hotel and event destination rich in history, architecture, and atmosphere. With less than two months remaining, now is the time to finalize your plans and join the conversations advancing compact modeling technologies and applications. We look forward to welcoming you to Long Beach! View the Program Register Now Conference Sponsors Media Sponsors Industry Sponsors