Seeing Transistor Scaling Up Close

 And What “tiny” Really Means - Comparing Modern Chips to the Machines of Life

BEHIND THE CHIP: Apr 17, 2026

<https://behindthechip.substack.com/p/seeing-transistor-scaling-up-close>

[repost] Modern transistors have gate lengths of around 8 nm. To put that in perspective: a red blood cell is 10,000 nm wide. A DNA strand is just 2 nm, and a transistor is sitting right between those two scales. We are literally engineering at the edge of atomic limits, silicon atoms themselves are only 0.2 nm wide.

That foundational brick of modern electronics keeps shrinking year after year, driven by companies like TSMC, Intel, Samsung, and ASML pushing the boundaries of what is physically possible.

Billions of these switches/transistors, smaller than a virus, packed into a chip you can hold between two fingers. That is what powers every microcontroller, every processor, every smart device you touch today.

Revolution EDA Mistral AI Experiments

Revolution EDA MistralAI Experiments

by Murat Eskiyerli  

There was a recent article by Prof Razavi, where the problems of Large Language Models in identifying various analogue integrated circuit blocks were recounted.

Revolution EDA uses structured JSON data format to store design files. JSON also happens to be very easy for LLMs to parse and understand. In fact, Mistral AI has a JSON mode. Mistral AI is the latest addition to the growing number of LLMs that Revolution EDA is able to use.

We did ask a few questions to Mistral AI to test its understanding of designs in Revolution EDA and its potential to help designers. The results have been very encouraging. The future analogue integrated circuit designers will be able to use large language models like Mistral AI to quickly gain understanding of a circuit and improve on it.

The transcription below is taken exactly from the interaction with Mistral AI except for small formatting changes [read more...]

2nd Semiconductor Device Frontier Summit

Date: May 18, 2026; Time: 10:00AM ~ 05:00PM

Ewha Womans University Student Culture Center (Small Theater B101)

The Semiconductor Device Research Group of the Society of Semiconductor Engineers has been holding this event since 2025 to strengthen human networks among domestic researchers and share the latest research trends.

This year's summit, now in its second year, invited top-notch speakers from various fields to provide a broad view of the latest technologies in industry and academia. It will be a place for meaningful academic exchanges to grasp the latest semiconductor technology trends as well as to share in-depth opinions on international market trends. This event is co-organized by the Society of Semiconductor Engineers and the IEEE EDS Seoul Section Chapter and aims to become an international event representing the semiconductor device field in Korea in the future. We ask for your interest and participation so that the 'Semiconductor Device Frontier Summit', which will be the core pillar of the Korean researcher network, can become the cornerstone of the development of our semiconductor industry.

Pre-registration deadline: Until May 16, 2026 (Saturday)

Time	Program
Opening Session
10:00 – 10:20	Welcome & Registration
10:20 – 10:30	Opening Remarks (Prof. Sung‑Jae Cho, Ewha Womans University)
Session 1 | Chair: Prof. Sung‑Jae Cho
10:30 – 11:15	Semiconductor Devices for the New Computing Era Prof. Woo‑Young Choi, Seoul National University
11:15 – 12:00	Development Strategy for AI‑Oriented NAND Solutions Prof. Ki‑Hwan Song, Yonsei University
12:00 – 13:30	Lunch
Session 2 | Chair: Prof. Myung‑Gon Kang
13:30 – 14:15	Trends and Outlook of eNVM Technology Visiting Prof. Yong‑Gyu Lee, Seoul National University
14:15 – 15:00	Memcapacitor Technology for Charge‑Domain PIM Implementation Prof. Tae‑Hyun Kim, Seoul National University of Science and Technology
15:00 – 15:10	Coffee Break
Session 3 | Chair: Prof. Il‑Hwan Cho
15:10 – 15:55	Atomically Thin 2D Semiconductor Electronics toward Beyond‑CMOS Technology Prof. Chul‑Ho Lee, Seoul National University
15:55 – 16:40	Orders‑of‑Magnitude Faster TCAD Device Simulation of GAA MOSFETs without Additional Computational Training Cost Prof. Sung‑Min Hong, GIST
16:40 – 17:00	Closing Ceremony | Prof. Il‑Hwan Cho, Myongji University

[chapter] Modeling of the MOSFETs

Jean-Marc Dienot, “A Review on Analytical and Electrical Modeling of the MOSFET Transistor”

Chapter 2 in "Field-Effect Transistors – Fundamentals, Technologies, and Future Applications"

Editor: Kenan Cicek

DOI: 10.5772/intechopen.1009040

ABSTRACT: Power semiconductor MOSFET and other MOS-controlled devices benefit from material and technology improvements to respond to high-level power features, high voltage, high current density, short switching times, and thermal constants, which optimize energy efficiency. These enhanced characteristics induce more electromagnetic noises and temperature-management constraints for the deployment of this technology. We describe synthetically modeling theory and technic, from basic-to-advanced, to derive predictive simulations for the power MOSFET challenging issues. Analytical and electrical circuit model of the MOSFET elementary cell at semiconductor level, time-domain simulation. Distributed and propagative model, including device packaging and power-printed circuit board (PPCB) PEEC and 3D model levels, signal integrity simulation, common mode emission simulation, and radiated field simulation. Electro-thermal model with thermal propagative network model coupled with electrical model at circuit level, time multi-domain simulation. Case studies on Power PCB with MOSFET Si et SiC illustrate modeling procedures.

FIG: Overeview of analytical equations of the MOSFETs

 

[Newsletter] Revolution EDA April 2026

Revolution EDA has two updates to share this month: 

• a browser-based cloud trial environment is now live, and 
• hierarchical Layout vs Schematic (LVS) verification has been added to the platform

Cloud Trial Environment

[paper] Open-Source SkyWater 130 nm MOSFETs at 77K

F. Beall1, A. Rimal1, O. Seidel1, Y. Mei1, A. D. McDonald3, I. Parmaksiz5,1 V. A. Chirayath1, J. Asaadi1, D. Braga2, J. B. R. Battat4

DC Cryogenic Modeling of Open-Source SkyWater 130 nm MOSFETs at 77K Using BSIM4

arXiv:2604.21625v1 [cond-mat.mes-hall] 23 Apr 2026

1 The University of Texas at Arlington, Physics Department, Arlington, TX 76019, USA
2 Fermi National Accelerator Laboratory, Microelectronics Department, Batavia, IL 60510, USA
3 Instrumentation Frontier Scientific, Arlington, TX 76019, USA
4 Wellesley College, Physics and Astronomy Department, Wellesley, MA 02481, USA
5 Rice University, Physics Department, Houston, TX 77005, USA

Abstract: Cryogenic applications in high-energy physics (HEP) demand reliable, low-power CMOS electronics capable of operating at liquid nitrogen temperatures (77K). The open-source SkyWater 130nm (SKY130) CMOS process has previously been shown to operate at temperatures as low as 4K making it a promising candidate for HEP applications. In this work, we characterize and model SKY130 low-threshold voltage transistors at 77K, which is a temperature commonly used in modeling applications for liquid argon detectors. DC characteristic measurements were performed at both room temperature and liquid nitrogen temperature. We created a cryogenic modeling approach to produce a SPICE-compatible, isothermal BSIM4-based model for select transistor sizes at 77K. The resulting model agrees with data at 77K with an average error on the order of 20% (relative RMS) and shows no dependence on drain voltage. Due to the open-source nature of SKY130, we have made our models publicly available on Github. We hope this work will continue the trend for democratizing circuit design at cryogenic temperatures in high-energy physics by enabling open access to accurate cryogenic CMOS device models at 77K.

Fig: Hardware setup used for I-V measurements: (a) Schematic of the I-V measurement

system (b) Wirebonded SKY130 chip mounted on PCB

Acknowledgments: The authors would like to thank various engineers in the microelectronics department at FNAL for their guidance and assistance on this project: Albert Dyer for help operating the cryo-cooler, and Louis Dal Monte and Pamela Klabbers for PCB design. The authors would also like to extend gratitude to Andy Pender from Synopsys for assistance with the modeling software, Mystic™. This material is also based upon work supported by U.S. Department of Energy, Office of Science, Office of High Energy Physics under Award Number DE-SC0022296 and DE-SC00253485 as well as support from the University of Texas at Arlington’s Center for Advanced Detector Technologies.

[paper] Multi-Agent Self-Evolved ABC

Cunxi Yu and Haoxing Ren

Autonomous Evolution of EDA Tools: Multi-Agent Self-Evolved ABC

In 63rd ACM/IEEE Design Automation Conference (DAC ’26)

July 26–29, 2026, Long Beach, CA

DOI: 10.1145/3770743.3804221

Abstract: This paper introduces the first self-evolving logic synthesis framework, which leverages Large Language Model (LLM) agents to autonomously improve the source code of ABC, the widely adopted logic synthesis system. Our framework operates on the entire integrated ABC codebase, and the output repository preserves its single-binary execution model and command interface. In the initial evolution cycle, we bootstrap the system using existing prior open-source synthesis components, covering flow tuning, logic minimization, and technology mapping, but without manually injecting new heuristics. On top of this foundation, a team of LLM-based agents iteratively rewrites and evolves specific sub-components of ABC following our “programming guidance“ prompts under a unified correctness and QoR-driven evaluation loop. Each evolution cycle proposes code modifications, compiles the integrated binary, validates correctness, and evaluates quality-of-results (QoR) on multi-suite benchmarks including ISCAS 85/89/99, VTR, EPFL, and IWLS 2005. Through continuous feedback, the system discovers optimizations beyond human-designed heuristics, effectively learning new synthesis strategies that enhance QoR. We detail the architecture of this self-improving system, its integration with ABC, and results demonstrating that the framework can autonomously and progressively improve EDA tool at full million-line scale.

Fig: Overview of the multi-agent self-evolving framework for ABC. Specialized LLM agents evolve distinct subsystems (flow optimization, core algorithms, and mapping), with each iteration undergoing compilation, formal CEC verification, and full QoR evaluation. A planning agent coordinates global decisions, a coding agent implements edits, and all agents follow a shared rulebase and unified evaluation pipeline to enable coordinated, correctness-preserving improvements.

Acknowledgment: The authors would like to thank Prof. Zhiru Zhang and his students for their valuable feedback and insightful discussions.

May 2026 Event "ISHI Kai 3rd Anniversary Event

May 2026 Event ISHI Kai 3rd Anniversary Event 

Gift to Students, Newcomers, and Semiconductor Beginners!

Tokyo Venue

Contents

The ISHI Association has finally celebrated its third anniversary!
This time, we have collected content for students, newcomers, and semiconductor beginners. What should university teachers and those who have done open source semiconductors do to step up for students and newcomers? And what means are there? This time, there are also on-site participation slots in Tokyo and Fukuoka, so please join us. This is only available for applications for the Tokyo venue.

Click here to apply for the Fukuoka venue >> https://ishikai.connpass.com/event/381975/

The activity is done on Discord. We hope you will join us!
(If it is disabled, please contact Noritsuna Atmark ishi-kai.org) 
https://discord.gg/Sj47dJk8x7

Participation fee >> Free

[papers] Charge-Based MOSFET Compact Models with ACM-2

IEEE 17th Latin America Symposium on Circuits and System 

LASCAS, Arequipa, Peru

24-27 February 2026

[1] R. Fiorelli, M. Miguez and J. Núñez, "Exploring Charge-Based Mosfet Compact Models with ACM-2 as a Design-Oriented Paradigm," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457086.

Abstract: Charge-based MOSFET compact models provide a physically consistent framework to describe transistor charges and capacitances across operating regimes. Unlike current-based approaches, they enforce charge conservation and yield reliable predictions of dynamic and RF behavior. This paper reviews the main charge-based formulations, ranging from industrial standards (BSIM, PSP, HiSIM) to academic compact models such as EKV and the recent ACM-2 five-parameter approach. We contrast their philosophies, complexity, and accuracy, highlighting the trade-offs between highly parameterized industrial models and compact analytical formulations oriented to design and education. Representative applications in analog/RF design, digital timing and power estimation are discussed. Particular attention is given to the lightweight ACM-2 model as a paradigmatic example of simplicity and analytical clarity. We conclude by outlining current challenges-advanced device architectures, quantum effects, and automated parameter extraction-and perspectives for future compact modeling in deeply scaled technologies.

[2] C. A. Dobrin, D. G. A. Neto, D. Gaidioz, P. Cathelin, S. Bourdel and M. J. Barragan, "RF Design-Oriented ACM Model Generation Using Parametric Test and Machine Learning Regression in 28nm FD-SOI CMOS Technology," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457152.

Abstract: This paper presents a methodology for extracting design-oriented MOS transistor models from wafer-level parametric test (PT) data, enabling accurate post-fabrication circuit characterization that inherently accounts for process variability. Leveraging an advanced compact MOSFET (ACM) model, the approach employs a neural network regressor to predict critical RF transistor parameters, including DC characteristics, parasitic capacitances, and excess noise factor, from standard PT measurements routinely collected during production. The regressed parameters are gathered into a Verilog-A component that faithfully represents the electrical behavior of fabricated transistors, facilitating variability-aware simulation and performance analysis of RF integrated circuits without requiring additional test structures or any measurement overhead. Validation on 28 nm FD-SOI technology shows high prediction accuracy for NMOS devices, confirming the effectiveness of the methodology as a tool for supporting post-fabrication circuit simulations and process variability management.

[3] D. G. A. Neto, M. C. Schneider, M. J. Barragan, S. Bourdel and C. Galup-Montoro, "Benchmarking the Symmetry of MOSFET Compact Models with Emphasis on ACM2," 2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS), Arequipa, Peru, 2026, pp. 1-5, doi: 10.1109/LASCAS67804.2026.11457119.

Abstract: The symmetrically built MOS transistors of integrated circuits exhibit symmetric electrical behavior if the source and drain terminals are interchanged. Additionally, a series association of transistors is electrically “equivalent” to a single transistor. However, some of the compact MOSFET models do not comply with the requirements of symmetry and transistor equivalence. This paper reports tests of symmetry and of series association of transistors of some compact models available in circuit simulators. We show that the ACM2, a chargebased model in which the terminal voltages are referred to the substrate, is fully compliant with the transistor symmetry, but that some popular models are not. To test the symmetry property, we show examples of transistor current-voltage characteristics and derivatives up to the fifth order, and capacitance-voltage characteristics, all tests around  VDS=0 . A MOSFET binary current divider is employed to test the consistency of the model applied to a series association of transistors.

[paper] ATMAD: Compact Modeling with Parameter Extraction

Yuhang Zhang, Qing Zhang, Yang Shen, Bingyi Ye, Xiaojin Li, Yabin Sun, Yanling Shi, Yong‑Fu Li

ATMAD: Agile Transistor Compact Modeling with Parameter Extraction 

Based on Automatic Differentiation

ACM 1084-4309/2026/04-ART103

DOI: 10.1145/3797484

1. School of Integrated Circuits, East China Normal University, Shanghai, China
2. Department of Micro‑Nano Electronics, Shanghai Jiao Tong University, Shanghai, China
3. East China Normal University, Shanghai, China
4. Shanghai Jiao Tong University, Shanghai, China

Abstract: Compact models of transistors are essential for simulating and optimizing circuits with the use of SPICE simulation tool. Parameter extraction, which is calibrating these models, is essential to ensure their alignment with measured or simulated data. However, conventional parameter extraction methods are generally iterative and experience-dependent, requiring significant time and effort from modeling engineers. Moreover, as semiconductor devices and compact models become increasingly advanced, the need for a tailored extraction process for each model has become increasingly inefficient. To address the above challenges, this work proposes an agile transistor compact modeling framework, ATMAD. The proposed framework takes a compact model file and a set of electrical characteristic data as inputs, producing a calibrated model with minimal human intervention. ATMAD automatically retrieves the equations in the compact model and converts them into computational flow graphs, thus supporting different compact models with a generalized process. A graph unlooping technique is proposed to support automatic differentiation for compact models with implicit functions (e.g., series resistance and surface potential solving). Based on the computational flow graph, ATMAD adopts automatic differentiation technique to achieve automatic and parallel optimization of model parameters. The proposed ATMAD framework is validated on commonly-used compact models in academia and industry, showing its effectiveness for compact modeling for both 𝐼𝑉 and 𝐶𝑉 characteristics.

Fig. The overall flow of ATMAD framework

Acknowledgements: This work is supported in part by the Shanghai Explorer Program under Grant No. 25TS1410300 and 24TS1400200 and in part by the National Natural Science Foundation of China under Grants No. 62304133 and 62350610271.

[paper] CrOx/TiOy Memristive Devices

Phu-Quan Pham1,2, Ngoc-Lam Le Pham3,4, Thuy-Anh Tran1,2, Van-Son Dang4, Quang Nguyen2,5, Ngoc Kim Pham1,2, Thuat Tran Nguyen3,4

On-Pinched Hysteresis in CrOx/TiOy-based Memristive Devices: Modeling and Analysis

Appl. Phys. Lett. 128, 153502 (2026)

DOI: 10.1063/5.0332014

1 Faculty of Materials Science and Technology, University of Science, Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 72754, Vietnam
2 Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 71309, Vietnam
3 Semiconductor and Advanced Materials Institute, Technology and Innovation Park, Vietnam National University – Hanoi, Hoa Lac, Hanoi, 13151, Vietnam.
4 Faculty of Physics, University of Science, Vietnam National University – Hanoi, 334 Nguyen Trai, Thanh Xuan, Hanoi, 11406, Vietnam
5 Department of Physics, International University, Vietnam National University – Ho Chi Minh City, Ho Chi Minh City, 71309, Vietnam

Abstract: Transition-metal oxide memristors are promising for neuromorphic computing, yet most SPICE models overlook material-specific effects such as oxygen stoichiometry and non-pinched hysteresis. Here, we systematically study CrOx/TiOy memristors fabricated under controlled oxygen concentrations (10%–50%) and propose an improved SPICE-compatible model. The devices exhibit oxygen-dependent resistive switching, retention, and pulse-driven plasticity, with optimal performance at 40% oxygen. Our model explicitly reproduces the non-pinched hysteresis observed in I–V curves, consistent with behaviors such as ion immigration, charge trapping, and remnant polarization, and achieves close agreement with experiments across multiple stoichiometries. Validation includes endurance, retention, and synaptic functions such as long-term potentiation/depression and spike-number/amplitude-dependent plasticity. Finally, the model is extended from single devices to a 4 × 4 crossbar array, demonstrating its scalability for artificial neural network simulations. These results emphasize the critical role of oxygen stoichiometry in CrOx/TiOy memristors and introduce a modeling framework that bridges experimental device physics with circuit-level neuromorphic applications.

Fig. a. Fabricated single cell memristor devic and b. 4×4 crossbar array

[paper] Thermal Management SiGe HBT in ICs

Boulgheb, Abdelaaziz

"Enhanced thermal management of SiGe HBT integrated circuits 

using the Peltier effect and DBC metal tracks"

Microelectronics Reliability 174 (2025): 115896

DOI: 10.1016/j.microrel.2025.115896

1 Department of Electronics, University of Sciences and Technology Houari Boumediene, Bab Ezzouar 16111, Algeria.
2 Hyperfrequencies and Semiconductors Laboratory, Department of Electronics, Faculty of Sciences and Technology, University of Frères Mentouri Constantine 1, PO Box 25017, Constantine, Algeria.

Abstract: Effective thermal management remains a major challenge for SiGe heterojunction bipolar transistor (HBT) integrated circuits, particularly in BiCMOS9MW 0.13µm technology. This study proposes a novel two-stage heat dissipation strategy that combines active thermoelectric cooling with passive DBC-based conduction an approach not previously explored in this context to address this issue. First, the Peltier effect is leveraged in combination with conventional plastic packaging to regulate circuit thermal performance. Second, Direct Bonded Copper (DBC) metal tracks are implemented to establish an efficient thermal pathway between the internal circuit and external heat sinks. Experimental results indicate that standard plastic packaging alone results in excessive heating (Tmax = 467 K). The incorporation of the Peltier effect significantly reduces the peak temperature to 380 K, while the addition of DBC tracks further enhances cooling, lowering the temperature to 340 K. Unlike traditional cooling solutions that rely solely on packaging or external heatsinks, our method enables localized, controllable heat extraction directly at the chip level, ensuring better thermal regulation and improved electrical performance. This dual approach not only mitigates self-heating but also leads to notable improvements in DC and RF performance. Specifically, the maximum current gain (βmax) increases from 1913 to 2183, and the transit frequency (ft) rises from 265 GHz to 285.6 GHz. These findings underscore the effectiveness of the combined Peltier-based cooling and DBC thermal management in enabling next-generation high-frequency applications.

Fig. a) SiGe HBT device structure simulated with COMSOL, showing the log of electron and hole concentrations. b) SEM cross-sectional view of the SiGe HBT.

Lin Fujian Optoelectronic Device Modeling Laboratory

Yangtze River Delta Integrated Circuit Industrial Application Technology Innovation Center

Jiangsu Jicui Integrated Circuit Application Technology Innovation Center

Lin Fujian Optoelectronic Device Modeling Laboratory

Optoelectronic Device Modeling Laboratory Services

• SPICE model development, characterization, and parameter extraction for silicon photonic waveguides and micro modulators and optical splitters/combiners
• Compact modeling, characterization, and parameter extraction for other advanced photonic devices
• GaN device characterization, EEHemt, ASM model and Angelov models
• InP‑HEMT device characterization, EEHemt model
• SiGe HBT device characterization, SPG/VBIC/HICUM model
• Characterization of micro‑/nano‑devices, internal/external parameter consistency studies, and high‑quality enhancement of existing models
• Ultra‑wideband SPICE models for electrical interconnects, packaging, and passive components
• Modeling of 1/f noise, noise parameters, avalanche effects, self‑heating, channel temperature, and related physical effects
• CNAS‑certified testing and final acceptance testing for major projects
• Other practical modeling services based on customer requirements

Laboratory Contact Information

联系人：小葛，18334212431，邮箱：gemy@jitric.cn

地址：无锡市锡山区凤威路与春江东路交叉口，长三角工业芯谷 A 栋 4 楼

定位：轻资产、高专业、全流程建模验证平台

合作模式：仪器有偿使用、可靠提参、技术赋能

[MEAD] Low-Power Analog IC Design

MEAD Education

June 22-26, 2026

Registration deadline: May 22, 2026

Payment deadline: June 12, 2026

MONDAY, June 22
8:30-12:00 am	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 23
8:30-10:00 am	Noise Performance of Elementary Circuits	Boris Murmann
10:30-12:00 am	Noise Performance of Filters, Feedback & SC Circuits	Boris Murmann
1:30-3:00 pm	Opamp Topologies and Design: Single-Stage Circuits	Boris Murmann
3:30-5:00 pm	Opamp Topologies: Cascoded and Two-Stage Circuits	Boris Murmann

[Read more and REGISTER]

[OpenSUSI] Kicks off Five-Year Plan

Industry-Academia Collaboration Project Launches for Real Chip Manufacturing 

Using NDA-Free PDK - Tokai Rika, Kyushu University, AIST Solutions, 

OpenSUSI Kicks Off Five-Year Plan for FY2026

Tokai Rika Co., Ltd., Kyushu University, AIST Solutions Co., Ltd., and OpenSUSI have announced a joint project on a five-year plan to develop semiconductor human resources and verify their implementation through industry-academia collaboration to actually manufacture chips using PDK (Process Design Kit) that does not rely on NDAs (non-disclosure agreements). The 2026 launch ceremony was held. The biggest feature of this project is that it allows students to experience a series of processes from design to chip manufacturing under an open design environment using NDA-free PDKs #OpenPDKs

Positioning and future development in FY2026 as the first year that this project will be fully developed over a five-year span. Based on an open design and manufacturing environment utilizing NDA-free PDK #OpenPDK, we will continue and develop the following initiatives:

• Continuation and advancement of hands-on semiconductor human resource development
• Providing opportunities for actual chip manufacturing and verification using NDA-free PDK
• Building a practical and highly reproducible education and implementation model through industry-academia integration
• In exchange for the cost support for this program, we will embed the company's logo on the prototype chip to spread awareness of semiconductor design human resource development as a social contribution activity

(From left) Junichi Okamura, Representative Director of OpenSUSI, 

Haruichi Kanaya, Professor of Kyushu University, 

Taketoshi Sakurai, Executive Officer of Tokai Rika, 

and Seiji Osaka, President and CEO of AIST Solutions

If you are interested or interested in this matter, please contact us at:

OpenSUSI Secretariat <secretary@opensusi.org>

 

[papers] Compact/SPICE Modeling

Sun, Jing, Daquan Liu, Hang Li, Wensheng Qian, Jiye Yang, Yabin Sun, Bingyi Ye, Yuhang Zhang, Yang Shen, and Xiaojin Li. "A physics-based and accurate STI-LDMOS compact subcircuit model with modified drift region resistance and gate-drain capacitance." 

Semiconductor Science and Technology (2026).

Abstract: This paper develops a physics-based and accurate shallow trench isolation lateral double-diffused MOS (STI-LDMOS) compact subcircuit model. In the proposed direct-current (DC) model, the drift-region resistances beneath both the STI region and the drain electrode are incorporated, thereby significantly improving its physical fidelity and predictive accuracy of the DC characteristics. For the proposed alternating-current model, the gate–drain capacitance model is decomposed into two components: a gate–drift-region overlap charge model with modified bias dependence derived from BSIM4.5, and a parallel-plate capacitance model for the gate–STI overlap region. In addition, the gate–source capacitance and drain–source charge models are further extended to match the physical structure and to more accurately capture the dynamic characteristics of an STI-LDMOS device. The model parameters are extracted and calibrated, and the proposed subcircuit model is implemented in Verilog-A. Excellent agreement is achieved between the proposed model and both the technology computer-aided design (TCAD) simulation results and the measured data from a 40 V STI-LDMOS device, demonstrating its accuracy and efficiency for circuit-level simulation of STI-LDMOS devices.

Nakos, Miltiadis Κ., Theodoros Α. Oproglidis, Dimitrios Η. Tassis, Constantinos Τ. Angelis, Charalabos Α. Dimitriadis, and Andreas Tsormpatzoglou. "Symmetric physics-based compact core model for double-gate junctionless transistors with ungated extensions." (2026).

Abstract: This work presents a physics-based compact model for double-gate junctionless field-effect transistors, with emphasis on accurately capturing the impact of ungated source/drain extensions on the drain current characteristics. The model is validated against two-dimensional device simulations performed using Silvaco ATLAS for two channel doping concentrations and a wide range of ungated extension lengths. To isolate the contribution of the access regions and clarify the effective channel length, all mobility degradation models were disabled in the simulations, allowing the observed current degradation to be attributed solely to the series resistance of the ungated extensions. The proposed formulation includes an analytical factor ξ that accounts for the reduced electrostatic influence of the source and drain terminals on the channel potential, as well as a closed-form expression for the fringe capacitance associated with the ungated regions. The resulting drain current model demonstrates very good agreement with numerical simulations across different geometries and doping levels. Model symmetry is further verified through a Gummel symmetry test, confirming the physical consistency of the formulation. Owing to its analytical nature and physical transparency, the proposed model is well suited to serve as a core building block for higher-level compact models of JL devices.

Y. Liu, L. Tian, Y. Niu, Y. Xia and W. Chen, "A SPICE-Compatible High-Efficiency Equivalent Mechanical Circuit Method for Electro-Thermal-Mechanical Coupling Simulation," in IEEE Transactions on Electron Devices

doi: 10.1109/TED.2026.3671249.

Abstract: Accurate and efficient modeling and simulation of electro-thermal-mechanical field coupling is essential for evaluating multiphysics effects on devices/circuits’ performance and reliability, as the multiphysics coupling effects become severe in advanced integrated circuits. In our previous work, we developed the equivalent mechanical circuit (EMC) method, thereby constructing a SPICE-compatible equivalent multiphysics circuit framework to simulate electro-thermal-mechanical coupling processes in advanced integrated circuits. However, the computational efficiency of the previous EMC (pEMC) method remains limited compared with the finite element method (FEM), since the pEMC method requires multiple iterations to simulate thermal expansion, even in linear equation systems. In this article, we develop a novel EMC method by proposing voltage-controlled current sources (VCCSs) into the pEMC. Therefore, the novel EMC method can simulate thermal expansion without iteration in linear equation systems. The results demonstrate that the computational efficiency of the novel EMC method achieves a tenfold improvement compared to the pEMC method and exhibits computational efficiency comparable to the FEM under the same number of nodes.

F. Yu et al., "Precise Surface Potential Modeling for Compact DC Models of a-IGZO Thin Film Transistors," in IEEE Transactions on Electron Devices, 

doi: 10.1109/TED.2026.3671772.

Abstract: Many thin film transistor (TFT) models that consider the free and trapped charges, including models for amorphous InGaZnO (a-IGZO) TFTs, rely on the accurate determination of surface potential. In this work, a physically-based initial solution and fast-converging iterative procedure with logarithmic increment are utilized for the precise determination of the surface potential model in TFTs with channels of noncrystalline semiconductors, which have exponentially distributed tails and deep traps in the semiconductors. In particular, the surface potential model does not use special functions, such as the Lambert W function. The precision of the proposed scheme of analytical model and iterative procedure is verified against reference simulations of surface potential, and against measured current–voltage DC characteristics of a-IGZO TFTs, employing a well-established surface-potential-based charge sheet model. The precision of the iterative procedure is in the range of few nV, converging approximately for less than half of the number of iterations of other schemes for the calculation of the surface potential. Accordingly, the proposed analytical model for surface potential and the iterative scheme for the determination of the values of the surface potential are suitable for implementation in TFTs’ circuit simulators.

K. Ohmori and S. Amakawa, "Variable-Temperature Broadband Noise Characterization of MOSFETs for Cryogenic Electronics: From Room Temperature down to 3 K," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, 

doi: 10.1109/EDTM55494.2023.10103124.

Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3 K and 300 K. Using the system, wideband noise spectroscopy (WBNS) from 20 kHz to 500 MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3 K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.

Jeong, Junhwa, Ilho Myeong, and Ickhyun Song. "Impact of MOSFET source/drain resistance on channel thermal noise calculation and noise performance." 

Results in Physics (2026): 108634.

Abstract: For sub-micron metal oxide semiconductor field effect transistors (MOSFETs), parasitic series source/drain resistance has a significant impact on channel thermal noise (Sid) and noise parameters. In this work, we propose an improved analytical channel thermal noise model considering parasitic resistance, based on physical thermal noise models of sub-micron intrinsic MOSFETs. To validate the proposed model, measurements were performed at room temperature (25°C) on nMOSFETs fabricated in a commercial 130-nm (0.13-µm) bulk RF CMOS technology. All RF S-parameter and noise measurements were conducted on-wafer at room temperature, with open/short de-embedding applied to accurately remove pads and interconnect parasitics. The model was calibrated by extracting parameters in a spice with the standard BSIM4 model as a baseline and validated against measured data such as Sid, Rn, NFmin, Gopt, and Bopt. Furthermore, the proposed model is extended to a circuit-level analysis by deriving the noise figure of a high-frequency amplifier (HFA) using Cadence Virtuoso (Spectre). A good agreement between the measurement and the developed model is observed, particularly under high gate bias (Vgs) conditions where the potential drop at the parasitic resistance becomes apparent. The analysis demonstrates that accurate modeling of parasitic resistance is essential for predicting the accurate noise figure of the HFA in high-current regimes. The improved model predicts the thermal noise of both the extrinsic MOS device and the HFA circuit well, thereby supporting accurate noise simulations for high-frequency circuits that operate under a wide range of gate bias conditions.

Fig. (a) 3D image of LDD MOSFET (b) equivalent circuits of (a) where

Rlds + Rss = RS and Rldd + Rdd = RD (c) equivalent circuit of intrinsic MOSFET.

[DATE2026] Open Source Related Talks

DATE 2026 Verona, Italy

Open Source Related Talks

Monday, 20 April - Wednesday, 22 April 2026

<https://date26.date-conference.com/programme>

Label	Title	Authors
TS02.8	ML-DSA-OSH: An Efficient, Open-Source Hardware Implementation of ML-DSA	Quinten Norga; Suparna Kundu; Ingrid Verbauwhede
LK03	Democratizing Silicon: The Rise of Open-Source EDA and Europe’s Strategic Roadmap	Luca Benini
TS10.1	PICOSNN: Partially Incoherent Configurable Optical Computing Architecture for SNN Acceleration	Bowen Duan; Zhenhua Zhu; Zhengyang Duan; Huazhong Yang; Yuan Xie; Yu Wang
TS16.1	Non-Volatile Spintronic Flip-Flops with Checkpoint Preservation Supported in RISC-V Platform	Jiongzhe Su; Mingtao Chen; Zhanpeng Qiu; Bo Liu; Hao Cai
LBR01.4	Float Fight - Verifying Floating-Point Behavior In Risc-V Simulators	Katharina Ruep, Manfred Schlaegl and Daniel Grosse
LBR01.7	Hybrid Virtual Platform + FPGA Co-Emulation Framework	Lorenzo Ruotolo; Giovanni Pollo; Mohamed Amine Hamdi; Matteo Risso; Yukai Chen; Enrico Macii; Massimo Poncino; Sara Vinco; Alessio Burrello; Daniele Jahier Pagliari
TS20.1	Fault-Tolerance Mapping of Spiking Neural Networks to RRAM-Based Neuromorphic Hardware	Yuqing Xiong; Chao Xiao; Zhijie Yang; Lei Wang; Mengying Zhao
TS21.4	Substrate: A Statically Typed Framework for Designing Highly Configurable Analog and Mixed-Signal Circuit Generators	Rahul Kumar; Rohan Kumar; Borivoje Nikolic
SD03	Open-Source Hardware Landscape
SD03.1	Open Silicon Fabrication – Made in Europe	Gerhard Kahmen, IHP GmbH, DE
SD03.2	From Schematic To Silicon: Mixed Signal Ic Design In Open Source Flows	Harald Pretl, JKU Linz, AT
SD03.3	Bringing Software Design Thinking To Chip Design	Tomi Rantakari, ChipFlow, GB

[paper] Memristors SPICE Compact Modeling

Thomas Günkel1,2, Aleix Barrera1, Lluís Balcells1, Narcís Mestres1, 

Enrique Miranda2, Anna Palau1, Jordi Suñé2

SPICE-Compatible Compact Modeling of Cuprate-Based Memristors Across

a Wide Temperature Range 

Advanced Electronic Materials (2026): e00861

DOI: https://doi.org/10.1002/aelm.202500861

1 Institut de Ciència de Materials de Barcelona, ICMAB-CSIC, Bellaterra (SP)
2 Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (SP)

ABSTRACT: Cryogenic memristors based on the high-temperature superconductor YBa2 CuO7−δ offer significant potential as nonvolatile memory elements or unit cell for analog artificial neural networks for future applications such as control units for quantum processors, cryogenic data centers or space-related electronics. In this work, the experimental switching capabilities of cuprate-based memristors are analyzed in terms of the material-specific physics. This work investigates the experimental switching behavior of cuprate-based memristors across temperatures from cryogenic to room temperature. The underlying interpretation, namely the trapping of injected charge carriers at a metal interface and field-induced detrapping, is incorporated into a physically inspired compact model. The core equations of this model consist of a differential balance equation and a current equation, which is derived from space-charge limited conduction. Comparison with experimental data shows that the model successfully reproduces the key features of the measured switching behavior across a wide temperature range, spanning from 80 to 300 K. Additionally, we implement the model in SPICE, enabling circuit-level simulations. The resulting compact model provides a useful framework for guiding experimental studies, capturing key features of the switching behavior, and bridging the gap between device-levelcharacterization and circuit-level design.

FIG: LTspice Simulations: (a) Implementation of the compact model into a LTspice schematic. The diagram is explained in more detail in the main text. Simulation results of the hysteron V(r) and the 𝐼𝑉 -characteristics abs(I(B2)) depending on the input signal V(v) are given for a simple sinusoidal input signal in (b) and a damped waveform in (c).

 

Acknowledgments: The authors acknowledge financial support from the Spanish Ministry of Science and Innovation MCIN/ AEI /10.13039/501100011033/ through CHIST-ERA PCI2021-122028-2A co-financed by the European Union Next Generation EU/PRTR, the “Severo Ochoa” Programme for Centres of Excellence CEX2023-001263-S, HTSUPERFUN PID2021-124680OB-I00,and HTS-4ICT PID2024-156025OB-I00, co-financed by ERDF A way of making Europe. The Spanish Nanolito networking project (RED2022-134096-T). The European COST Action SUPERQUMAP (CA 21144). EMand JS would like to thank the support the Spanish Ministerio deCiencia e Innovación (MCIN) / Agencia Española de investigación (AEI)10.13039/501100011 033 (Under project No. PID2022-139586NB-C41). TG acknowledge support from AGAUR Catalan Government Predoctoral Fellowship (2022 FISDU 00115). J.S. and E. M. acknowledge the support of the EU through the HORIZON Chips-JU 101194172 NeAIxt Project and the Agencia Española de Investigación (AEI)/10.13039/501100011033 under Project PCI2025-163216. The authors acknowledge the Scientific Servicesat ICMAB and the UAB PhD program in Materials Science.

[GitHub] Heat Map of Developers in Africa

Commonwealth Report "Open Source Africa" 

by OpenUK

The heatmap illustrates the distribution of developers with GitHub accounts across Africa. It shows that accounts are dispersed in multiple regions throughout the continent. Among the countries highlighted in the OpenUK report, Nigeria has the largest number of users with approximately 1.8 million accounts, followed by Kenya with 666,020 accounts and Rwanda with 85,978 accounts.
[Read More] in recent Commonwealth Report "Open Source Africa" by OpenUK

[paper] ULTRARAM Neuromorphic Memory Device

Abhishek Kumar, Peter D. Hodgson, Manus Hayne, and Avirup Dasgupta

Artificial synapse based on ULTRARAM memory device for neuromorphic applications

Journal of Applied Physics 139, no. 12 (2026)

DOI: 10.1063/5.0314826

1. Department of Electrical Engineering and Computer Sciences, UCB (USA)

2. Department of Physics, Lancaster University, Lancaster LA1 4YB (UK)

3. Quinas Technology Limited, Lancaster LA1 4YB, (UK)

4. Department of Electronics and Communication Engineering, IIT Roorkee (IN)

Abstract: The memory demands of large-scale deep neural networks (DNNs) require synaptic weight values to be stored and updated in off-chip memory, such as dynamic random-access memory, which reduces energy efficiency and increases training time. Monolithic crossbar or pseudo-crossbar arrays using analog non-volatile memories, which can store and update weights on-chip, present an opportunity to efficiently accelerate DNN training. In this article, we present on-chip training and inference of a neural network using an ULTRARAM memory device-based synaptic array and complementary metal–oxide–semiconductor (CMOS) peripheral circuits. ULTRARAM is a promising emerging memory exhibiting high endurance (⁠> 10E7P/E cycles), ultrahigh retention (⁠>1000 years), and ultralow switching energy per unit area. A physics-based compact model of ULTRARAM memory device has been proposed to capture the real-time trapping/de-trapping of charges in the floating gate and utilized for the synapse simulations. A circuit-level macro-model is employed to evaluate and benchmark the on-chip learning performance in terms of area, latency, energy, and accuracy of an ULTRARAM synaptic core. In comparison with CMOS-based design, it demonstrates an overall improvement in area and energy by 1.8x and 1.52x⁠, respectively, with 91% of training accuracy.

FIG: Schematic of an ULTRARAM memory cell and the corresponding transmission electron microscope image of the device’s epilayers

Acknowledgments: This work was supported in part by the Quinas Technology Limited, Lancaster, United Kingdom; Indian Institute of Technology Roorkee, India; and Prime Minister’s Research Fellowship, Ministry of Education, Government of India under Grant No. PM-31-22-773-414.

Data Availability: The data that support the findings of this study are available within the article.

[github] NVC: VHDL compiler and simulator

 

https://cameron-eda.com/

NVC is a VHDL compiler and simulator

https://github.com/kev-cam/nvc

NVC supports almost all of VHDL-2008 with the exception of PSL, and it has been successfully used to simulate several real-world designs. Experimental support for Verilog and VHDL-2019 is under development. NVC has a particular emphasis on simulation performance and uses LLVM to compile VHDL to native machine code. NVC is not a synthesizer. That is, it does not output something that could be used to program an FPGA or ASIC. It implements only the simulation behaviour of the language as described by the IEEE 1076 standard. NVC supports popular verification frameworks including OSVVM, UVVM, VUnit and cocotb. See below for installation instructions.

Vendor Libraries

NVC provides scripts to compile popular verification frameworks and the simulation libraries of common FPGA vendors

• For OSVVM use nvc --install osvvm
• For UVVM use nvc --install uvvm
• For Xilinx ISE use nvc --install ise
• For Xilinx Vivado use nvc --install vivado and additionally nvc --install xpm_vhdl
  if you require simulation models of the XPM macros
• For Altera Quartus use nvc --install quartus
• For Lattice iCEcube2 use nvc --install icecube2
• For Free Model Foundry common packages use nvc --install fmf

[Open Source Survey] From RTL to Fabrication

Emilio Isaac Baungarten-Leon

From RTL to Fabrication: Survey of Open-Source EDA Tools and PDKs

Electronics 2026, 15(5), 1048;

DOI: 10.3390/electronics15051048

* Departamento de Electromecánica, Universidad Autónoma de Guadalajara, Zapopan 45129, Mexico

Abstract: This article aims to synthesize the current ecosystem of open-source tools for Integrated Circuit (IC) design, covering the entire digital design flow from Register-Transfer Level (RTL) description to fabricable layouts. The survey categorizes and analyzes tools across major stages of design, including code-generation tools, logic synthesis, simulation, and physical design flow. Special emphasis is given to the fabricable open-source Process Design Kit (PDK), which enables the physical realization of open-hardware projects. By examining interoperability, limitations, and maturity across this toolchain, the article provides a comprehensive overview of the Electronic Design Automation (EDA) landscape and identifies the research and educational opportunities that arise from democratizing silicon design through open and reproducible workflows.

Fig: (a) IC design flow illustrating the complete process from RTL specification through logic synthesis, physical design (floorplanning, placement, clock tree synthesis, routing), verification, and final GDSII generation for fabrication. (b) FPGA design flow showing the progression from RTL description to synthesis, technology mapping, placement-and-routing on the target FPGA fabric, bitstream generation, and device configuration.

Acknowledgments: The APC was funded by Universidad Autónoma de Guadalajara (UAG), financial support provided through its Fondo Semilla. The author gratefully acknowledges the Universidad Autónoma de Guadalajara (UAG) for the financial support provided through its Fondo Semilla program, which covered the article processing charges and enabled the publication of this work. During the preparation of this manuscript, the authors utilized GPT-5.2 solely to enhance the clarity, grammar, and overall quality of the English text. The author reviewed and edited all AI-assisted content and takes full responsibility for the accuracy, originality, and integrity of the final manuscript.

Table A1. Main open-source EDA tools and their official repositories

Category	Tool	Official Link
Code-Generation Tools	PandA Bambu HLS	https://github.com/ferrandi/PandA-bambu (accessed on 20 January 2026)
	Kiwi Compiler	https://www.cl.cam.ac.uk/~djg11/kiwi/ (accessed on 20 January 2026)
	LegUp HLS	https://github.com/LegUpComputing/legup-examples?tab=readme-ov-file (accessed on 20 January 2026)
	ROCCC	http://roccc.cs.ucr.edu/ (accessed on 20 January 2026)
	PyMTL3	https://github.com/pymtl/pymtl3 (accessed on 20 January 2026)
	Chisel	https://www.chisel-lang.org/ (accessed on 20 January 2026)
	SpinalHDL	https://github.com/SpinalHDL/SpinalHDL (accessed on 20 January 2026)
	Pyverilog	https://github.com/PyHDI/Pyverilog (accessed on 20 January 2026)
	Amaranth HDL	https://github.com/amaranth-lang (accessed on 20 January 2026)
LLM-Based Code Generation	RTLCoder	https://github.com/hkust-zhiyao/RTL-Coder (accessed on 20 January 2026)
	Spec2RTL-Agent	https://cirkitly.kernex.sbs/ (accessed on 20 January 2026)
	OriGen	https://github.com/pku-liang/OriGen (accessed on 20 January 2026)
	AutoChip	https://github.com/shailja-thakur/AutoChip (accessed on 20 January 2026)
	CodeV	https://github.com/cluesmith/codev (accessed on 20 January 2026)
	VeriCoder	https://github.com/Anjiang-Wei/VeriCoder (accessed on 20 January 2026)
	StarCoder	https://github.com/bigcode-project/starcoder (accessed on 20 January 2026)
	CodeLlama	https://github.com/meta-llama/codellama (accessed on 20 January 2026)
	DeepSeek-Coder	https://github.com/deepseek-ai/DeepSeek-Coder (accessed on 20 January 2026)
	CodeQwen	https://github.com/QwenLM/qwen-code (accessed on 20 January 2026)
	Gemini	https://gemini.google.com/ (accessed on 20 January 2026)
	GPT	https://chatgpt.com/ (accessed on 20 January 2026)
	ChatEDA	https://github.com/wuhy68/ChatEDA (accessed on 20 January 2026)
Synthesis Tools	Yosys	https://yosyshq.net/yosys/ (accessed on 20 January 2026)
	ABC (Berkeley)	https://people.eecs.berkeley.edu/~alanmi/abc/ (accessed on 20 January 2026)
	ODIN II (VTR)	https://docs.verilogtorouting.org/en/latest/odin/ (accessed on 20 January 2026)
	GHDL-Yosys Plugin	https://github.com/YosysHQ/yosys (accessed on 20 January 2026)
	Synlig	https://github.com/chipsalliance/synlig (accessed on 20 January 2026)
	Mockturtle (EPFL)	https://github.com/lsils/mockturtle (accessed on 20 January 2026)
Simulation & Verification Tools	Verilator	https://www.veripool.org/verilator/ (accessed on 20 January 2026)
	Icarus Verilog	https://steveicarus.github.io/iverilog/ (accessed on 20 January 2026)
	cocotb	https://www.cocotb.org/ (accessed on 20 January 2026)
	GTKWave	https://gtkwave.sourceforge.net/ (accessed on 20 January 2026)
	Yosys-SMTBMC	https://symbiyosys.readthedocs.io/en/latest/reference.html (accessed on 20 January 2026)
	EQY	https://github.com/YosysHQ/eqy (accessed on 20 January 2026)
	CoSA	https://github.com/cristian-mattarei/CoSA (accessed on 20 January 2026)
	OpenSTA	https://github.com/The-OpenROAD-Project/OpenSTA (accessed on 20 January 2026)
	OpenTimer	https://github.com/OpenTimer/OpenTimer (accessed on 20 January 2026)
	Tatum (VTR)	https://github.com/verilog-to-routing/tatum (accessed on 20 January 2026)
Physical Design Flow Tools	OpenROAD	https://theopenroadproject.org/ (accessed on 20 January 2026)
	OpenLane	https://github.com/The-OpenROAD-Project/OpenLane (accessed on 20 January 2026)
	iEDA	https://github.com/OSCC-Project/iEDA (accessed on 20 January 2026)
	SiliconComp	https://github.com/siliconcompiler/siliconcompiler (accessed on 20 January 2026)
Fabricable PDKs	SKY130	https://github.com/gdsfactory/skywater130 (accessed on 20 January 2026)
	GF180MCU	https://github.com/google/gf180mcu-pdk (accessed on 20 January 2026)
	IHP SG13G2	https://github.com/IHP-GmbH/IHP-Open-PDK (accessed on 20 January 2026)
	ICsprout55	https://github.com/openecos-projects/icsprout55-pdk (accessed on 20 January 2026)

[DATE2026 Panel] Empowering Education through Open-Source Hardware

 #SavetheDate | On April 22, 2026, at 11:00 Norbert Wehn and Lukas Krupp from the RPTU Kaiserslautern-Landau will host a special session at the DATE Conference 2026 in Verona, Italy: “Empowering Education through Open-Source Hardware”.

The session focuses on how open design ecosystems can make chip development more accessible, from first hands-on experiences to full design flows from system level to GDSII. Topics include:

• open-source hardware in education
• hands-on chip design across the full stack
• broader access to PDKs, IP, and EDA tools

Panelists:

• Luca Benini (ETH Zürich)
• Luca Carloni (Columbia University)
• Oscar Gustafsson (Linköping University)
• Patrick Haspel, PhD (Synopsys Inc)
• Prof. Dr.-Ing. Gerhard Kahmen (IHP – Leibniz Institute for High Performance Microelectronics)
• Matt Venn (Tiny Tapeout)

Save the date and learn more about our upcoming stops and events here: 

https://lnkd.in/dgGbnJgn

26th Workshop Analog Circuits

26th Workshop Analog Circuits 

12.03.2026 and 13.03.2026

at Leibniz University Hannover

The workshop series offers a platform to present one's own ideas and discuss results with science and industry. The focus is on integrated analog and mixed-signal circuits.

The workshop will take place on 12.03.2026 and 13.03.2026 in the Royal Horse Stable of the University of Hannover.  Registration - Participation in the workshop is free of charge.

The programme will be compiled after the call for papers has been completed and is avalable online 

In the run-up to the 26th Workshop on Analog Circuits, the DE:Sign cooperation event on the topic of "Open Source Tools for Analog Design" will take place on the morning of 12.03.2026. In this event, the funded projects will present their current status on open design tools and methods for analogue design. Participants will receive an overview of the contribution of the respective projects to the development of technology open, accessible, and sustainable design chains in the sense of the DE:Sign guideline.

If you have any questions, please contact the organizers by e-mail at: analog2026@ims.uni-hannover.de

Aalto Microelectronics Fair

Aalto Microelectronics Fair

March 20, 2026, 9.00-15.30

Aalto Yliopisto, Kandidaattikeskus, H304, Otakaari 1, 02150 Espoo

Time	Session
8:30–9:00	Morning coffee
9:00–9:15	Opening Aleksi Korsman
	Keynotes
9:15–10:00	Keynote 1: “OpenPDK - Global Scholar Platform”, Wladek Grabinski, Open PDK Initiative
10:05–10:50	Keynote 2: “Open Source Design Tools in SME IC Design Companies”, Ari Paasio, Kovilta
	Research overviews
11:00–11:15	Research overview: Kari Stadius
11:15–11:30	Research overview: Prof. Marko Kosunen
11:30–11:45	Research overview: Prof. Kwantae Kim
11:45–12:45	Lunch (and posters)
12:45–13:15	Student talk: “Five years of RISC‑V processor design at Aalto”, Aleksi Korsman
13:15–13:45	Student talk: “Beyond Neural Networks: Overcoming the Symbolic Bottleneck via Approximate Logarithm Acceleration”, Lingyun Yao
	Posters
13:45–14:00	Poster intro
14:00–15:00	Posters with coffee and snacks
15:00–15:30	Feedback and closing

Should you have any questions, please email Marko Kosunen