Sep 29, 2025
[Thesis] Verilog-A MOSFET Model for Analog IC Design
Apr 26, 2025
Heading to San Francisco for ICMC 2025?
The International Compact Modeling Conference (ICMC) is just 2 months away! Be sure to register and secure your room at the Clift Royal Sonesta. Book by May 26 to take advantage of a special discounted rate!
🔗 Register now: https://loom.ly/XmJUtI4
🔗 Reserve your room: https://loom.ly/zyzycVs
hashtag
Jan 11, 2025
[paper] Optoelectronic device library containing multiple Verilog-A models
1 Key Laboratory of Solid-State Optoelectronics Information Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, 100083, China
2 Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing, 100049, China
3 School of Mathematics and Physics, Beijing Key Laboratory for Magneto-Photoelectrical Composite and Interface Science, University of Science and Technology Beijing, Beijing, 100083, China
Dec 9, 2024
[Program Highlights] 17th International MOS-AK Workshop Silicon Valley, December 11, 2024

Oct 28, 2024
[paper] FOSS support for CM with Verilog-A
Feb 28, 2024
[FOSSDEM 2024] Open PDK Initiative
There were two DevRooms to discuss the status and further FOSS CAD/EDA IC design tools developments and open PDK initiative:
- Libre-SOC, FPGA and VLSI DevRoom
- Open Hardware and CAD/CAM DevRoom
Oct 27, 2023
[paper] STT-MTJ Device Model
General-Purpose STT-MTJ Device Model Based on the Fokker-Planck Equation
IEEE Transactions On Nanotechnology, VOL. 22, 2023 659 A
DOI: 10.1109/TNANO.2023.3322468.
Oct 23, 2023
[paper] Lorentzian noise spectra in compact models
* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece
Aug 14, 2023
[11k online viewers] 7th Sino MOS-AK/Nanjing
Aug 10, 2023
[paper] 5-DC-parameter MOSFET model
1 Federal University of Santa Catarina, Florianopolis (BR)
2 STMicroelectronics, Crolles (F)
3 Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, Grenoble (F)
Mar 22, 2023
[analog-wg] Video of March 21 AWG Meeting
The AWG Video Meeting on March 21, 2023 included two presentations:
- Ken Kundert "Why Fund OpenVAF"
- Pascal Kuthe "OpenVAF: An innovative open-source Verilog-A Compiler"
![]() |
![]() |
![]() |
- 4th April: Update from Tim Edwards: Magic and PEX extraction
- 18th April: Update from Sadayuki Yoshitomi: Ecosystem of compact model development
- 2nd May (tentative): Update from C. Enz,EPFL: test structures measurements
Feb 13, 2023
FOSS Verilog-A Models Repository
Dietmar Warning, ngspice team, has announced his new github project VA-Models repository
<https://github.com/dwarning/VA-Models>
Don't hesitate to contact Dietmar Warning, ngspice team, if there is something wrong, especially in kind of legal aspects. All the contributions are welcome.
Jan 30, 2023
[paper] Zener diode compact modeling and simulation
Dec 20, 2022
[OpenVAF] Next-Generation Verilog-A Compiler
Roadmap: OpenVAF is still in development and there many goals we aim to achieve in the longterm:
- Noise analysis (planned for 2023)
- Reaching full compliance with the Verilog-A standard
- Behavioral modelling features
- Support for features that allow defining full circuits/full PDKs in Verilog-A
- OSDI integration in Xyce
- Improved documentation
- A detailed paper about the technical innovations in OpenVAF and attendance at international conferences
Circuit simulators play a critical role in the design of electrical circuits. Accurate simulations enable circuit designers to validate circuit behavior before actual fabrication happens, potentially saving significant re-design costs. The simulation of a circuit critically depends on the so-called compact models and therefore:
- The accuracy of the compact-model equations
- The quality of the model parameters
The complexity of compact models has made the manual integration into simulators a tedious, error-prone and therefore expensive task. One reason for this is that not only the model equations have to be implemented, but also their symbolic derivatives. Numeric derivatives are not an option because they are orders of magnitude slower to compute than analytical derivatives and can introduce convergence problems due to inaccuracies. It is not uncommon - even in commercial tools - to find model implementation bugs or to observe convergence problems that result from incorrectly implemented derivatives. Some simulators with no or limited Verilog-A integration do not implement certain compact-models and can therefore not be used to simulate some processes at all.
Manually implemented compact models may differ between simulators since EDA vendors often rename parameters or alter particular model equations. Due to these simulator specific peculiarities, PDKs can usually only be used by a few specific simulators.
Verilog-A has been developed to address these problems and has become the de-facto standard for developing and distributing compact models. It allows implementing compact models via a simulator independent and standardized language. Verilog-A compilers can translate these models to machine code and allow simulators to use these models without manually implementing them. Verilog-A enables:
- model development and customization by allowing to quickly modify the model equations without having to worry about model implementation details.
- implementing behavioral or data-driven models, or even entire circuits.
- inherent portability between simulators for both models and PDKs that would not be possible with traditional netlist-based formats.
May 17, 2022
[mos-ak] [2nd Announcement and C4P] 4th International MOS-AK/LAEDC Workshop July 3 Puebla (MX)
- Compact Modeling (CM) of the electron devices
- Advances in semiconductor technologies and processing
- Verilog-A language for CM standardization
- New CM techniques and extraction software
- Open Source (FOSS) TCAD/EDA modeling and simulation
- CM of passive, active, sensors and actuators
- Emerging Devices, Organic TFT, CMOS and SOI-based memory
- Microwave, RF device modeling, high voltage device modeling
- Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
- Technology R&D, DFY, DFT and reliability/aging IC designs
- Foundry/Fabless Interface Strategies (eg: Skywater 130nm CMOS)
- Sergio Bampi, UFRGS (BR)
- Juan Brito, IMPINJ (BR)
- Antonio Cerdeira, CINVESTAV (MX)
- Benjamin Iniguez, URV (SP)
- Roberto Murphy, INAOE (MX)
- Jean-Michel Sallese, EPFL (CH)
- Gilson I Wirth, UFRGS (BR)
- Call for Papers: Dec. 2021
- 2nd Announcement: May 2022
- Final Workshop Program: June 2022
- MOS-AK: July 3 2022, Puebla (MX)
- 8:30am - 12:30pm (UTC/GMT -5 hours) MOS-AK Workshop