Jan 27, 2012

Execs gather at SEMI ISS

From Semiconductor Manufacturing and Design:

At SEMI's Industry Strategy Symposium (ISS), Applied Materials CEO Mike Splinter urged creation of a forum for equipment makers to provide input to the Global 450 Consortium (G450C). Splinter said collaboration is needed to tackle the 450mm transition, which could have an R&D t tag of $15-20 billion.

Speaking at ISS, an ASML executive put some hard numbers on the expected performance of the forthcoming commercial EUV tool. The NXE:3300 EUV scanners will start out with throughput rated at 69 wafers an hour, said James Koonmen.

The chip industry's three biggest spenders are bullish. Intel said it will up its capex spending for 2012, with more than a third of the $12.5 billion going into 14nm fab construction in Oregon and Arizona. Intel also promoted a manufacturing executive, Brian Krzanich, to chief operating officer, as part of a wider reorganization.

TSMC chairman Morris Chang said much of the foundry's $7 billion in 2012 capex is going into building new fabs in Taichung and Hsinchu, in preparation for 20nm risk production late next year. Samsung also is spending heavily, with capital expenditures of $29 billion going into making semiconductors and displays for mobile systems. More than a billion dollars is expected to go toward expanding logic IC capacity at its Austin fab.

KLA-Tencor said it has done a grounds-up redesign of its 2900 broadband wafer inspection tool, and upgraded its narrowband and e-beam wafer inspection systems as well.

SemiMD senior editor Mark LaPedus reported "there are more rumors that Micron Technology Inc. will make a bid for debt-ridden Elpida Memory Inc."

Jan 20, 2012

[mos-ak] C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18, 2012

C4P MOS-AK/GSA Workshop at JIIT, Noida (U.P.) India, March 16-18,

Together with the Organizing Committee and Extended MOS-AK/GSA TPC
Committee, we have pleasure to invite to the MOS-AK/GSA Workshop at
JIIT, Noida (U.P.) India, March 16-18, 2012 with the tutorial on CMOS
technology and SPICE Models by Dr. N.D. Arora, Silterra, Malaysia.

List of the international modeling experts contributing to the MOS-AK/
GSA Workshop includes following names (in alphabetic order)
* Nanrian D. Arora, Silterra, Malaysia
* Navakanta Bhat, IISC Bangalore, India
* A.B. Bhattacharyya, JIIT Noida, India
* Mike Brinson, London Metropolitan University, UK
* Amitava Dasgupta, IIT Chennai, India
* Christian Enz, EPFL, Switzerland
* Tamilmani Ethirajan, IBM, India
* Thomas Gneiting, ADMOS, Germany
* Wladek Grabinski, MOS-AK/GSA
* Andre Juge, STM, France
* M. Jagdesh Kumar, IIT Delhi, India
* Shantanu Mahapatra, IISc, India
* Mitiko Miura-Mattausch, Hiroshima University, Japan
* Ramgopal Rao, IIT Mumbai
* Samar Saha, IEEE
* Manoj Saxena, University of Delhi, India
* Ehrenfried Seebacher, AMS, Austria
* Vaidyanathan Subramanian, IBM, India
* Xing Zhou, NTU, Singapore

The terms of participation:
* To register please visit the INAE website <http://inae.org/
> and complete the registration form
* Poster abstract submission with the deadline on Jan. 31, 2012.
Posters' abstract of maximum 300 words and paper of maximum 5 pages in
A4 size double spaced two columns should be submitted to Prof. AB
Bhattacharyya at <inaehq@gmail.com>

Intending participants and authors should also note the following
* Announcement and Call for Papers - Q4 2012
* Poster abstract submission deadline - Jan.31, 2012
* Final Workshop Program - Feb. 2012
* MOS-AK/GSA Workshop - March 16-18, 2012

Further details and updates: <http://www.mos-ak.org/india>
Email contact: <india@mos-ak.org>

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Jan 11, 2012

[mos-ak] MOS-AK/GSA Washington DC on-line publications

MOS-AK/GSA Washington DC workshop on-line publications are available,

I would like to thank all MOS-AK/GSA speakers for sharing their
compact modeling competence, R&D experience and delivering valuable
MOS-AK/GSA presentations. I am sure, that our modeling event in
Washington DC was a beneficial on to all the attendees as well as to
all MOS-AK/GSA Group.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
MOS-AK/GSA India March 16-17, 2012
MOS-AK/GSA Dresden April 26-27, 2012
MIXDES Special Modeling Sesion Warsaw May 24-26, 2012
MOS-AK/GSA Bordeaux Sept.21, 2012
MOS-AK/GSA San Francisco Q4 2012

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EPFL Post-doctoral/ experienced engineer position

Candidate will integrate the Swiss CTI project CAPED for a period of 18 months. This research project aims at developing new technologies based on low power wireless communications, for communication between one intelligent pill implanted in the digestive system and an external control unit. The main industrial partner of this project is the Swiss company Motilis Medica SA. Dr. Catherine Dehollain (RF IC group leader) is the scientific coordinator of this project. 
We are looking for one post-doc/ experienced engineer specialized in low power microelectronic integrated circuits with strong practical experience in the following topics:

  • Design of CMOS low power integrated circuits (analog, mixed-mode and RF blocks) 
  • Design of CMOS low power integrated circuits for energy scavenging (AC to DC converter, voltage regulator, bandgap reference circuit, power-on-reset circuit, etc)
  • Design of CMOS power management circuits 
  • Design of CMOS low power transmitter and receiver (LNA, PLL, VCO, mixer, filters, etc) for wireless communications 
  • Practical experience in the measurements of CMOS integrated circuits EDA tools dedicated to the design of integrated circuits (e.g. Cadence, Agilent ADS, Pspice, etc) 

The RF IC group provides a stimulating environment, good working conditions, and collaborations within a team of 10 researchers and PhD students working on related projects.

  • Starting date: as soon as possible. 
  • Contract duration: 18 months 

Application has to include a CV, copies of the diplomas, significant published or unpublished papers, motivation letter and three letters of reference (or submit 3 reference names). Please send your application at the latest at the end of February 2012 to Dr. Catherine Dehollain

Jan 9, 2012

C4P: 2012 IEEE Silicon Nanoelectronics Workshop

Hilton Hawaiian Village in Honolulu, Hawaii (June 10-11, 2012)
Sponsored by the IEEE Electron Device Society
Authors are encouraged to submit a full-length paper to the IEEE Transactions on Nanotechnology or the IEEE Transactions on Electron Devices. Download the Call for Papers (PDF format) Further Information The 2012 Silicon Nanoelectronics Workshop is a satellite workshop of the 2012 VLSI Symposia sponsored by the IEEE Electron Device Society. It will be held on June 10-11, 2012 at the Hilton Hawaiian Village in Honolulu, Hawaii USA. This will be the seventeenth workshop in the annual series. Original papers on nanometer-scale devices and technologies which utilize silicon or which are based on silicon substrates are welcome. Prospective authors are requested to submit an abstract in PDF format, consisting of one page of text and one page of figures. It must include the paper title, the authors’ names and affiliation(s), and the full contact information (mailing address, phone and FAX numbers, e-mail address) for the corresponding author. Accepted abstracts will be reproduced in the workshop proceedings exactly as received. Some of the accepted papers will be presented in Poster Sessions. The deadline for receipt of abstracts is 5PM (Pacific Time) April 1, 2012. Authors will be notified by April 30, 2012.
Registration forms and hotel reservation forms will be provided in the Advanced Program of the 2012 VLSI Technology Symposium (http://www.vlsisymposium.org/index.html).
•Sub-10 nm transistors, including those employing non-classical structures, novel channel and source/drain materials, or non-thermal injection mechanisms
•Junction and insulator materials and process technology for nanoelectronic devices
•Techniques for fabrication of nanostructures, including nanometer-scale patterning
•Physics of nanoelectronic devices, e.g. quantum effects, non-equilibrium transport
•Modeling/simulation of nanoelectronic devices, e.g. including atomistic effects
•Nanoscale surface, interface, and heterojunction effects in devices
•Device scaling issues including doping fluctuations and atomic granularity
•Circuit design issues and novel circuit architectures, including quantum computing, for nanoelectronic devices
•Optoelectronics using silicon nanostructures
•Techniques targeting zero power electronics (self-supplying), including wireless sensors, energy harvesting, steep slope devices, ultra-low power design and devices
•Devices for heterogeneous integration on silicon, including Graphene, III-V devices, CNT, spin-based devices, MEMs and NEMS, etc.
[read more...]

Jan 3, 2012

Price per transistor on a chip

The price per transistor on a chip has dropped dramatically since Intel was founded in 1968. Some people estimate that the price of a transistor is now about the same as that of one printed newspaper character.

Intel has shipped over 200 million CPUs using high-k/metal-gate transistors – the kind used in 32nm processors -- since the technology was first put into production in November 2007. This translates to over 50,000,000,000,000,000 (50 quadrillion) transistors, or the equivalent of over 7 million transistors for every man, woman and child on earth. [more]

25th ICMTS Conference

SAN DIEGO March 19-22, 2012
Note: This program is subject to change without notice. Final printed version of program will be available at the conference.

Scientific employee, PhD student, or postdoc at TU Dresden

in circuit design 
on organic, flexible, roll-to-roll-printed & plastic-based semiconductor technologies 

The period of employment is governed by the Fixed Term Research Contracts Act (Wissenschaftszeitvertragsgesetz - WissZeitVG). The position is in the frame of the FLEXIBILITY (Flexible Multifunctional Bendable Integrated Light-Weight Ultra-Thin Systems) project funded by the EU involving 7 industry partners and 4 research institutions. PhD students will find excellence prerequisites for an innovative PhD thesis. The first wireless communication receiver fully integrated in a piece of plastic foil (without the need for a silicon chip) will be developed. The project is coordinated by our chair and provides an excellent platform for interdisciplinary cooperation with industry partners. 
Design (analyses, simulation, device modelling, layout, testing and documen-tation) of circuits and systems operating up to radio frequencies in novel OLAE (Organic and Large Area Electronics) and roll-to-toll printed technologies for wireless communications. The authoring of scientific publications and the participation at project meetings and international conferences are expected. The active involvement in project management is planned for postdocs. 
Excellent to good master, Dipl.-Ing. or PhD degree in microelectron-ics, electrical engineering, physics or chemistry. Knowledge in circuit design, inde-pendent and flexible working attitude, innovative and analytical thinking, strong commitment, communicative team-player, good English. Knowledge in the following areas is advantageous: Integrated circuit design, OLAE, device modelling, high frequency engineering, communications and semiconductor technologies, measure-ment techniques, German language.
Applications from women are particularly welcome. The same applies to the disabled. Interested candidates are requested to submit concise application material including CV and copy of certificates per email in pdf format to Frank.Ellinger@tu-dresden.de [read more...]