Sep 30, 2018

Sep 28, 2018

New Charge Pumping Current #Model Assuming Exponential Tails in the Trap Energy Distribution. This modified expression leads to a different method of extracting the trap emission time constant

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September 28, 2018 at 12:20PM

Sep 27, 2018

System76 To Release A "New #opensource #Computer"

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September 27, 2018 at 05:14PM

[paper] Importance of complete characterization setup on onwafer TRL calibration in sub-THz range

Chandan Yadav, Marina Deng, Magali De Matos, Sebastien Fregonese
and  Thomas Zimmer
IMS Laboratory, University of Bordeaux
351 cours de la Libération – 33405 Talence cedex, France

Abstract: In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, onwafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented. 

FIG: 3D view of the Open-M1 where metal-1 (M1) does not have connection with ground as shown in the enlarged view.

Sep 26, 2018

#Modeling of Electron Devices Based on 2-D Materials. Shortly analyze the main open challenges of modeling 2-D-based electron devices.

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September 26, 2018 at 02:48PM

Sep 14, 2018

Ph D student scholarship about compact modeling at URV (Tarragona, Spain)

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for three years. The monthly salary will be about 1000 Euro/month, which is more than enough to live in Tarragona. The position will start between January and April 2019.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs under cryogenic conditions for Quantum Computing.This work will be carried out in collaboration with a research team in IMEC in Leuven (Belgium).
The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible) with passport number
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates are requested to send their documents by e-mail to:
Prof. Benjamin IñiguezDepartment of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
Tarragona (Spain)Email: benjamin.iniguez@gmail.comTel: +34977558521 Fax:+34977559610

Deadline for documents submission: October 6 2018
You can contact Prof. Benjamin Iñiguez ( for more information
Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at:

Sep 11, 2018

[mos-ak] [press note] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

Dresden, Sept. 3, 2018

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 16th MOS-AK Workshop in the timeframe of ESSDERC/ESSCIRC. The event was hosted on September 3rd, 2018, by the TU Dresden in Dresden, Germany. The technical program of the event was coordinated by the MOS-AK TPC Committee. The workshop has received technical program promotion provided by ASCENT Network, Europractice, EPFL EDlab, IJHSES as well as NEEDS of

The MOS-AK workshop was opened by Wladek Grabinski, who has welcomed all the attendees. A group of 30+ international academic researchers and modeling engineers attended 10 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support.

The workshop was chaired by Larry Nagel, OEC (USA), Suba Subramaniam, XFAB (D) and Matthias Bucher, TUC (GR). In the first morning session Wladek Grabinski gave an overview of the MOS-AK Community. Afterwards, Prof. Muhammad Mustafa Hussain from KAUST (SA) held a talk of "Physically Compliant CMOS Electronics Enabled Interactive Electronic System". It followed a talk by Dr. Sadayuki Yoshitomi from Toshiba Memory Corp. (J) gave some insights of "RF CMOS Compact modeling technologies past and future".
Krishna Pradeep from ST Microelectronics (D) started the second morning session with a talk entitled "Analysis and modeling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data". Kerim Yilmaz from TH Mittelhessen (D) offered a modeling approach for "Scaling correlation between DG & GAA MOSFETs". Dr. Laurie Calvet from University Paris-Sud (F) held a talk on "Compact Modeling for Neuromorphic Applications". The morning session ended with "Advanced PDK and Technologies accessible through ASCENT" by Dr. Luca Perniola from CEA (F).

The afternoon session continued with four additional talks, where Dr. Farzan Jazaeri from EPFL (CH) gave a talk on "Reliability Modeling in Harsh Radiation for Space Applications". Prof. Benjamin Iniguez from URV (SP) explained the latest results on "Low frequency noise modeling of organic and IGZO TFTs". Dr. Mike Schwarz from NanoP (D) continued with the topic "Schottky Barrier MOSFET Device Physics for Cryogenic Applications". The session was closed by a talk of Dr. Daniel Tomaszewski, ITE (PL), on various methodologies of "Compact Modeling for Process and Device Characterization".

The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and all the presentations are available online for download at

Photo: Part of the participants of the 16th MOS-AK Workshop at ESSDERC/ESSCIRC

Afterward all the participants could follow ESSDERC Track4 "Compact modeling of devices and circuit" on Sept. 5-6, 2018
Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
Chair: Wladek Grabinski, Thierry Poiroux
Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
Chair: Daniel Tomaszewski, Benjamin Iniguez

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA, China and India throughout coming 2018/2019 years, including:
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit:

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Sep 8, 2018

Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques #paper IJNM

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September 08, 2018 at 04:32PM

#FOSSCON 2018: Where #OpenSource and #LEGO Collide | Tux Machines

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September 08, 2018 at 01:09PM