Friday, January 31, 2020

#paper A. Dasgupta et al., "BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs," in IEEE Transactions on Electron Devices, vol. 67, no. 2, pp. 730-737, Feb. 2020. doi: 10.1109/TED.2019.2960269

from Twitter

January 31, 2020 at 11:29PM

Wednesday, January 29, 2020

#paper: S. A. Albahrani, L. Heuken, D. Schwantuschke, T. Gneiting, J. N. Burghartz and S. Khandelwal, "Consistent Surface-Potential-Based Modeling of Drain and Gate Currents in AlGaN/GaN HEMTs," in IEEE TED, vol. 67, no. 2, pp. 455-462, Feb. 2020.

from Twitter

January 29, 2020 at 11:28AM

Tuesday, January 28, 2020

#CMP provides new MPW access to #EMM 0.18µm CMOS 4/5ML EMALP018. The use of the near and sub-threshold voltage for the MOS devices with the #EKV #model is one of the key feature and strength of the EM Microelectronic offer

from Twitter

January 28, 2020 at 01:27PM

How I #teach #physics using #opensource tools

from Twitter

January 28, 2020 at 11:34AM

Free Software Foundation behind petition to #OpenSource Windows 7 #win7

from Twitter

January 28, 2020 at 09:18AM

C4P: The 2020 edition of the International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) will be held in Erfurt, Germany, June 20-23, 2020 #paper

from Twitter

January 28, 2020 at 09:13AM

#paper: Michał Zaborowski, Daniel Tomaszewski, and Jacek Marczewski "A test structure for investigation of #junctionless #FETs as #THz radiation #sensors ", Proc. SPIE 10175, Electron Technology Conference 2016, 1017512 (22 December 2016);

from Twitter

January 28, 2020 at 07:27AM

Monday, January 27, 2020

TowerJazz, Cadence, and #Kyiv Polytechnic Institute (KPI) to Open First #Analog #Design Lab #paper

from Twitter

January 27, 2020 at 02:18PM

#paper: P. Grybos, "European Summit on Solid-State Device and Circuit Research: #ESSDERC/#ESSCIRC Conference in #Krakow (PL)" in IEEE Solid-State Circuits Magazine, vol. 12, no. 1, pp. 87-91, winter 2020 doi: 10.1109/MSSC.2019.2951652

from Twitter

January 27, 2020 at 12:58PM

Sunday, January 26, 2020

#paper: G. J. Coram, C. C. McAndrew, K. K. Gullapalli and K. S. Kundert, "Flicker Noise Formulations in Compact Models," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi: 10.1109/TCAD.2020.2966444

from Twitter

January 26, 2020 at 07:38PM

Friday, January 24, 2020

Through the Looking Glass #2020 Edition: #Trends in Solid-State Circuits From #ISSCC #paper

from Twitter

January 24, 2020 at 11:28AM

Coming Soon to a Processor Near You: #Atom-Thick #Transistors [IEEE Spectrum #paper]

from Twitter

January 24, 2020 at 10:26AM

#dnGrep is an #opensource tool that can search for text inside documents [gHacks Tech News]

from Twitter

January 24, 2020 at 08:09AM

Thursday, January 23, 2020

#SiC #Foundry Business Emerges #paper

from Twitter

January 23, 2020 at 01:48PM

9th SiNANO Modeling and Simulation Summer School

2020 Summer School on advanced modeling and simulation of conventional and novel nano-CMOS devices, to be held in Glasgow, Scotland with technical sessions from the 29th June – 3rd July 2020

This year the SINANO Summer School will target multi-scale modeling and simulation of semiconductor devices. It includes a total of 15 lectures targeting topics related to the modelling and simulation as well as fabrication and characterization of different types of semiconductor nanoelectronic devices. The Summer School will cover to the following topics:
  • Novel nanoelectronics devices and corresponding modelling challenges.
  • Material modeling and atomic scale device simulation.
  • Quantum transport and simulations.
  • Monte Carlo and Wigner Monte Carlo simulations.
  • Compact modeling
  • Process simulations
  • Design Technology Co-Optimization (DTCO)

Confirmed invited speakers:
Dr. Victor Moroz
Prof. Gerhard Klimeck
Purdue University
Prof. Adrian Ionescu
Prof. Philippe Dollfus
University Paris Sud
Prof. Mathieu Luisier 
Prof. Nicola Marzari
Dr. Kirsten Moselund
IBM Zurich
Prof. Francisco Gamiz
University of Granada
Dr. Kurt Stokbro
Prof. Max Fischetti
The Uni. Texas - Dallas
Prof. Jurgen Lorenz
IISB Fraunhofer
Prof. Tibor Grasser
TU Vienna
Dr. Yann-Michel Niquet
CEA Leti
Dr. Cory Weber
Intel USA
Dr. Plamen Asenov

For more information please see the flyer and this website:

Wednesday, January 22, 2020

#paper: D.Root, "Generation X: Second Generation X-parameter technology”

from Twitter

January 22, 2020 at 02:24PM

#Perovskite range enables #opto applications #paper

from Twitter

January 22, 2020 at 11:41AM

Monday, January 20, 2020

Qucs-S as R&D design software


is not a simple circuit simulator, but also a research software. Please cite your R&D articles, if you are using Qucs-S in your research.



Qucs-S is not a simple circuit simulator, but also a research software. Please cite our articles, if you are using Qucs-S in your research.
  1. Brinson, M. E., and Kuznetsov, V. (2016) A new approach to compact semiconductor device modelling with Qucs Verilog-A analogue module synthesis. Int. J. Numer. Model., 29: 1070-1088. (BibTeX)
  2. D. Tomaszewski, G. Głuszko, M. Brinson, V. Kuznetsov and W. Grabinski, "FOSS as an efficient tool for extraction of MOSFET compact model parameters," 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, 2016, pp. 68-73. (BibTeX)
  3. M. Brinson and V. Kuznetsov, "Qucs-0.0.19S: A new open-source circuit simulator and its application for hardware design," 2016 International Siberian Conference on Control and Communications (SIBCON), Moscow, 2016, pp. 1-5. (BibTeX)
  4. M. Brinson and V. Kuznetsov, "Improvements in Qucs-S equation-defined modelling of semiconductor devices and IC's," 2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems, Bydgoszcz, 2017, pp. 137-142. (BibTeX)
  5. M. Brinson and V. Kuznetsov, "Extended behavioural device modelling and circuit simulation with Qucs-S" International Journal of Electronics, 2017, pp.1 - 14 (BibTeX)

Friday, January 17, 2020

H2020 Training Courses

H2020 Financial Management Training
18-20 Feb 2020 - Rome, Italy
03-05 Mar 2020 - Amsterdam, the Netherlands
28-30 April 2020 - Brussels, Belgium
16-18 Jun 2020 - Valletta, Malta
Read More
H2020 Proposal Writing Training
29-30 Jan 2020 - Lisbon, Portugal
04-06 Feb 2020 - Vienna, Austria
10-12 Mar 2020 - Barcelona, Spain
12-14 May 2020 - Amsterdam, the Netherlands
09-11 June 2020 - Valletta, Malta
*Our H2020 Proposal Writing training will now be a 3 day event which will now include guidance & information on how the new Horizon Europe programme is shaping up to look like plus a day dedicated to the management of the Funding & Tenders Portal (SEDIA)

Universities: Contact your international office for possible funding opportunities to attend our trainings under Erasmus +

All our H2020 trainings can be delivered in–house anywhere in Europe or around the world.

Find out more here

Wednesday, January 15, 2020

[mos-ak] 2020 calendar

MOS-AK 2020 Calendar
The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru 2020 year, including:
W.Grabinski on the behalf of International MOS-AK Committee

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The #opensource licence debate: what we need to know

from Twitter

January 15, 2020 at 12:19PM

EKV2.6 conference paper reached 50 reads

W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," 
ESSDERC, Krakow, Poland, 2019, pp. 190-193.
doi: 10.1109/ESSDERC.2019.8901822

Monday, January 13, 2020

#ENSEMBLE3 project on new photonic materials is starting #paper

from Twitter

January 13, 2020 at 08:24PM

#CERN Endorsing Microsoft Alternatives #opensource Like ownCloud, Kopano, Alt-Office Suite - Phoronix

from Twitter

January 13, 2020 at 03:08PM

N7 FinFET Self-Aligned Quadruple Patterning #Modeling

from Twitter

January 13, 2020 at 12:00PM

#paper: K. Aadithya, P. Kuberry, B. Paskaleva, P. Bochev, K. Leeson, A. Mar, T. Mei, E. Keiter; Development, Demonstration, and Validation of Data-driven Compact Diode Models for Circuit Simulation and Analysis (Submitted on 6 Jan 2020)

from Twitter

January 13, 2020 at 10:45AM

#paper: Zhou, W, Liu, J, Chen, Z, Sun, L. A broadband small‐signal model extraction methodology over 0.2‐220 GHz for bulk FinFETs in #RF #CMOS technology. Int J Numer Model El. 2020;e2712.

from Twitter

January 13, 2020 at 08:57AM

Thursday, January 9, 2020

Wednesday, January 8, 2020

Ivanka to CES: College Is Overrated #paper

from Twitter

January 08, 2020 at 10:18AM

#Huawei’s Linux Distribution #openEuler is Available Now! #opensource

from Twitter

January 08, 2020 at 10:06AM

Prof. Benjamin Iniguez nominated IEEE Fellow (2020)

Prof. Benjamin Iniguez, IEEE EDS R8 Active Fellow (2020)
Research Engineer/Scientist
for contributions to physics-based compact models of semiconductor devices

Tuesday, January 7, 2020

What is #FOSS, and how does it differ from #Freeware #opensource

from Twitter

January 07, 2020 at 09:32PM

#paper F. Jazaeri, M. Shalchian and J. Sallese, "Transcapacitances in EPFL #HEMT Model," in IEEE Transactions on Electron Devices doi: 10.1109/TED.2019.2958180

from Twitter

January 07, 2020 at 03:16PM

#paper: L. Yu, J. Ren, X. Lu and X. Wang, "NBTI and HCI Aging Prediction and Reliability Screening During Production Test," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. doi: 10.1109/TCAD.2019.2961329

from Twitter

January 07, 2020 at 03:13PM

#paper: Y. Ma, M. Xiao, R. Zhang, H. Wang and Y. Zhang, "Superjunction Power Transistors With Interface Charges: A Case Study for GaN," in IEEE JEDS, vol. 8, pp. 42-48, 2020 doi: 10.1109/JEDS.2019.2959713

from Twitter

January 07, 2020 at 11:00AM

Friday, January 3, 2020

C4P Special Issue JEDS on Compact Modeling

Call for papers for a Special Issue
of IEEE Journal of the Electron Devices Society
on “Compact Modeling of Semiconductor Devices”
Submission deadline: April 1, 2020 MAY 15, 2020

In order to exploit the full potential of semiconductor devices in circuit design, compact device models are critically needed. Compact device models are the vehicle that allow the design of circuits using the targeted devices. Predictive and physically-based compact device models are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate compact device models. 
Compact models should accurately capture the physics of the device in all operation regimes, but at the same time they should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. Furthermore, compact models can also be used as a tool to make realistic estimations of the performances of future devices following technological trends.
The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical phenomena which determine their behaviors. Regarding many emerging non-silicon devices, circuit and system designers very often rely on empirical behavioral macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, and therefore does not allow accurate production quality design.

Suggested topics include but not limited to:

1. Silicon MOSFET modeling
a. Advanced Bulk MOSFETs
c. Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, nanosheet MOSFETs, UTB SOI MOSFETs, etc.
d. Junctionless MuGFETs
e. Power and high voltage MOSFETs
2. Junction-based and compound semiconductor FET modeling:
a. Advanced MESFETs
b. Advanced HEMTs
d. Advanced JFETs
3. Diode and bipolar transistor modeling:
a. Advanced BJTs
b. HBTs
c. IGBTs
d. pn and pin diodes
e. Varactors
4. Emerging transistor modeling:
a. Tunnel FETs
b. Molecular transistors
c. Single Electron Transistors
d. Quantum Dot Transistors
e. Negative Capacitance Transistors
5. Emerging semiconductor devices
Memories, MRAM, PCRAM, etc.
Spintronic devices
Layered/2D semiconductor devices
Graphene-based devices
6. TFT
a. a-Si:H TFTs
b. Polycrystalline Si TFTs
c. OTFTs and OECTs
d. Oxide TFTs
e. Single-crystal TFts
7. Modeling of physical effects
a. Noise
b. High frequency operation
c. Cryogenic conditions
d. Mismatch
e. Strain
f. High energy particle interactions in ICs (Cosmic rays and energy beams)
g. ESD events
h. Ballistic and quasi-ballistic transport
i. Layout dependent effects
8. Photonic devices
a. LEDs and OLEDs
b. Photodiodes
c. Solar cells
d. Photodetectors
e. SPADs
f. Photonic Crystals
9. Parameter extraction methods
a. Direct extraction methods
b. Global optimization methods

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please, visit article/use-authoring-toolsand-ieee-article-templates/ieee-article-templates/templates-for- transactions/ to download the templates. When submitting your manuscript through the IEEE’s web-based ScholarOne Author Submission and Peer Review System (, please indicate that your submission is for this special issue.

Guest Editor in Chief:
  • Benjamin Iniguez, Universitat Rovira i Virgili, Tarragona, Spain
Guest Associate Editors:
  • Yogesh Chauhan, IIT Kanpur (IN) 
  • Slobodan Mijalkovic, Silvaco Europe Ltd., St.Ives (UK) 
  • Kejfun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
  • Jhung-Suk Goo, Global Foundries, Sunnyvale, CA (USA), 
  • Marcelo Pavanello, Centro Universitario da FEI, Sao Paulo (BR), 
  • Marek Mierzwinski, Keysight Technologies, Santa Rosa, CA (USA)
  • Wladek Grabinski, GMC Consulting, Commugny (CH)
Please, direct all communications to Marlene James at

DOI 10.1109/TED.2019.2960953

#paper: C. Kun, Y. He, Y. Li, A. Ng and J. Yu, "A Room Temperature Hydrocarbon Electronic Nose Gas Sensor Based on Schottky and Heterojunction Diode Structures," IEEE EDL, vol. 41, no. 1, pp. 163-166, Jan. 2020 doi: 10.1109/LED.2019.2956560

from Twitter

January 03, 2020 at 02:16PM

Thursday, January 2, 2020

[mos-ak] [online publications] 12th International MOS-AK Workshop Silicon Valley, December 11, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
12th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, organized consecutive, 12th International MOS-AK Workshop which took place at Silvaco HQ on Dec. 11, 2019 (co-located with the IEDM and CMC Meetings). 

Dr. Bogdan Tudor, Sr. Manager and Head of Device Characterization at Silvaco, lead the local organizing committee and was Silvaco's host at the event. Dr. Tudor and Dr. Grabinski of MOS-AK gave the opening remarks and introduction. There were more than 30 attendees from the research community followed 13 technical presentations covering selected aspects of the compact/SPICE modeling and its Verilog-A standardization (see all the citation and abstract below; all the slide presentations online at The event short summary and a photo gallery is also available online

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special 
Solid State Electronics issue on compact modeling planned for 2020

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses around the globe thru 2020 year, including:
W.Grabinski on the behalf of International MOS-AK Committee

Agenda Citation and Abstract of 12th International MOS-AK Workshop
9:00-12:00MOS-AK Morning Session
Chair: Roberto S. Murphy, INAOE, Puebla (MX) and Bogdan Tudor, Silvaco (USA)
MOS-AK Introduction
Bogdan Tudor and W. Grabinski, Silvaco and MOS-AK
MOS-AK Meetings are organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors. The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme – frontiers of the compact modeling for nm-scale MEMS/NEMS designs, CMOS/SOI and HEMT IC simulation.
Si2 Compact Model Coalition: 2019 Update
Peter M. Lee, Si2 CMC
This talk will summarize the accomplishments and ongoing initiatives of the Si2 Compact Model Coalition for 2019. The release of new standards, new releases of existing standards, look-ahead projects, and revised policies will be presented.
What's in the Standard? Establishing the CMC Policy for Verilog-A Models
Geoffrey Coram, Analog Devices, Inc.
The Compact Model Coalition, part of the Silicon Integration Initiative (Si2), is developing a policy on what parts of the Verilog-A code for a model are officially part of the standard. Under long-standing CMC policy, a compliant implementation of a standard model must produce the same currents (dc, transient, and ac) and noises as the reference model. The new policy extends the requirements to operating-point values, noise contributors, terminal names, etc. This talk will discuss the process of developing this policy and the inconsistencies that motivated its development.
SPICE Modeling of Power Devices
Bogdan Tudor, Silvaco
Review of Power device SPICE modeling including macromodel development using TCAD data, specific capacitance modeling and scaling, and transient model tuning. This is illustrated on various device types such as power MOSFET, symmetric and asymmetric GaN HEMT, VDMOS, and IGBT.
Coffee Break
Toward physics-based reliability-aware compact models
Pieter Weckx, Erik Bury, Ben Kaczer, imec
This presentation will discuss a range of reliability solutions from test structures to reliability-aware compact modeling. Developing tools and compact models to enable accurate degradation assessment at the design level is imperative for improving end-product PPAC. To maximize potential gains, workload dependence needs to be factored-in, combined with detailed knowledge of the underlying device degradation mechanisms such as Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), including Self-Heating Effects (SHE). Physics-based understanding of degradation at microscopic / individual defect level will be reviewed. Internally-developed tools and methodologies for assessing and modeling the mean and the variance of device degradation, such as Smart Arrays, Comphy, TCAD, and compact modeling, will be discussed.
Overview and Parameter Extraction of L-UTSOI Model for FDSOI Technologies
Ma Long and Shuang Cai, Keysight
The Fully Depleted Silicon On Insulator (FDSOI) exhibits excellent electrostatic control and reduced variability for the advanced technologies down to 20nm. L-UTSOI is a standardized model that can describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, we will talk about the L-UTSOI model and introduce the latest extraction flow.
Characterization of Semiconductor Devices in the High-Frequency Regime
Roberto S. Murphy, INAOE, Puebla, México
As electronic devices reach higher frequencies of operation, the need to trustworthy characterize and model them garners importance. Measurements in the high-frequency regime are not straightforward, however, since the ensemble is prone to experimental errors, which have to be considered and corrected for beforehand. In this talk, I will address the measurement system setup, skimming through measurement uncertainty considerations, setup calibration, and de-embedding aspects. An example of a characterization and modeling run for MOS transistors is also presented. The talk closes with a discussion of future trends and needs in the area.
12:00-13:00Lunch Break
13:00-16:00MOS-AK Afternoon Session
Chair: Bogdan Tudor, Silvaco (USA) and W. Grabinski MOS-AK (EU)
Latest Developments in the Xyce Large-Scale Analog Circuit Simulator
Jason Verley, Sandia National Labs
This presentation will provide an overview of the open source analog simulation tool, Xyce, which was designed from the ground-up to perform large-scale circuit analysis. Current capabilities of the simulation tool will be discussed, including the analysis methods, device models, and parallel implementation. An emphasis will be made on the latest developments in Xyce. In the last year, the focus of Xyce development has been in the following areas. First, the calculation of analytic derivatives was added to the Xyce-ADMS backend, resulting in significant performance enhancements. Other performance improvements in the linear solver resulted in improved run times, and a 20% reduction in memory use. The mixed-signal interface was modified to use the VPI (Verilog Procedural Interface) standard, and S-parameter analysis was added. Finally, an HSPICE netlist translation capability will soon be made available to allow easy use of PDKs and circuit designs created for that simulator. The talk will conclude with a discussion of planned developments in the near future.
An oxide-based bipolar RRAM compact model
Meng-Hsueh Chiang, Jia-Wei Lee, Po-An Chen, and Chun-Hsiang Hsu, National Cheng Kung University
RRAM (resistive random-access memory) has emerged as a promising nonvolatile memory technology due to high density, fast speed, and technology compatibility. Applications of RRAM are also very demanding as RRAM provides opportunities of in-memory and neuromorphic computing with its versatile programming capability and synaptic nature, respectively. All these requires a reliable model that can capture the physical phenomena and can be simply calibrated to limited hardware data, or even can be predictive when technology is not so mature. An oxide-based bipolar RRAM compact model is introduced. Recent findings from technology advances that might enable nonconventional design techniques is overviewed as well.
Keeping Up with Mextram: 2019 Development Updates with SiGe HBT Circuit Implications
Guofu Niu*, Huaiyuan Zhang*, Yiao Li*, Andries Scholten**, Marnix Willemsen***, Wei Chen****,
*Auburn University, ** NXP Semiconductors, *** Texas Instruments
An overview of recent Mextram developments will be given with SiGe HBT circuit application examples, including both Mextram 505.1.0 and 504.13.0 that were released March 2019, as well as on going developments to be included in next release. Mextram 505.1 adds new models for 1) much improved RF linearity modeling, 2) much improved high injection Cbc modeling, 3) much improved substrate current modeling at high VBE, and 4) CB junction leakage and off state breakdown modeling. The background behind the release of 504.13.0 and its implications to oscillator phase noise simulation will be discussed. We will show that the choice of avalanche initiating current has subtle but significant implications on both RF impedance and noise in presence of avalanche, particularly when transistor main current is low.
Coffee Break
10 Device Modeling for Neuromorphic Computing with Dynamic Time Evolution Method
Lining Zhang, Mansun Chan, UST (HK)
Memory based neuromorphic computing becomes popular among researchers and compact memory modeling is required for circuit designs. In this talk we will introduce the dynamic time evolution method to reproduce the analog memory nature which is the core feature for the unique application. Continuous programing of the memory in the low-to-high or high-to-low resistance transitions are precisely simulated. The model has been used in the simulations of a phase-change-memory synapse in conjunction with the control circuits as well as the neurons with nice convergence. At the same time, the dynamic time evolution method allows a reduction in the circuit matrix size with a significant reduction of the simulation time for large scale memory applications.
11 Model Evaluation for HiSIM2 3.1.1
Chika Tanaka, Takeshi Naito, Miya Yamamoto, Atsushi Sueoka, and Sadayuki Yoshitomi, Memory Division, Kioxia Corporation
Model Evaluation for HiSIM2 3.1.1 concerning optimization results with added new model parameter will be reported.
12 MVSG model for RF applications: Thermal, Scalability and Parasitic Modeling
Xuesong Chen, Ujwal R Krishna, Lan Wei, Massachusetts Institute of Technology
In this work, we extend the industry standard MIT Virtual Source GaN HEMT (MVSG) model to include layout dependent effects such as scaling of parasitic fringing capacitances, scaling of distributed gate- and channel-resistance, and scaling of thermal network, which target wide periphery FETs for high-frequency (HF) power amplification applications. We have also studied self-heating mechanism and its impact on electrical performance of short gate length GaN HEMTs based on electro-thermal TCAD simulations. Different roles of equivalent channel temperature and max channel temperature are discussed and modeled. Further, we capture the safe-operating area (SOA) of the device by including channel-breakdown in addition to gate-diode breakdown which is useful for high voltage (HV) applications. The modeling approach satisfies Gummel symmetry-benchmarks and is valid for symmetric switch FETs.
13 FOSS EKV2.6 Model at GitHub
W. Grabinski, MOS-AK
The EKV2.6 MOSFET compact model has had a considerable impact on the academic and industrial community of analog integrated circuit design, since its inception in 1996. The model is available as a free open-source software (FOSS) tool coded in Verilog-A. The present paper provides a short review of foundations of the model and shows its capabilities via characterization and modeling based on a test chip in 180 nm CMOS fabricated via Europractice.
16:00End of MOS-AK Workshop

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