Tuesday, January 30, 2018

Extraction of #Process #Variation Parameters in FinFET Technology Based on #Compact #Modeling and... https://t.co/vqTFtfDxWG


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January 30, 2018 at 03:51PM
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Extraction of #Process #Variation Parameters in FinFET Technology Based on #Compact #Modeling and Characterization - IEEE Journals & Magazine https://t.co/6RlUeQ3fhp


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January 30, 2018 at 03:51PM
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Monday, January 29, 2018

A look inside #Facebook's #opensource program https://t.co/3NxWinj54L https://t.co/9Q8ZCDCcpx


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January 29, 2018 at 01:54PM
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A Method for Local Parametric Fault Diagnosis of a Broad Class of Analog Integrated Circuits https://t.co/KwosJZWeZx #paper


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January 29, 2018 at 09:47AM
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Why is #opensource software so #popular? https://t.co/2k9RDZCciB https://t.co/Dc0yWbPgpw


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January 29, 2018 at 10:01AM
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Sunday, January 28, 2018

[PhD] Modeling and Spice Implementation of SOI G4FET

Modeling and Spice Implementation of Silicon on Insulator (SOI)
Four Gate (G4FET) Transistor
Md Sakib Hasan
PhD Dissertation
The University of Tennessee, Knoxville, August 2017

Abstract: As the device dimensions have reduced from micrometer to nanometer range, new bulk silicon devices are now facing many undesirable effects of scaling leading device engineers to look for new process technologies. Silicon-on-insulator (SOI) has emerged as a very promising candidate for resolving the major problems plaguing the bulk silicon technology. G4FET [G4FET] is a SOI transistor with four independent gates. Although G4FET has already shown great potential in different applications, the widespread adoption of a technology in circuit design is heavily dependent upon good SPICE (Simulation Program with Integrated Circuit Emphasis) models. CAD (Computer Aided Design) tools are now ubiquitous in circuit design and a fast, robust and accurate SPICE model is absolutely necessary to transform G4FET into a mainstream technology.
The research goal is to develop suitable SPICE models for G4FET to aid circuit designers in designing innovative analog and digital circuits using this new transistor. The first phase of this work is numerical modeling of the G4FET where four different numerical techniques are implemented, each with its merits and demerits. The first two methods are based on multivariate Lagrange interpolation and multidimensional Bernstein polynomial. The third numerical technique is based on multivariate regression polynomial to aid modeling with dense gridded data. Another suitable alternative namely multidimensional linear and cubic spline interpolation is explored as the fourth numerical modeling approach to solve some of the problems resulting from single polynomial approximation.
The next phase of modeling involves developing a macromodel combining already existing SPICE models of MOSFET (metal–oxide–semiconductor field-effect transistor) and JFET (junction-gate field-effect transistor). This model is easy to implement in circuit simulators and provides good results compared to already demonstrated experimental works with innovative G4FET circuits. The final phase of this work involves the development of a physics-based compact model of G4FET with some empirical fitting parameters. A model for depletion-all-around operation is implemented in circuit simulator based on previous work. Another simplified model, combining MOS and JFET action, is implemented in circuit simulator to model the accumulation mode operation of G4FET [read more...]

Saturday, January 27, 2018

#C4P for a Special Issue of IEEE Transactions on Electron Devices on #2D #Materials for Electronic, Optoelectronic and Sensor Devices https://t.co/c76nBVISRO #paper


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January 27, 2018 at 12:14AM
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Friday, January 26, 2018

X. Cheng, S. Lee and A. Nathan, "Deep #Subthreshold #TFT Operation and Design Window for #Analog Gain Stages," in IEEE JEDS, vol. 6, no. 1, pp. 195-200, 2018. 10.1109/JEDS.2018.2789579 https://t.co/tsvLTC9z0r #paper


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January 26, 2018 at 08:23PM
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Wednesday, January 24, 2018

Tuesday, January 23, 2018

#China Declared World's Largest Producer of #Scientific #Articles https://t.co/hFX6Atk6ru #paper


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January 23, 2018 at 08:20PM
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Monday, January 22, 2018

#Organic $TFT New Gate Dielectric Opens Door to Future Electronics https://t.co/kMkigcS7Ey #paper https://t.co/0tPwTpOO2O


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January 22, 2018 at 04:15PM
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Thursday, January 18, 2018

New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs https://t.co/7ZXUlR4MMk #paper


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January 18, 2018 at 04:07PM
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[mos-ak] [2nd Announcement and Call for Papers] Spring'18 MOS-AK Workshop Strasbourg, March 15-16, 2018

Spring'18 MOS-AK Workshop
Strasbourg, March 15-16, 2018

2nd Announcement and Call for Papers 

Together with local organization team: Christophe Lallement and Morgan Madec (ESP, Uni Strasbourg), Technical MOS-AK Program Coordinator: Jean-Michel Sallese (EPFL) as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized at Strasbourg University on March 15-16, 2018

Planned, Spring MOS-AK/Strasbourg workshop, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: 
ICube Laboratory 
(UMR CNRS/UdS 7357)
Strasbourg University

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Dec. 2017
  • 2nd Announcement - Jan. 2018
  • Final Workshop Program - Feb. 2018
  • MOS-AK Workshop - March 15-16, 2018 
Prospective authors should 
submit abstract online
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

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Sunday, January 14, 2018

#Bika #LIMS : Free #Opensource Laboratory Information Management System. https://t.co/6MtlzH9sJF #FOSS


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January 14, 2018 at 09:48PM
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Friday, January 12, 2018

#Nanostructure Boosts Stability Of #Organic #TFT https://t.co/Ovpc6YJIBh #paper


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January 12, 2018 at 10:07PM
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Wednesday, January 10, 2018

Why isn't #opensource hot among computer science students? https://t.co/hynyL0FNam


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January 10, 2018 at 09:43PM
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