Tuesday, December 31, 2019

5 #opensource innovation predictions for the 2020s and #4 is: "Quantum processors available for developers" https://t.co/xuyqACjisD https://t.co/hLcKH7QF5f


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December 31, 2019 at 08:49AM
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Thursday, December 26, 2019

Researchers demo #CMOS-compatible #SOT #MRAM cell https://t.co/lbwzyuA5YE #paper https://t.co/5KIe9yJVaE


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December 26, 2019 at 11:46AM
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#paper K. Kato, H. Matsui, H. Tabata, M. Takenaka and S. Takagi, "Fabrication and Electrical Characteristics of ZnSnO/Si Bilayer Tunneling Filed-Effect Transistors" IEEE JEDS, vol. 7, pp. 1201-1208, 2019 doi: 10.1109/JEDS.2019.2933848 https://t.co/TrScHGouQR https://t.co/qizSOxCKSu


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December 26, 2019 at 10:22AM
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Wednesday, December 25, 2019

Monday, December 23, 2019

#paper: Lee, M. Millimetre-scale thin-film batteries on a charge. Nat Electron 2, 550 (2019) doi:10.1038/s41928-019-0346-7 https://t.co/xzO5o0e6fl https://t.co/t5NHibezRc


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December 23, 2019 at 12:38PM
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#paper H. Hu et al., "A Compact Phase Change Memory Model With Dynamic State Variables," in IEEE TED. doi: 10.1109/TED.2019.2956193 https://t.co/PicLTsiRPy https://t.co/E2Knk0ZibS


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December 23, 2019 at 12:14PM
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Friday, December 20, 2019

Visualizing Moore’s Law in Action (1971-2019) https://t.co/jiCMsFxvVA #paper https://t.co/Ck0Pe8fHEz


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December 20, 2019 at 10:22PM
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#paper Si, M., Saha, A.K., Gao, S. et al. A #ferroelectric semiconductor field-effect transistor #FET. Nat Electron 2, 580–586 (2019) doi:10.1038/s41928-019-0338-7 https://t.co/DfLtGSLdrJ https://t.co/ZOMSORypoN


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December 20, 2019 at 11:43AM
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EspoTek Labrador by EspoTek A small, portable, USB-connected electronics lab-on-a-board that includes an oscilloscope, waveform generator, power supply, logic analyzer, and multimeter. https://t.co/KjhalAzAZy #modeling https://t.co/CR1iTXYklY


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December 20, 2019 at 09:39AM
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#paper Papadopoulos, N., Qiu, W., Ameys, M. et al. Touchscreen tags based on thin-film electronics #TFT for the Internet of Everything #IoT. Nat Electron 2, 606–611 (2019) doi:10.1038/s41928-019-0333-z https://t.co/EW6V32HgM2 https://t.co/5ZeCNzvssH


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December 19, 2019 at 11:22PM
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Thursday, December 19, 2019

IEDM took place last week with: * Tutorials on Saturday * Two parallel short courses on Sunday * Plenary session on Monday morning * Press luncheon on Monday * Then a dozen sessions running in parallel https://t.co/hdrySfWNHf #paper https://t.co/0GxwGRMy0A


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December 19, 2019 at 03:48PM
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Wednesday, December 18, 2019

IRPhE 2020 Aghveran, Armenia

International Conference on Microwave & THz Technologies,
Wireless Communications and OptoElectronics
September 23-25, 2020, Aghveran, Armenia

IRPhE 2020 Call for Papers

The aim of the IRPhE’ 2020 Conference is to provide an open forum for the presentation and discussion of current research in Microwave and THz technologies, wireless communications, alternative electronic devices, photonics and its applications.

The main topics of the conference are and not limited to:

  • Microwave devices, antennas, propagation and remote sensing
  • THz technique, spectroscopy and applications
  • Alternative semiconductor and dielectric materials, electronic devices
  • Wireless communications and related information technologies
  • Microwave photonics
For further information visit the website: http://www.irphe.am/?q=conference

Submission Information
Original one page abstracts will be accepted for review in Word and PDF formats.The accepted abstracts will be published in an abstract book and distributed during the conference.
All the authors who have presented their work at the conference will be invited to submit 4-page follow-up papers for publication special IJHSES issue on the "Microwave and THz technologies"

Abstracts must be submitted via email: science@irphe.am.

Tuesday, December 17, 2019

Intel’s Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm; It’s worth also pointing out, based on the title of this slide, that #Intel still believes in #Moore’s Law. Just don’t ask how much it’ll cost. https://t.co/VIwrSoWEgB #paper https://t.co/LorF5xyHnT


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December 17, 2019 at 12:03PM
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Monday, December 16, 2019

#paper Z. Ahmed, Q. Shi, Z. Ma, L. Zhang, H. Guo and M. Chan, "Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations," in IEEE EDL doi: 10.1109/LED.2019.2952382 https://t.co/CiaNcxqSwb https://t.co/xxTqg2iAMI


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December 16, 2019 at 02:22PM
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The Open Source Computer Aided Modeling and Design #devroom schedule for #FOSDEM 2020 is official at: https://t.co/5GpDFo6fpo #paper https://t.co/dkTuVHseGP


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December 16, 2019 at 11:13AM
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Wednesday, December 4, 2019

The EKV2.6 MOSFET compact #model has had a considerable impact on the academic and industrial community of ultra low power analog/RF IC design, since its inception in 1996. Its Verilog-A code is available online at GitHub, now https://t.co/0iDmBChDVm https://t.co/BTBAbPm7aN


from Twitter https://twitter.com/wladek60

December 04, 2019 at 03:23PM
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article reached 300 reads


W. Grabinski, D. Tomaszewski, L. Lemaitre and A. Jakubowski
Standardization of the compact model coding: non-fully depleted SOI MOSFET example
in Journal of Telecommunications and Information Technology

AbstractThe initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented. 

Keywords: Verilog-AMS, compact model coding, SOI MOSFET.

Fig: Approximation of the distribution of currents components
in the non-fully depleted SOI MOSFET.  

Monday, December 2, 2019

[mos-ak] [Final Program] 12th International MOS-AK Workshop; Silicon Valley, Dec.11 2019

12th International MOS-AK Workshop
(co-located with the IEDM and Q4 CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 12th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. 

The MOS-AK workshop program is available online:

Venue:
Silvaco 
2811 Mission College Blvd., 6th Floor 
Santa Clara, CA 95054

Online Registration is still open
(any related enquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special 
Solid State Electronics issue on compact modeling 

W.Grabinski on the behalf of International MOS-AK Committee

WG02122019

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#Alibaba’s growing #opensource stature - Eyes on APAC https://t.co/W3qBN15Wsr https://t.co/DoR0OSzOMh


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December 02, 2019 at 04:07PM
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[C4P] 50th ESSDERC / 46th ESSCIRC

Grenoble (F) Sept.14-18 2020
Call for Papers

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits. The level of integration for system-on-chip design is rapidly increasing. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers and system designers is necessary. While keeping separate Technical Program Committees, ESSDERC and ESSCIRC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both communities. Attendees registered for either conference are encouraged to attend any of the scheduled parallel sessions, regardless to which conference they belong.

TPC Tracks:

  • Advanced Technology, Process and Materials
  • Analog, Power and RF Devices
  • Compact modeling and process/device simulation
  • Joint TRACK: Memory devices and circuits towards non Von Neumann
  • Joint TRACK: Emerging Computing Devices and Circuits
  • Joint TRACK: Devices and circuits for Sensors, Optoelectronics and Display
  • Analog Circuits
  • Data Converters Circuits
  • RF & mmW Circuits
  • Frequency Generation Circuits
  • Wireless & Wireline Circuits & Systems
  • Digital Circuits & Systems
  • Power Management Circuits

Saturday, November 30, 2019

#paper A. Biswas, D. Ludwig and M. Cotorogea, "A New Computer-Aided Calibration Technique of Physics Based IGBT & Power-Diode Compact Models with Verilog-A Implementation," 2019 SISPAD, Udine, Italy, 2019, pp. 1-4. doi: 10.1109/SISPAD.2019.8870499 https://t.co/tM3k2ejZWs https://t.co/8bzoxK27ru


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November 30, 2019 at 06:12PM
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Friday, November 29, 2019

PhD Positions at Institute for Microelectronics/TU Wien

PhD Positions
on Characterization, Modeling and Circuit Simulation in Microelectronics
Institute for Microelectronics/TU Wien


The Institute for Microelectronics is a world leading research institute focused on the reliability of circuit components (especially transistors). In addition to conventional Si transistors, the behavior of SiC devices designed for high-power applications is also at the center of interest. The broad field of research conducted at the Institute of Microelectronics ranges from characterization, physical modeling and ab-initio simulations to compact modeling and circuit simulation. For the characterization of transistors, the Institute for Microelectronics has a modern laboratory equipped with commercial and custom-built measurement instruments. To explain the experimental data, elaborate physical models are developed and constantly improved. The models are directly incorporated into state-of-the-art device simulators, i.e. MinimosNT and Comphy. To perform computationally expensive simulations a modern computer cluster is while for circuit simulations Cadence and Synopsis spice simulators are available.

The institute is currently looking for highly talented and motivated young researchers to join the team in one of the following areas:
  • Physical modeling of silicon-carbide transistors
  • Single-defect characterization of low-noise silicon transistors
  • Development of custom-made measurement instruments
  • Circuit simulations using advanced implementation of reliability models in Verilog-A for SPICE
For the positions knowledge in one or more of the following areas is advantageous to complement our team:
  • C/C++ and Python
  • Semiconductor device physics
  • Circuit simulation
  • Implementation of new compact/physical models
  • Handling of device/circuit simulators
  • Design of discrete analog circuits and hardware/software solutions
  • Wafer probers and instruments for microelectronics
  • Keithley instruments and scripting language LUA
  • Measurement techniques in microelectronics (MSM, C(V), DLTS, charge pumping etc.)
As a teaching institution, knowledge transfer and close cooperation with students are very importance. The applicants should like to work together with students and supervise Master’s and Bachelor theses.

Starting Date: As soon as possible

Salary: Three-year positions (40hours/week) are in accordance with the salary regulations of the Austrian Science Fund. The gross annual salary is approximately EUR 40,300

Application Material: Please provide a detailed CV, your collective certificates, your Master’s thesis (weblink or PDF), and a single-page motivation letter (discussing relevant previous experience related to the desired skills and experiences) and summarize your motives for joining us.

Application: Please submit your application to jobs@iue.tuwien.ac.at.
Application Deadline: The positions will remain open until filled.

#paper J. A. D. Alamo, "Kudos to Our Golden Reviewers," in IEEE Electron Device Letters, vol. 40, no. 12, pp. 1891-1891, Dec. 2019. doi: 10.1109/LED.2019.2953249 https://t.co/dVuoduU4Di https://t.co/XAmjPMHry7

and some 2019 EDL Review Statistics:

from Twitter https://twitter.com/wladek60
https://t.co/dVuoduU4Di pic.twitter.com/XAmjPMHry7
— Wladek Grabinski (@wladek60) November 29, 2019

November 29, 2019 at 11:45AM
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Do want to do a #PhD with two of the best #companies in the #world and #receive highly #competitive salary package? More #information here: https://t.co/PyBHCi2z7y https://t.co/JXua7rZGAn #modeling https://t.co/2cd5mE3fJt


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November 29, 2019 at 11:31AM
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Thursday, November 28, 2019

X-FAB 车规级特色工艺技术研讨会 诚挚邀请您参加在深圳举办的技术研讨会,共同发掘合作新契机! https://t.co/hhv4z3m9dE #modeling https://t.co/kELItLlPMC


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November 28, 2019 at 01:42PM
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imec jobs Postdoctoral Researcher III-N MOCVD on Si https://t.co/S61MYHsymx #modeling https://t.co/nUH8nrjyUg


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November 28, 2019 at 11:35AM
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#Opensource software on the rise in #Africa [DW | 27.11.2019] https://t.co/S5jwjQgJZt https://t.co/J9RBSdFd95


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November 28, 2019 at 09:47AM
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Wednesday, November 27, 2019

Why do we contribute to #opensource software? https://t.co/Mygk0E4uPs https://t.co/J6TXnk7ZEz


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November 27, 2019 at 11:40AM
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Open PhD/PostDoc positions at the University of Pisa

device and 2D materials modeling, analog circuit design, 
power electronics, wireless sensors design

We are in the process of opening a few positions for PhD students and for Post Docs at the University of Pisa, in the fields of modeling of nanoscale electron devices, 2D materials, analog circuit design, power electronics design and wireless sensors for harsh environments. We are now asking for expressions of interest from perspective candidates.

I would be very grateful if you could forward this information to whom you think could be interested in applying.

Expressions of interest must be submitted by email, together with a CV and contact information by 31 Dec 2019 to giuseppe.iannaccone@unipi.it.

The available research topics are listed below. They are typically performed in the framework of a larger project within a European collaboration or of a bilateral project with an industrial sponsor.

1. Theoretical investigation of ultra-low-power nanoscale transistors and memories for large scale integrated circuits. This will include devices based on heterostructures of 2D materials. We are looking for candidates with strong background in Electrical Engineering and/or Physics.

2. Quantum engineering of materials and devices based on heterostructures of 2D materials. This activity is based on materials modeling with quantum chemistry methods and quantum transport modeling. We are looking for candidates with strong background in Physical Chemistry and/or Physics.

3. Design of low-power analog integrated circuits for analog hardware  accelerators of artificial intelligence (deep learning) algorithms and for new computing architectures. We are looking for candidates with strong background in Electrical Engineering.

4. Design of low-power mixed signal circuits for security hardware, such as physical unclonable functions and hardware security signatures. We are looking for candidates with strong background in Electrical Engineering.

5. Modeling of power devices based on GaN and SiC for performance and reliability optimization and model development. We are looking for candidates with strong background in Electrical Engineering and/or in Physics.

6. Design of highly efficient power management circuits and systems based on switched capacitors. Both circuits based on silicon technology, on SiC and on GaN will be considered. We are looking for candidates with strong background in Electrical Engineering.

PhD positions are for three years, Post Doc positions are initially for one year and might be renewed for up to four years. Positions of shorter duration (for visiting students/scholars or for MS  thesis projects) might be considered depending on the expertise of the candidate and the definition of a suitable subproject.

For additional information and specific information on the projects, please send an email to
Prof. Giuseppe Iannaccone
giuseppe.iannaccone@unipi.it

Tuesday, November 26, 2019

#paper W. Grabinski et al., "FOSS EKV2.6 Verilog-A Compact MOSFET Model," ESSDERC, Krakow, Poland, 2019, pp. 190-193. doi: 10.1109/ESSDERC.2019.8901822 https://t.co/rONWC5mTQE https://t.co/Sw8iobvIai


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November 26, 2019 at 09:13PM
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Friday, November 22, 2019

ADF Germany on Dec.4 | NI AWR Design Environment Seminar is FREE to attend. Lunch and refreshments are complimentary. https://t.co/NfuD8MRJFd #paper https://t.co/9uDP61kXwz


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November 22, 2019 at 11:01AM
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#FOSS Portal: Free and open-source software - Wikipedia https://t.co/EK2xk0walv #paper https://t.co/yVjzu6xKFw


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November 22, 2019 at 10:23AM
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Tuesday, November 19, 2019

[Conference Reports] 2019 Symposia on VLSI Technology and Circuits: Pushing the Limits of Semiconductors for a United and Connected World in IEEE SSC Magazine, vol. 11, no. 4, pp. 83-86, Fall 2019 doi: 10.1109/MSSC.2019.2939456 https://t.co/f51V2MT0S9 #paper https://t.co/pe9IUWra4X


from Twitter https://twitter.com/wladek60

November 19, 2019 at 08:47PM
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MOS-AK India #45395 is now published in IEEE Xplore

2019 IEEE Conference on Modeling of Systems Circuits and Devices 
(MOS-AK India) - #45395 
is now published in IEEE Xplore

Conference Record #45395

Dear Arifuddin Sohel, Desai UB, Govindacharyulu P.A, Wladek Grabinski, Venkatesh N

Congratulations! 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) has been posted to the IEEE Xplore digital library effective 2019-11-18.

Along with publication in IEEE Xplore, IEEE assures wide distribution of conference proceedings by providing abstracting and indexing information of all individual conference papers to worldwide databases. IEEE makes every reasonable attempt to ensure that abstracts and index entries of content accepted into the program are included in databases provided by independent abstracting and indexing services. Each abstracting and indexing partner makes its own editorial decision on what content to include. IEEE cannot guarantee entries are included in any particular database.

IEEE Meetings, Conferences & Events (MCE)
445 Hoes Lane, Piscataway, NJ 08854 USA
IEEE: Advancing Technology for Humanity

#paper J. Trommer, M. Simon, S. Slesazeck, W. M. Weber and T. Mikolajick, "Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs," ESSDERC 2019, Krakow, 10.1109/ESSDERC.2019.8901730 https://t.co/xGNhchlT24 https://t.co/RpSsxIkfe8


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November 19, 2019 at 05:51PM
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#paper K. Harrouche, R. Kabouche, E. Okada and F. Medjdoub, "High Performance and Highly Robust AlN/GaN HEMTs for Millimeter-Wave Operation," in IEEE Journal of the Electron Devices Society, vol. 7, pp. 1145-1150, 2019. doi: 10.1109/JEDS.2019.2952314 https://t.co/jNkb9EJ9Zn https://t.co/eVGvTeltX5


from Twitter https://twitter.com/wladek60

November 19, 2019 at 02:54PM
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#paper Faber, H., Anthopoulos, T.D. Adding a new layer to ‘more than Moore’. Nat Electron 2, 497–498 (2019) doi:10.1038/s41928-019-0329-8 https://t.co/0DGQKfB8PA https://t.co/BvjI3yrezw


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November 19, 2019 at 10:38AM
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#paper D. Mahajan, S. A. Albahrani, R. Sodhi, T. Eguchi and S. Khandelwal, "Physics-Oriented Device Model for Packaged GaN Devices," in IEEE TPE doi: 10.1109/TPEL.2019.2953060 https://t.co/fZEFBTrvHg https://t.co/aFN8iGGVDA


from Twitter https://twitter.com/wladek60

November 19, 2019 at 10:20AM
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Wednesday, November 13, 2019

Czochralski IEEE Milestone Event (Nov.15 2019) Hochschule für Technik und Wirtschaft Berlin University of Applied Sciences - HTW Berlin https://t.co/MzxFrFUbTf #paper https://t.co/4HZPQe4WeA


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November 13, 2019 at 11:32AM
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Monday, November 11, 2019

#paper F. Ávila Herrera, et al., "Leading-Edge Thin-Layer MOSFET Potential Modeling Toward Short-Channel Effect Suppression and Device Optimization," in IEEE JEDS doi: 10.1109/JEDS.2019.2948648 doi: 10.1109/EDTM.2019.8731246 https://t.co/7E9755kTOW https://t.co/vh1Zy9BifJ


from Twitter https://twitter.com/wladek60

November 11, 2019 at 08:32PM
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8th International NRNU MEPhI Workshop

VIII Международный научно-методический семинар по средствам автоматизированного проектирования интегральных микросхем для физического эксперимента совместно с компанией Cadence

it is our pleasure to announce the 8th International Workshop and school on computer aided design of integrated circuits for physical experiments to be held at NRNU MEPhI on November 25-27, 2019. The Workshop and school are organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information are available via site cad.mephi.ru.

Participation in the event is free of charge but registration is necessary.

E. Atkin, NRNU MEPhI event secretary,

Thursday, November 7, 2019

#paper Tengteng Lu, Zhen Li, Chao Luo, Jun Xu, Weicheng Kong, and Guoping Guo Characterization and Modeling of 0.18µm CMOS Technology at sub-Kelvin Temperature IEEE TED 2018 https://t.co/4lkzLP9jvz https://t.co/4QUcjG94EY


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November 07, 2019 at 03:27PM
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#paper Alam, M.N.K., Roussel, P., Heyns, M. et al. Positive non-linear capacitance: the origin of the steep subthreshold-slope in ferroelectric FETs. Sci Rep 9, 14957 (2019) doi:10.1038/s41598-019-51237-2 https://t.co/zWwduLz8pB https://t.co/6pXnXiXjW8


from Twitter https://twitter.com/wladek60

November 07, 2019 at 10:24AM
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Wednesday, November 6, 2019

#Google Is Helping Design an #OpenSource, Ultra-Secure #Chip. #OpenTitan is a so-called secure enclave based on open source that could shake up hardware security. https://t.co/Kaqgh5xTh0 https://t.co/CiL5HGuoJa


from Twitter https://twitter.com/wladek60

November 06, 2019 at 05:07PM
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N. Makris, M. Bucher, F. Jazaeri and J. Sallese, "CJM: A Compact #Model for Double-Gate Junction FETs," in IEEE JEDS. doi: 10.1109/JEDS.2019.2944817 https://t.co/3kba45imdB https://t.co/9WqLtmG2Jl


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November 06, 2019 at 05:03PM
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Tuesday, November 5, 2019

Si2 Compact Model Coalition Releases #SPICE #Model for Advanced IC Designs Twenty #CMC Members Benefit from 18-Month Access to New Standard Model https://t.co/yQyblGXwuG https://t.co/nUX9XtQESq


from Twitter https://twitter.com/wladek60

November 05, 2019 at 04:42PM
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#paper A. Rassekh, F. Jazaeri, M. Fathipour and J. Sallese, "Modeling Interface Charge Traps in Junctionless FETs, Including Temperature Effects," in IEEE TED, vol. 66, no. 11, pp. 4653-4659, Nov. 2019. doi: 10.1109/TED.2019.2944193 https://t.co/Ccg4wQtcG5 https://t.co/sBLZMVxcZo


from Twitter https://twitter.com/wladek60

November 05, 2019 at 02:41PM
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Monday, November 4, 2019

Futurehorizons Silicon Chip Industry Workshop Monday Nov 11 2019 Holiday Inn - Kensington Forum, 97 Cromwell Road, London https://t.co/YSQduuwVGn #paper https://t.co/AKkgonXxby


from Twitter https://twitter.com/wladek60

November 04, 2019 at 05:38PM
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#paper C. Prasad, "A Review of Self-Heating Effects in Advanced CMOS Technologies," in IEEE #TED, vol. 66, no. 11, pp. 4546-4555, Nov. 2019. doi: 10.1109/TED.2019.2943744 https://t.co/gAh4CAmDzu https://t.co/hyaCcsktDQ


from Twitter https://twitter.com/wladek60

November 04, 2019 at 04:55PM
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IEDM Panel Dec 10 Rest in Peace Moore’s Law, Long Live AI Moderator: Vijay Narayanan, IBM Panelists: Vivek De Intel Wilfried Haensch IBM Mike Henry Mythic Ron Ho Facebook Seongjun Park Samsung Dimitri Strukov UCSB Douglas Yu TSMC https://t.co/G3Yy5XpIPK #paper https://t.co/ffijI0TpMP


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November 04, 2019 at 11:09AM
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BCICTS 2019: 2b. High Frequency Characterisation Tuesday 8:00 AM - Blackbird A/B Session Chair: Breandán Ó hAnnaidh, Analog Devices Co-Chair: Sadayuki Yoshitomi, Toshiba https://t.co/hghKdEx9ty #paper https://t.co/SbPScPM0ee


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November 04, 2019 at 08:28AM
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6 remarkable features of the new #UN #opensource #initiative https://t.co/UCk0xLbtL5 https://t.co/uNGBipmWrx


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November 04, 2019 at 09:29AM
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Friday, November 1, 2019

#paper: Versatile model for the contact region of organic thin-film transistors A.Romeroab J.Gonzáleza M.J.Deenc J.A.Jiménez-Tejadab https://t.co/9wJwjKlu69 https://t.co/rFCp02RFEF


from Twitter https://twitter.com/wladek60

November 01, 2019 at 03:56PM
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#Indian #startups have raised a record $11.3B this year – TechCrunch https://t.co/qiJE1BnlV1 #paper https://t.co/yDn1H7aiPJ


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November 01, 2019 at 03:03PM
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Openings for Research Staff and PhD Scholarships Singapore-MIT Alliance for Research and Technology Low Energy Electronic Systems - Phase II 1 CREATE Way 09-01/02 CREATE Tower; 01-13 Enterprise Wing Singapore 138602 https://t.co/hUapbZCyAU #paper https://t.co/VNFXBjlxRY


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November 01, 2019 at 02:01PM
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Program to convert Sandia’s Albuquerque, N.M.-based fab from 150mm (6-inch) to 200mm (8-inch) wafer sizes. As part of the move, Sandia is converting its 0.35-micron (350nm) rad-hard process from 150mm to 200mm. The process is called CMOS7 https://t.co/JrWmF8BV0a #paper https://t.co/FJasxsp3s1


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November 01, 2019 at 01:55PM
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Wednesday, October 30, 2019

[mos-ak] [2nd Announcement and C4P] 12th International MOS-AK Workshop, Silicon Valley, DEC.11, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
12th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop which will be organized at Silvaco HQ on Dec. 11, 2019 (co-located with the IEDM and CMC Meetings)

Planned 12th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source (FOSS) TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2019
  • 2nd Announcement - Oct. 2019
  • Final Workshop Program - Nov. 2019
  • MOS-AK Workshop: Dec. 11, 2019
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)
WG301019

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2019 Heterogeneous Integration Roadmap (#HIR) Identifies Long-Term Technology Requirements to Inspire Collaboration in the Electronics Industry https://t.co/jaUzdB43xC #paper https://t.co/46jxVMGZ9O


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October 30, 2019 at 02:37PM
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Monday, October 28, 2019

6 signs you might be a Linux user - No.6 is: You have a passion for #opensource https://t.co/qccZsXhLBE


from Twitter https://twitter.com/wladek60

October 28, 2019 at 07:17PM
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#China has set up a new national #semiconductor fund of 204.2 #billion yuan ($28.9 billion), as it seeks to nurture its domestic chip industry and close the technology gap with the U.S. https://t.co/TkPFpKl4FG #paper https://t.co/VwRp13XNJU


from Twitter https://twitter.com/wladek60

October 28, 2019 at 01:47PM
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Friday, October 25, 2019

Wednesday, October 23, 2019

#Google scientists confirmed in a blog post that their #quantum #computer had needed just 200 seconds to solve a problem that they claim would take the world’s fastest supercomputer 10,000 years to complete. https://t.co/9OeWXZADKj #paper https://t.co/SjkB5JlZVv


from Twitter https://twitter.com/wladek60

October 23, 2019 at 03:46PM
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Synthesis of an optimized control signal for an improved EMC switching behavior of MOSFETs using a system characterization approach; C Krause, A Bendicks, T Dörlemann, S Frei; On-board Systems Lab, TU Dortmund University; EMC EuropeLab https://t.co/4PcH1vSYE7 #paper https://t.co/q8QWRoBWJI


from Twitter https://twitter.com/wladek60

October 23, 2019 at 10:13AM
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Thursday, October 17, 2019

3rd Symposium on Schottky barrier MOS devices was held on October 4th, 2019 at the Amphi Bloch, Orme de Merisiers-CEA, Gif-sur Yvette (F) https://t.co/xfFGcUx5gl #paper https://t.co/j0WbRdUWiJ


from Twitter https://twitter.com/wladek60

October 17, 2019 at 02:19PM
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Interlligent UK’s RF & Microwave Design Seminar |7 November 2019 | Møller Centre, Cambridge, UK” https://t.co/9wotXU6KZ5 #paper https://t.co/1chZlALkMb


from Twitter https://twitter.com/wladek60

October 17, 2019 at 02:11PM
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ESSCIRC/ESSDERC will take place in Grenoble from Sept 14th to 17th 2020, and the website in on-line. Watch-out for more. Looking forward to meet you there! https://t.co/GVb5q2YpYh #paper https://t.co/z2u5MSs5Ia


from Twitter https://twitter.com/wladek60

October 17, 2019 at 02:00PM
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Open Position - SiNANO - To work on the EPSRC funded project: Quantum Simulator for Entangled Nano-Electronics – The main aim is to go beyond the state of the art in device modelling of resonant tunnelling diode and single electron transistors. https://t.co/Vnul8S7GK7 #paper https://t.co/bPeudmiIaq


from Twitter https://twitter.com/wladek60

October 17, 2019 at 01:57PM
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Do you know "flash memory"? It's a very small and important thing that comes in smartphones. But where and how is it used? #flashmemory that supports everyone's convenient life. Let's explore secrets with this book! A series by Gakken Manga https://t.co/FdEgh40jE4 #paper https://t.co/6WuKG5D5Ir


from Twitter https://twitter.com/wladek60

October 17, 2019 at 10:15AM
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Wednesday, October 16, 2019

#Microsoft To Linux Community: ‘We Are An #OpenSource #Company’ https://t.co/YJk1TO4qpZ https://t.co/IagLDVJn1v


from Twitter https://twitter.com/wladek60

October 16, 2019 at 04:45PM
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Top Ten (+2) Companies For US Patents https://t.co/oeNFCdXZTj #paper https://t.co/SdScSwJB3c


from Twitter https://twitter.com/wladek60

October 16, 2019 at 10:23AM
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Tuesday, October 15, 2019

#Space #Radiation and Its Effects on #Electronic Systems https://t.co/MK7pzndDFL #paper https://t.co/p6BseiZGES


from Twitter https://twitter.com/wladek60

October 15, 2019 at 08:38PM
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Your #Future #RaspberryPiCPU Could Be Made From #Bacteria https://t.co/ABMbYvshSF #paper https://t.co/eloydfpGD9


from Twitter https://twitter.com/wladek60

October 15, 2019 at 08:33PM
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#TSMC to present 5nm CMOS, 22nm STT-MRAM at #IEDM https://t.co/alFyUIzWqK #paper https://t.co/ju4zRE0oyX


from Twitter https://twitter.com/wladek60

October 15, 2019 at 06:42PM
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[#paper] S.M. Mohd Hassan, A. Marzuki; Millimeter-wave CMOS Transistor Design and Modelling: A Review; IJSAR , 6(10), 2019; 01-14 https://t.co/yz0cTjl3DM https://t.co/QHDk8m7luW


from Twitter https://twitter.com/wladek60

October 15, 2019 at 09:04AM
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Monday, October 14, 2019

#OpenSource Hardware Trends, #Arm Takes a Different Tack https://t.co/ATXoMCU2qI https://t.co/uxhMZlgmRM


from Twitter https://twitter.com/wladek60

October 14, 2019 at 04:03PM
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#OpenHardware #CfP #OpenSource Computer Aided Design #CAD and Modeling devroom at FOSDEM 2020 https://t.co/woFwcGzemc https://t.co/auoGQMk45L


from Twitter https://twitter.com/wladek60

October 14, 2019 at 10:23AM
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[Open Hardware] [CfP] Open Source Computer Aided Design and Modeling devroom at FOSDEM 2020

We are pleased to announce the CfP for

Open Source Computer Aided Design and Modeling devroom 
at FOSDEM 2020
1-2 February 2020, Brussel, Belgium.

The devroom will take place on Saturday, 1 February 2020, at [ULB (Campus Solbosch)](https://www.openstreetmap.org/node/1632534522), in Brussels, Belgium.

We hope you'll join us for a full day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. We welcome any talk proposals about the creation of physical objects. Topics of interest include, but are not limited to:

- Circuit Design
    * Printed circuit board design tools
    * Circuit simulation
- 3d modeling and analysis
    * Solid modeling tools
    * Meshing, modeling and transforming physical representations
    * Finite element analysis
- 3d printing
    * 3d slicing tools
    * Motor control
- Machine design and integration
    * Open Hardware projects
    * ECAD/MCAD integration
    * Thermal analysis
    * Wire modeling
- Physical Model Data storage
    * Data representation and optimization
    * Version control in hardware data storage
    * Collaborative and team-based hardware design techniques

Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.

The submission process
Please submit your proposals at
https://penta.fosdem.org/submission/FOSDEM20 before 20 November 2019.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.

Please include the following information with your submission:

  • Abstract
  • Preferred Session length
  • Speaker bio
  • Link to any hardware / code /slides for the talk

When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Open Source Computer Aided Design and Modeling" in the track drop-down menu. Otherwise your proposal may go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers.

Important dates
- Call for papers available: 13 October 2019
- Call for participation closes: 20 November 2019
- Devroom schedule available: 15 December 2019
- Devroom day: Saturday 1 February 2020 (09:00 to 17:00)

Recordings
The talks will be recorded and live-streamed during FOSDEM20. The
recordings will be published under the same licence as all FOSDEM
content (CC-BY). Only presentations will be recorded, not informal
discussions and whatever happens during breaks between presentations.
By agreeing to present at FOSDEM, you give permission to be recorded.
Please contact us if you would like to request an exception to the
recording policy for your talk.

Mailing list
Feel free to subscribe to the [Open Source Computer Aided Design and
Modeling mailing list](https://lists.fosdem.org/listinfo/open-hardware-devroom)
to submit ideas, ask questions and generally discuss about the event.
_______________________________________________
open-hardware-devroom mailing list
open-hardware-devroom@lists.fosdem.org
https://lists.fosdem.org/listinfo/open-hardware-devroom

Friday, October 11, 2019

#GaN as a key material for establishing a #sustainable society by Hiroshi Amano is a Japanese physicist, engineer, and inventor, awarded the 2014 #Nobel Prize in Physics 14 October 2019 | 12:15pm-1pm | EPFL Forum Rolex https://t.co/ti6j4BvrCW #paper https://t.co/XBoGbSAeps


from Twitter https://twitter.com/wladek60

October 11, 2019 at 08:39PM
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Thursday, October 10, 2019

article with 200 reads


Wladek Grabinski, Matt Bucher,Jean-Michel Sallese and François Krummenacher
Journal of Telecommunications and Information Technology 2000(3-4):31-42, March 2000



Mukku P.K., et al. (2020) Recent Trends and Challenges on Low-Power FinFET Devices. In: Smart Intelligent Computing and Applications. Smart Innovation, Systems and Technologies, vol 160. https://t.co/Nzgcx7NKME #paper https://t.co/OEqyhNfDKC


from Twitter https://twitter.com/wladek60

October 10, 2019 at 11:21AM
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#UNICEF Launches #Cryptocurrency Fund to Back #OpenSource Technology https://t.co/bLVBN5LLVt https://t.co/EZTMhieghQ


from Twitter https://twitter.com/wladek60

October 09, 2019 at 11:32PM
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