Monday, June 17, 2019

[open source paper] Open-source circuit simulation tools for RF compact semiconductor device modelling



Open-source circuit simulation tools for RF compact semiconductor device modelling
Wladek Grabinski (editor), Mike Brinson, Paolo Nenzi, Francesco Lannutti, Nikolaos Makris, Angelos Antonopoulos and Matthias Bucher
September 2014
DOI: 10.1002/jnm.1973

SUMMARY: MOS-AK is a European, independent compact modelling forum created by a group of engineers, researchers and compact modelling enthusiasts to promote advanced compact modelling techniques and model standardization using high level behavioral modelling languages such as VHDL-AMS and Verilog-A. This invited paper summarizes recent MOS-AK open source compact model standardization activities and presents advanced topics in MOSEFT modelling, focusing in particular on analogue/RF applications. The paper discusses links between compact models and design methodologies, finally introducing elements of compact model standardization. The open source CAD tools: Qucs, QucsStudio and ngspice all support Verilog-A as a hardware description language for compact model standardization. Latter sections of this paper describe a Verilog-A implementation of the EKV3 MOS transistor model. Additionally, the simulated  RF model performance is evaluated and compared with experimental results for 90nm CMOS technology. 

KEYWORDS: CAD; GNU; Qucs; QucsStudio; ngspice; compact modeling; EKV3; RF; MOSFET; Verilog-A

Friday, June 14, 2019

[book] POWER/HVMOS Devices Compact Modeling


 


POWER/HVMOS Devices Compact Modeling 
Wladyslaw Grabinski and Thomas Gneiting
Editors

Book 7 Citations;   119 Readers;   2 Reviews;   6k+ Downloads
DOI: 10.1007/978-90-481-3046-7

Since its online publication on Jun 10, 2010, there have been a total of 6452 chapter downloads for your eBook on SpringerLink. The table below shows the download figures for the last years:

YearUsage
2018
656
2017
766
2016
843
2015
912
2014
1333
2013
658
2012
420
2011
401
2010
463

Thursday, June 13, 2019

#XFAB and #Efabless developed the #opensource RISC-V microcontroller, called Raven, in less than three months https://t.co/2kEZVEEZum https://t.co/oWoYlMjk4o


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Tuesday, June 11, 2019

[mos-ak] [Final Program] 4th Sino MOS-AK Workshop Chengdu, June 20-22, 2019

4th Sino MOS-AK Workshop 
UESTC 电子科技大学 Chengdu, June 20-22, 2019 

Together with local host Prof. Yuhang Xu, UESTC 电子科技大学 and coordinating organizer Dr. Min Zhang, XMOD as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 4th Sino MOS-AK Workshop at UESTC 电子科技大学 Chengdu, between June 20-22, 2019

After successful series of MOS-AK workshops in Shanghai, Hangzhou and Beijing, our next scheduled, subsequent 4th Sino MOS-AK Workshop at UESTC 电子科技大学 Chengdu, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <http://www.mos-ak.org/chengdu_2019/> (see also below)

Venue:
会议场所:电子科技大学图书馆求实厅(图书馆旁博物馆二楼)
UESTC Library Realistic office (the second floor of the museum next to the library)
<http://www.xmodtech.cn/Workshop-Address>

Online Registration is still open
 (any related enquiries can be sent to Yuan Yao mobile:13086679508)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Recommended hotels
酒店:成都新希望高新中心假日酒店
Hotel: Holiday Inn Chengdu High-Tech Center
地址:中国四川省成都市郫都区西芯大道1号附1号
Address: No.1-1 Xixin Avenue Pidu District Chengdu China

Prof. Yuhang Xu, UESTC
Dr. Min Zhang, XMOD
and W.Grabinski
WG110619

Final MOS-AK Program Announcement
20th JUNE MOS-AK Tutorial Day
9:00-11:45 Modeling of Silicon-Germanium Heterojunction Bipolar Transistors for mm-Wafer circuits
Andreas Pawlak
Infineon AG
13:00-16:15 1. Radar frontends for ranging and speed measurements operating at 24GHz, 60GHz and 122GHz ISM frequency bands 
2. Radar frontends for MIMO radars operating at 24GHz, 60GHz, 122GHz and 245GHz ISM frequency bands
Wojciech Debski 
Silicon Radar GmbH
21st JUNE 1st Day of MOS-AK Workshop
8:30-9:20 WORKSHOP CHECK IN 
9:30-9:35  MOS-AK Opening Speech
TBD
UESTC
9:35-9:40 MOS-AK Review & Outlook
Min Zhang, Wladek Grabinski
XMOD, MOS-AK
9:40-10:25 The Model and Algorithm Prototyping Platform (invited talk)
Jaijeet Roychowdhury
U.C.Berkely
10:25-10:50 Device modeling Eco-system Driven by Learning-based algorithms
Yanfeng Li
Platform-DA
10:50-11:05 Tea break
11:05-11:50 Simulation and Modeling of Dynamic Systems with Time Varying device Characteristics (invited talk)
Masun Chan
HKUST
11:50-12:00 Group photo
12:00-13:30 Lunch 
13:30-14:00 Advanced TFT Modeling Techniques for GOA Driver Circuit Design Optimization (invited talk)
An-Thung Cho, Lifeng Wu
HuaDa Empyrean software, Chongqing HKC
14:00-14:25 Active Device Channel spice thermal modeling and parameter extraction 
Fujiang Lin
USTC
14:25-14:50 Simulation-Based Reliability Analysis for Advanced Designs and Applications
Xugang Shen
Synopsys, Inc.
14:50-15:10 Tea break
15:10-15:55 Silicon intergrated magneto-optical nonreciprocal photonic devices (invited talk)
Lei Bi
UESTC
15:55-16:20 An Analysis of DG SOI MOSFET Modeling and Simulation with PSP, BSIM-IMG and HiSIM_SOTB
GuoFang Wang, Jun Liu
HDU
16:20-16:45 TCAD-Based Statistical Modelling Methodology for Nanoscale FinFET Variability
Guo Ao
ICRD
16:45-17:10 Characterization and Modeling of the Reverse behavior of a Vertical Power MOSFET
Lixi Yan
Stuttgart University
17:10-17:35 An Industry Standard Model Including Fast and Extended Range Core with Improved Mobility and Noise effect
Chetan Kumar Dabhi
IITK
17:35-18:30MOS-AK Compact Modeling Round-Table Forum
Min Zhang, Wladek Grabinski
XMOD, MOS-AK
18:30-20:00 MOS-AK Gala Dinner
22nd JUNE 2nd Day of MOS-AK Workshop
8:30-9:20 WORKSHOP CHECK IN 
9:30-10:15 Negative Capacitance FET and Nanowire/Nanosheet FET modeling (invited talk)
Yogesh Chauhan
IITK
10:15-10:40 An Simulation Platform for IGBT Module Electrothermal Analysis
Chen Shen
Cogenda
10:40-11:00 Tea break
11:00-11:45 Artificial Neural Networks for Microwave Modeling and Design (invited talk) 
Qijun Zhang
Carleton University
11:45-12:10 A transient ionizing Radiation Spice model for PDSOI MOSFET
Jianhui Bu
IME Chinese Academy
12:10-13:30 Lunch 
13:30-14:15 Quasi-physical Zone division (QPZD) model for microwave wide-band-gap semiconductor technology (invited talk)
Yuehang Xu
UESTC
14:15-14:40 RF GaN Device model survey and model parameter extraction flows
Raj Sodhi
Keysight
14:40-15:05 Charaterization and modeling of Memory effects for GaN HEMTs
ZhiFu Hu 
HSRI
15:05-15:25 Tea break
15:25-15:50 Key Technology to GaN-based mm-Wave Devices and MMIC's (invited talk)
Xiaohua Ma
Xidian University
15:50-16:15 A Dimension-Reduction Method for the Thermal Modeling of InGaP/GaAs HBTs
Wenrui Hu, Yongxin Guo
NUS
16:15-16:40 DC and RF Modeling of CMOS Schottky Diodes 
Wenyuan Zhang, Yan Wang
Tsinghua University
16:45-17:10 RF GaN Device modeling for MMIC design
Chujun Wang
CETC 55
17:10-17:15 MOS-AK 2020
Min Zhang, Wladek Grabinski
XMOD, MOS-AK
End of the MOS-AK Chengdu Workshop

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S. Li etal. A Buffer-Less Wideband Frequency Doubler in 45nm SOI with Transistor Multi-Port Waveform Shaping Achieving 25% Drain Efficiency and 46-89GHz Instantaneous Bandwidth in IEEE Solid-State Circuits Letters. doi: 10.1109/LSSC.2019.2918943 https://t.co/buZkWbSAvo #paper https://t.co/dEPj5OG5Vb


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June 11, 2019 at 02:22PM
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Monday, June 10, 2019

#Medicine needs to embrace #opensource https://t.co/zEIjyMOcht https://t.co/W4RClFXRuv


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June 10, 2019 at 09:07PM
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#Qualcomm backs #Sifive, #opensource alternative to ARM - Gizmochina https://t.co/vuBycJuVrG


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June 10, 2019 at 07:29PM
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Where Open Hardware Is Today | FOSS Force by @bbyfield. #paper https://t.co/dBp48r3axq


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June 10, 2019 at 01:16PM
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Thursday, June 6, 2019

You Don’t Need That Bulky CRT #Oscilloscope Anymore https://t.co/UFW4yYoPcS #opensource https://t.co/CqVdDKnPQr


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June 06, 2019 at 12:06PM
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Modeling Emerging Semiconductor Devices for Circuit Simulation https://t.co/QMvNfZ9vsl #paper https://t.co/1gWFMFxzmq


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June 06, 2019 at 10:03AM
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[paper] Novel General Compact Model Approach

A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond

Qiang Huo, Zhenhua Wu, Weixing Huang, Xingsheng Wang, Senior Member, IEEE, Geyu Tang, Jiaxin Yao, Yongpan Liu, Feng Zhang, Ling Li, and Ming Liu, Fellow,IEEE

Abstract: This work presents a novel general compact model for 7nm technology node devices like FinFETs. As an extension of previous conventional compact model that based on some less accurate elements including one-dimensional Poisson equation for three-dimensional devices and analytical equations for short channel effects, quantum effects and other physical effects, the general compact model combining few TCAD calibrated compact models with statistical methods can eliminate the tedious physical derivations. The general compact model has the advantages of efficient extraction, high accuracy, strong scaling capability and excellent transfer capability. As a demo application, two key design knobs of FinFET and their multiple impacts on RC control ESD power clamp circuit are systematically evaluated with implementation of the newly proposed general compact model, accounting for device design, circuit performance optimization and variation control. The performance of ESD power clamp can be improved extremely. This framework is also suitable for pathfinding researches on 5nm node gate-all-around devices, like nanowire (NW) FETs, nanosheet (NSH) FETs and beyond.

Index Terms: General compact model, FinFET, ESD power clamp, 7 nm technology node and beyond.

Fig. (A) The schematic of partial parameters of FinFET. (B) Key design rules of 7nm node FinFET as according to [1]. 

Access: https://arxiv.org/ftp/arxiv/papers/1905/1905.11207.pdf

REF: [1] S. Narasimha et al.“A 7nm CMOS technology platform for mobile and high performance compute application,” IEEE International Electron Devices Meeting (IEDM), Dec. 2017, pp. 29.5.1-29.5.4, doi: 10.1109/IEDM.2017.8268476.

[paper] Analogue and RF performances of Fully Depleted SOI MOSFET

Jean-Pierre Raskin1
1Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université catholique de Louvain (UCLouvain), Place du Levant, 3, Maxwell Building, bte L5.04.04, office B.327, B-1348 Louvain-la-Neuve, Belgium
ABSTRACT. Performance of RF integrated circuit (IC) is directly linked to the analogue and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today Partially Depleted (PD) SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance operating at lower power consumption and in the millimeter-waves range. Fully Depleted (FD) SOI MOSFET is a quite promising candidate for the development of these future wireless communication systems. Most of the reported data on FD SOI concern their digital performance. In this paper, their analogue/RF behaviour is described and compared with bulk MOSFETs. Self-heating issue, non-linear behaviour as well as high frequency performance at cryogenic temperature for FD SOI MOSFET are discussed. Finally, a brief summary of the published RF and millimeter-waves ICs based on FD SOI technology is presented.

KEYWORDS. Silicon-on-Insulator (SOI), Fully Depleted (FD), high frequency behaviour, Radio Frequency (RF), millimeter-waves, analogue/RF performances, self-heating, non-linear behaviour, cryogenic temperature, Integrated Circuits (ICs).

FIG: Simplified cross section of FD SOI nMOSFET with back-gate (BGN).


ACCESS: http://www.openscience.fr/IMG/pdf/iste_componano19v2n1_5.pdf

Friday, May 31, 2019

As IEEE enters U.S/Huawei fray, Chinese editorial board member resigns https://t.co/piWApiqC0F #paper


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May 31, 2019 at 01:28PM
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Tuesday, May 28, 2019

#Taiwan #Startup Plan Emulates #MIT, #Stanford https://t.co/BIMmAKI9iu #paper https://t.co/w1Qvi0LmT7


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May 28, 2019 at 09:19AM
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#Xyce Binaries, building and more information including documentation, build instructions and binary executables—see the Xyce Homepage at #Sandia National Laboratories.” https://t.co/AhuZrAsuH7 #paper https://t.co/MGuIcsBdnx


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May 28, 2019 at 08:54AM
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Monday, May 27, 2019

15 Best Free Linux #Bioinformatics Tools https://t.co/DalDhCPate #paper


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May 27, 2019 at 03:29PM
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Friday, May 17, 2019

X. Liu, T. Ytterdal, V. Y. Kachorovskii and M. S. Shur, "Compact Terahertz #THz #SPICE/ADS Model," in IEEE Transactions on Electron Devices, vol. 66, no. 6, pp. 2496-2501, June 2019. doi: 10.1109/TED.2019.2911485 #paper


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May 17, 2019 at 04:00PM
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Thursday, May 16, 2019

Bashir, MA, Wu, Y, Liu, J, Zhao, C, Tang, H, Kang, K. A millimeter‐wave #mmW scalable small signal model of #RF #CMOS transistor against number of fingers. Int J Numer Model. 2019;e2608. https://t.co/bs9Keh4m6Y #paper https://t.co/yJkhFNoL7s


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May 16, 2019 at 08:30PM
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Fable: The #MOS #Pioneer https://t.co/IVvGuIXw63 #paper https://t.co/PQv80O8jiF


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May 16, 2019 at 08:21PM
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Saturday, May 11, 2019

European Commission #EC #conference dedicated to #OpenSource https://t.co/Y9VF24fF5K


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May 11, 2019 at 02:31PM
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#Intel to Introduce Chips Based on #7nm in #2021 https://t.co/4xEVHZwdoo #paper


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May 11, 2019 at 01:58PM
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Friday, May 10, 2019

Three Reasons Why You Should NOT Miss #56DAC https://t.co/B9emrCspQm #paper


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May 10, 2019 at 05:51PM
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Thursday, May 9, 2019

#RedHat: #IBM Ownership Won't Change #opensource Mission https://t.co/G8zDNCewyk https://t.co/2KIDNnVpvK


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May 09, 2019 at 08:28PM
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Tuesday, May 7, 2019

The state of #opensource in South Korea https://t.co/2dNMJq9ot9


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May 07, 2019 at 03:29PM
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Sunday, May 5, 2019

X. Liu, T. Ytterdal, V. Y. Kachorovskii and M. S. Shur, "Compact Terahertz SPICE/ADS Model," Abstract: We describe a compact THz SPICE/ADS model based on the extended EKV model with channel segmentation but accounting for the new physics https://t.co/sVhj5RlwHh #paper https://t.co/N0dj9AIlWn


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May 05, 2019 at 12:16PM
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Thursday, May 2, 2019

Atomera adds dopant engineering to boost #transistor performance using Mears Silicon Technology (#MST) https://t.co/OC05r0eGKd #paper https://t.co/81WNPzuMHX


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May 02, 2019 at 05:52PM
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#RF #GaN 2019 - Patent Landscape Analysis - i-Micronews https://t.co/mTVWGKo0pc #paper https://t.co/EX83lTOEQF


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May 02, 2019 at 09:25AM
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Tuesday, April 30, 2019

IMEC, Leti and Fraunhofer have agreed to join forces with the SEMI industry association to drive nanoelectronic roadmaps and standards. https://t.co/HVT0PmaowD #paper https://t.co/ZPXSDAZ5FL


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April 30, 2019 at 04:18PM
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No company is ready to dethrone #TSMC from #1 spot” https://t.co/BNUjnLpq5f #paper https://t.co/fU2THb8wov


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April 30, 2019 at 01:31PM
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Monday, April 29, 2019

P. Kushwaha et al., "Characterization and Modeling of Flicker #Noise in #FinFETs at Advanced Technology Node," in IEEE Electron Device Letters. doi: 10.1109/LED.2019.2911614 https://t.co/RuzIYlIOiL #paper https://t.co/y7lpjHI02W


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April 29, 2019 at 09:32AM
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Friday, April 26, 2019

A Compact Model for Border Traps in Lateral MOS Devices with Large Channel Resistance https://t.co/p9sOA4A8Ee #paper


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April 26, 2019 at 09:14PM
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A Quick #TSMC 2019 Tech Symposium Overview #FinFET https://t.co/NzINOJTciz #paper


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April 26, 2019 at 02:29PM
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Thursday, April 25, 2019

H. Cortes-Ordonez, S. Jacob, F. Mohamed, G. Ghibaudo and B. Iniguez, "Analysis and Compact Modeling of Gate Capacitance in Organic Thin-Film Transistors," in IEEE Transactions on Electron Devices, vol. 66, no. 5, pp. 2370-2374, May 2019. https://t.co/IHtWBBiqiI #paper https://t.co/Ryp6FJ6TlS


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April 25, 2019 at 09:34PM
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#Emerging #memories https://t.co/Iv50OpzJGO #paper


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April 25, 2019 at 07:20AM
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Wednesday, April 24, 2019

#TSMC Steps Through 7, 6, 5, #Moore https://t.co/qauTuVuRNu #paper


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April 24, 2019 at 07:01PM
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Controlling #IC Manufacturing #Processes For #Yield https://t.co/Jkaagd6fcH #paper


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April 24, 2019 at 06:57PM
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Silicon Valley #SOI Symposium a Huge Success. Key #Takeaways (Part 1) Here. https://t.co/gDG4fZGnC3 #paper


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April 24, 2019 at 07:18AM
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Tuesday, April 23, 2019

Changes in the Editorial Board of the IEEE Transactions on Electron Devices (#TED)” https://t.co/IdvKWuxOyh #paper https://t.co/JslqPEuBE6


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April 23, 2019 at 08:04PM
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Sunday, April 21, 2019

Wednesday, April 17, 2019

Is #ETHZ’s genetically engineered ‘biological dual-core processor’ actually a pair of gates? https://t.co/4swqZuKfk6 #paper https://t.co/OMlQyV8sTs


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April 17, 2019 at 10:10PM
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#MEMS research is better #together #Japan https://t.co/chDClsOcjZ #paper https://t.co/7zUt4UisGI


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April 17, 2019 at 09:39PM
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W. Wang, P. Yu and Y. Jiang, "#Compact #Model for Digital Circuits Operating Near Threshold in Deep-Submicrometer MOSFET," in IEEE TED doi: 10.1109/TED.2019.2905895 https://t.co/ST4J8u2pRY https://t.co/3bYTnxKi3c


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April 17, 2019 at 07:51PM
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Monday, April 8, 2019

Symposium on Schottky Barrier MOS devices

Towards neuromorphic and quantum computing applications” 
October 4, 2019, Paris (F)
organized by EDS French Chapter & Universite Paris-Sud

A symposium on Schottky Barrier MOS (SB-MOS) devices is planned for October 4th at the new Center for Nanoscience and Nanotechnology laboratory in Palaiseau, France. This is the third meeting of an enthusiastic group of Schottky barrier researchers and this year it is sponsored by LabexNanoSaclay, the IEED EDS French chapter, the Robert Bosch GmbH and Silvaco Inc.


This year the theme of the symposium is “Towards neuromorphic and quantum computing applications” organized by Dr. Laurie Calvet (C2N, Palaiseau, France), Dr. Francesca Chiodi (C2N, Palaiseau, France), Dr. Mireille Mouis (IMEP-LAHC, Grenoble INP, France) and Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany) and the staff at the Centre of Nanoscience and Nanotechnology at the Université Paris-Sud. 

The symposium starts on October 4th at 9:00 am and the following speakers have confirmed their invitations: Prof. Benjamin Iniguez (DEEEA, Universitaet Rovira I Virgili), Dr. Laurie E. Calvet (C2N, CNRS-Université Paris-Sud), Dr. Mike Schwarz (Robert Bosch GmbH, NanoP THM, Germany), Dr. David Green / Dr. Ahmed Nejim (Silvaco Inc.), Dr. John Snyder (JCAP, LLC), Dr. Francesca Chiodi (C2N, CNRS-Université Paris-Sud), Dr. François Lefloch (CEA, Grenoble), Dr. Fabrice Nemouchi (CEA, Grenoble).



Sunday, April 7, 2019

Restoring An #HP4276A LCZ Meter From The 1980s https://t.co/K9LM1c5Ao0 #paper


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April 07, 2019 at 05:10PM
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Saturday, April 6, 2019

First #opensource #MIPS code is released https://t.co/0NbQasWuVx


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April 06, 2019 at 10:19PM
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2019 CAD-TFT Workshop in Tarragona (Spain)


2019 International Workshop on
Computer Aided Design of Thin-Film Transistors (CAD-TFT)
University Rovira i Virgili, Tarragona (Catalonia) Spain
July 8-10, 2019

The 2019 CAD-TFT Workshop will provide a forum for discussions and current practices on compact TFT modeling and to promote research on CAD techniques at all levels (TCAD, compact modelling, circuit & system design) for TFT technologies. It is also intended to promote the training of students, young researchers and engineers and to build international, academic-industry, and cross-level collaborations to evoke new applications of TFT technologies. The workshop will technically be co-sponsored by the IEEE EDS Compact Modeling Technical Committee, in joint collaboration with the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV) and Silvaco Europe Ltd. An EDS Mini-Colloquium will take place on July 8. 

The chair of the 2019 CAD-TFT Workshop and the EDS Mini-Colloquium is Prof. Benjamin Iñiguez, from URV.

 
A partial list of the areas of interest includes:

· Physics of TFTs and operating principles
· Compact TFT device models for circuit simulation
· Model implementation and circuit analysis techniques
· Model parameter extraction techniques
· TFT design for displays and emerging applications

█ Abstract Submission Deadline: May 1, 2019

Please note, abstracts will be considered for the conference even after the official submission deadline.


Prospective participants should email a no-more-than 100-word abstract to: benjamin.iniguez@urv.cat


Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most  important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.