Saturday, June 30, 2007

Experiment on Scientific Communications

Well, today we can celebrate our first six months of existence in this blog. I'd like to take advantage of this fact to propose to all the gentle readers (as the dear old Dr. Isaac Asimov said) to leave a comment on what do you think about the utility of a blog as a method for scientific communication. I mean: there are the traditional ways (Conferences, Workshops, and so on), but the internet offers us many new possibilities, blogging being only one among others. Do you think that blogging can be useful? What do you think about other possibilites? Do you think that you could organize (for instance) a Conference using SecondLife? Do you think that webcasts (either from IEEE or other organizations) are useful or are they somewhat marginal?

Thanks (in advance) for your (kind) comments!

Friday, June 29, 2007

Threshold voltage and subthreshold swing models in undoped Double-Gate MOSFETs

Accurate models for the threshold voltage and subthreshold swing in nanoscale MOSFETs should be based forom a 2D electrostatic analysis.

In doped devices, the carrier concentration is usually neglected in such electrostatic analysis, that is carried out in the subthreshold region, where the doping concentration is much higher than the carrier concentration.

However, in the case of undoped DG MOSFETs, the carrier concentration may be not negligible for that electrostatic analysis, in particular in the threshold regime.

A recent paper was presenting the first complete threshold voltage and subthreshold swing models for nanoscale DG MOSFETs, by considering the carrier concentration in Poisson's equation:

El Hamid, H. A.; Roig Guitart, J.; Iniguez, B., "Two-Dimensional Analytical Threshold Voltage and Subthreshold Swing Models of Undoped Symmetric Double-Gate MOSFETs," IEEE Trans. on Electron Devices, vol. 54, no. 6, pp. 1402-1408, June 2007

This model includes the threshold voltage roll-off, the DIBL and the subthreshold swing degradation.

This paper improves the model developed by Qian Chen et al., also published in IEEE Transactions on Electron Devices, in which the carrier concentration was considered, but the model development was done only at low drain voltage; the DIBL and the subthreshold swing degradation with the drain voltage were ignored:

Q. Chen, E. M. Harrell, J. D. Meindl, "A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs," IEEE Transactions on Electron Devices, vol. 50, no. 7, pp. 1631-1637, July 2003

Wednesday, June 27, 2007

IEEE papers

Well, another update on some IEEE publications. I've got three papers quite related to compact modeling:

"An analytical Compact Model for Nanowire FET", by B.C. Paul et alter, in IEEE Trans. on Electron Devices.

"Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs", by O. Moldovan et alter, also in IEEE Trans. on Electron Devices.

"Limits of Performance Gain of Aligned CNT Over Randomized Network: Theoretical Predictions and Experimental Validation", by N. Pimparkar et alter, in IEEE Electron Device Letters.

Monday, June 25, 2007

International Semiconductor Device Research Symposium'07

The biennial International Semiconductor Device Research Symposium will take place on December 12-14, on Maryland, USA.
This Symposium focuses on exploratory research in electronic and photonic materials and devices. Areas such as novel device concepts, processing technologies, advanced modeling, nanotechnology, nanoelectronics, wide band-gap semiconductors, MEMS materials and devices, oxides and dielectrics, magnetic materials and devices, organic and polymer opto-electronic materials and devices, ultra high frequency devices & RF effects, and high power-high temperature devices are included. The Symposium brings together diverse participants in multidisciplinary areas, and provides a forum for extended personal scientific interaction for engineers, scientists, and students working in the field of advanced electronic materials and device technologies.
Moreover, it has a topic dedicated to Compact (and Distributed) Modeling, so I guess it can be interesting to go there and have a look. Another interesting advantage of presenting a paper at ISDRS 2007 is that it is held just after IEDM, and very close to the IEDM venue (Washington DC), so researchers who present papers at ISDRS can attend before IEDM and then go to ISDRS. This is why ISDRS is held every two years, when ISDRS is held at Washington DC.
In fact, ISDRS an alternative to IEDM, especially for university teams, in the sense that IEDM is more industrial oriented, while ISDRS focuses more on device properties research and device modeling.

Wednesday, June 20, 2007


The 2007 IEEE Custom Integrated Circuits Conference (CICC) will take place on September 16-19, 2007, at the DoubleTree Hotel in San Jose, California, in the heart of Silicon Valley.

CICC is one of the top conferences on circuit design. The main topics of the conference are Analog Circuit Design, Digital Circuit amd SoC/ASIP/SiP Design and Methodology, Custom Applications and Power Management, Sensors, MEMs, Manufacturing and Test, Wireless Designs, Wireless Communications, Programmable Devices, Embedded Memory, Signal and Data Processing and Simulation and Modeling, including Compact Device Modeling.

CICC 2007 will intend to show the latest developments in Compact Modeling, for the training of designers and to facilitate a close interaction between designers and compact model developers.

I will present an invited paper at CICC 2007, which will present charge based modeling techniques for multiple-gate MOSFETs.

Not all is business in San Jose. It is a wonderful city with many other attractions: golf courses, wineries, and for hikers and nature lovers, the Alum Rock Park. Besides, San Jose, which is called the "Safest Big City in America", has an intense nightlife, with many dance clubs and sports bars.


The 21st IEEE International Conference on Microelectronic Test Structures (ICMTS) will be held in Edinburgh, Scotland, March 24-27 2008.

ICMTS has become a well established conference addressing topics such as test structures, material, process and device characterization techniques, compact device model parameter extraction and reliability analysis.

In 2008 ICMTS will be organized by the University of Edinburgh. Extended abstracts should be submitted by September 14 2007.

From my experience, ICMTS is a very interesting forum to present new methods to extract parameters of compact device models. In the recent times there has been emphasis on parameter extraction from RF measurements. Also ICMTS allows a very useful interaction between researchers coming from characterization teams and compact modeling teams. On the other hand, I want to highlight that ICMTS uses to have a very nice social programme.


The third edition of the International Conference on Organic Electronics (ICOE) was held at the High-Tech Campus in Eindhoven, The Netherlands, June 04-07 2007

ICOE arised as an initiative of the European Framework 6 IST Programme through the Integrated Project 'PolyApply'. This conference addresses all issues related to organic electronics, such as materials, manufacture, Organic Thin Film Transistors (OTFTs), OLEDs, PV devices, organic circuit design, and organic device modeling.

Many interesting papers were presented, mostly from Europe. It should be mentioned that there are many European teams currently working on organic electronics.

There were not many paper dealing with device modeling, although there were interesting. We can highlit the papers entitled "Modeling Traps in ultrathin pentacene transistors," by A. D. Geiser, A. von Mühlenen, N. Errien and L. Zuppiroli (EPFL, Lausanne, Switzerland), "Paper Charge Injection Model for Organic Light-emitting Diodes," by L. Li, G. Meller, and H. Kosina (Institute for Microelectronics, TU-Wien, Wien, Austria).

One paper presented a compact model for OTFTs, assuming a transport mechanism based on a quasi-drift-quasi-diffusion theory.. It was entitled "Analytical modelling of TFTs and diodes on small molecule organic semiconductor devices," by S. Prior, D.Donaghy, W.Eccleston (Organic Electronics Group, University of Liverpool, Liverpool, UK), and B. Stablober and A. Haase (Joanneum Research, Austria).

The invited speakers were also top scientists in Organic Electronics. Sergei Baranovski (Philipps-University Marburg, Germany) presented a theory of the charge transport in disordered organic materials. Dan Frisbie (University of Minnesota, USA) made a talk about the Polymer Electrolyte-Gated Organic Field-Effect Transistors. Hagen Klauk (Max Planck Institute for Solid State Research, Stuttgart, Germany) made a very interesting presentation about low voltage organic transistors and circuits. Takao Someya (University of Tokyo, Japan) addressed the printed organic transistors for large-area skin-like sensors and actuators.

Despite PolyApply will end at the end of 2007, it is expected that ICOE will still be held new year, supported by other sponsors.


MOS-AK Workshop on compact modeling will be held on Friday, 14 September 2007 in Munich, and it is organized for fifth subsequent time as an integral part of the ESSDERC/ESSCIRC conference, aims to strengthen a network and discussion forum among experts in the field, create an open platform for information exchange related to compact/Spice modeling, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD tool vendors.

The topics cover all important aspects of compact model development, implementation, deployment and standardization within the main theme - compact models for mainstream CMOS/SOI circuit simulation. The specific workshop goal will be to classify the most important directions for the future development of the compact models and to clearly identify areas that need further research.

This workshop is designed for device process engineers (CMOS, SOI, BiCMOS, SiGe) who are interested in device modeling; ICs designers (RF/IF/Analog/Mixed-Signal/SoC) and those starting in that area as well as device characterization, modeling and parameter extraction engineers. The content will be beneficial for anyone who needs to learn what is really behind IC simulation in modern device models. The technical program of MOS-AK Workshop consists of one day of tutorials given by noted academic and industry experts, also a posters session is foreseen.

More information on

Tuesday, June 19, 2007

CMOS at 60GHz

It is not Compact Modelling, but it is interesting enough. It seems that toshiba has developed a CMOS (yes, CMOS) technology able to run at 60GHz... See yourself the press release here.