[course] MEAD @ EPFL

Low-Power Analog Circuit Design

Live Course @ EPFL, Lausanne, Switzerland

JUNE 17-21, 2024

Registration Deadline: May 17, 2024 >> REGISTER

MONDAY, June 17
8:30 am-12:00 pm	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 18
8:30 am-12:00 pm	Noise Performance of Elementary Circuit Blocks	Boris Murmann
1:30-5:00 pm	Opamp Topologies and Design Fundamentals	Boris Murmann
WEDNESDAY, June 19
8:30-10:00 am	Low-Power High Efficiency OpAmp Design	Klaas Bult
10:30 am-12:00 pm	Low-Power High Efficiency Residue Amplifiers	Klaas Bult
1:30-3:00 pm	Analog Design Methodology and Practical Techniques for Frequency Compensation	Vadim Ivanov
3:30-5:00 pm	Energy Efficient Voltage References, Biasing in Analog Systems and Current Sources	Vadim Ivanov
THURSDAY, June 20
8:30-10:00 am	Power Dissipation in ADC Buidling Blocks	Klaas Bult
10:30 am-12:00 pm	Power Dissipation in ADCs	Klaas Bult
1:30-5:00 pm	Micropower ADCs	Kofi Makinwa
FRIDAY, June 21
8:30 am-12:00 pm	Energy Efficient Sensor Interfaces	Taekwang Jang
1:30-5:00 pm	Low-Power Frequency Reference Circuits	Taekwang Jang
1:30-5:00 pm	Power Management With Nanoampere Consumption and Efficient Energy Harvesting	Vadim Ivanov

[paper] EKV Model for Bulk-Driven Circuit Design Using gmb/ID Method

Lukas Nagy, Daniel Arbet, Martin Kovac, Miroslav Potocny, Robert Ondica and Viera Stopjakova

EKV Model for Bulk-Driven Circuit Design Using g_mb/I_D Method

IEEE AFRICON; 13-15 September 2021; Arusha (TZ)

 
Institute of Electronics and Photonics; Faculty of Electrical Engineering and Information Technology; Slovak University of Technology; Bratislava (SK)

Abstract: The paper addresses a development and application of EKV MOS transistor compact model with focus on the ultra low-voltage / ultra low-power analog integrated circuit (IC) design employing bulk-driven (BD) technique. The presented contribution can be viewed as an extension of standard EKV model application and as a contribution to ultra low-voltage IC design techniques. The paper compares the measured and extracted small-signal parameters of standalone transistor samples fabricated in 130 nm CMOS technology and the simulation results obtained using the proposed bulk-driven EKV v2.63 model and foundry-provided BSIM model v3.3. The transistor samples were analyzed with power supply of VDD = 0.4 V The paper also discusses the implementation of 3D graphs as a result of introducing another degree of freedom into the essential MOS transistor characteristics, while maintaining the ease of using the design hand-calculation with the original gm/ID approach.

Fig: Bulk-Driven TEF vs Inversion Coefficient – g_mb/I_D

Acknowledgment: This work has been supported in part by the Slovak Research and Development Agency under grant APVV 19-0392, the Ministry of Education, Science, Research and Sport of the Slovak Republic under grants VEGA 1/0731/20 and VEGA 1/0760/21, and ECSEL JU under project PROGRESSUS (Agr. No. 876868)