Tuesday, February 28, 2017

[mos-ak] [Final Program] Spring MOS-AK Workshop at DATE Conference in Lausanne, March 31, 2017

 Spring MOS-AK Workshop  
   at DATE Conference in Lausanne, March 31, 2017
     Final Program online http://mos-ak.org/lausanne_2017/   
 Together with the MOS-AK workshop chair, Dr. Jean-Michel Sallese, EPFL and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held during DATE Conference on March 31, 2017 in Lausanne (CH). The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Preannouncement - Dec. 2016
  • Call for Papers - Jan. 2017
  • Final Workshop Program - Feb. 2017
  • MOS-AK Workshop - March 31, 2017
Swisstech Convention Centre Quartier Nord de l'EPFL Route Louis-Favre 2 CH-1024 Ecublens (CH)
Final Program of Spring MOS-AK/DATE workshop is available online

Online MOS-AK/DATE Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee


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[ngspice] FM Bugger Circuit

Project Summary by https://www.eeweb.com
The project circuit design is a FM Bugger circuit. It works like a transmitter that transmits and projects information signals into the air wherein a FM radio will act as a receiver which would receive the transmitted signal. The circuit and the FM radio must be tuned-in with the same frequency to be able to transmit and receive information in the same channel. The FM bugger circuit is originally designed to be used like a spy gadget to eavesdrop other people’s conversations. Though it is designed that way, it is pretty much useful as a transmitter or as a walkie-talkie to relay messages in a distance [read more...]

Testing and Design Procedure
The FM bugger circuit is tested using PartSim and the NGSpice to test the output of the circuit:

FM Bugger Circuit Simulation
R1 Net1009 Mic 22K
R2 Net1009 Net1016 47K
R3 Net1003 0 33K
C1 Net1016 Mic 1NF
C2 Net1016 0 1NF
C3 Net1002 Net1003 4.7pF
C4 Net1002 Antenna 1NF
C5 Net1009 0 22NF
C6 Net1009 Net1002 50pF
L1 Net1009 Net1002 9NH
Q1 Net1002 Net1016 Net1003 2N2222
V1 Net1009 0 3V
V2 Mic 0 SINE ( 1 1 20Khz 0.0S )
R4 0 Antenna 1K
.options rshunt = 1.0e12 KEEPOPINFO
.MODEL 2N2222 NPN IS =3.0611E-14 NF =1.00124
+ BF =220 IKF=0.52 VAF=104 
+ ISE=7.5E-15 NE =1.41 NR =1.005 BR =4 
+ IKR=0.24 VAR=28 ISC=1.06525E-11 NC =1.3728 RB =0.13 
+ RE =0.22 RC =0.12 CJC=9.12E-12 MJC=0.3508 VJC=0.4089 
+ CJE=27.01E-12 TF =0.325E-9 TR =100E-9
write Net1002 Net1003 Net1009 Net1016 Mic Antenna I(V1) I(V2)
set appendwrite true
rusage everything
The simulation of the FM bugger circuit in PartSim shows that the circuit is working. The microphone was assumed to have an input of a 20 kHz sinusoidal wave. Then, the output signal at the load, R4 assumed to be the antenna for the circuit, turns out to produce a FM signal. Therefore, the FM bugger circuit itself has a great possibility to succeed and operate in real

Project Links:

[paper] Readout electronics for LGAD sensors

Readout electronics for LGAD sensors
O. Alonso,a N. Franch,a J. Canals,a F. Palacio,a M. López,a A. Vilà,a A. Diéguez,a
M. Carulla,b D. Flores,b S. Hidalgo,b A. Merlos,b G. Pellegrinib and D. Quirionb
aDepartment of Engineering: Section of Electronics, University of Barcelona,
C/ Martí i Franquès nº1, Barcelona, 08028 Spain
bInstituto de Microelectrónica de Barcelona — Centro Nacional de Microelectrónica (IMB-CNM),
Campus UAB, Cerdanyola del Vallès, Bellaterra, Barcelona, 08193 Spain

Abstract: In this paper, an ASIC fabricated in 180 nm CMOS technology from AMS with the very front-end electronics used to readout LGAD sensors is presented as well as its experimental results. The front-end has the typical architecture for Si-strip readout, i.e., preamplification stage with a Charge Sensitive Amplifier (CSA) followed by a CR-RC shaper. Both amplifiers are based on a folded cascode structure with a PMOS input transistor and the shaper only uses passive elements for the feedback stage. The CSA has programmable gain and a configurable input stage in order to adapt to the different input capacitance of the LGAD sensors (pixelated, short and long strips) and to the different input signal (depending on the gain of the LGAD). The fabricated prototype has an area of 0.865mm  0.965mm and includes the biasing circuit for the CSA and the shaper, 4 analog channels (CSA+shaper) and programmable charge injection circuits included for testing purposes. A first approach to find the proper dimensioning of the input transistor has been done using a Matlab script, where the transconductance value has been calculated with the EKV model

Acknowledgments This work has been partially funded by the Spanish national projects FPA2013-48387 and FPA2015-71292. In addition, this work has been done in the framework of RD50 CERN collaboration.

Tuesday, February 21, 2017

1-cent "lab on a chip" could save lives

Rahim Esfandyarpour, Stanford University, helped to develop a way to create a diagnostic "lab on a chip" for just a penny:
"I'm pretty sure it will open a window for researchers because it makes life much easier for them - just print it and use it," said Esfandyarpour. The results of this research were recently published in the journal Proceedings of the National Academy of Sciences [Source: Stanford Medicine]

[paper] Bipolar and MOS Transistors Under the Effect of Radiation

Measurements of the Electrical Characteristics of Bipolar and MOS Transistors
Under the Effect of Radiation
K. O. Petrosyants, L. M. SamburskiiI. A. KharitonovM. V. Kozhukhov
Meas Tech (2017) doi:10.1007/s11018-017-1100-z

ABSTRACT: The specific nature of the process of measuring the electrical characteristics of bipolar and metal-oxidesemiconductor (MOS) transistors subjected to the action of neutron, electron, and gamma irradiation is considered. An automated measurement system is developed. Examples illustrating the use of the system for investigations of the radiation hardness of transistors are presented and the parameters of SPICE models for use in circuit design (including SOI/SOS CMOS circuits with EKV-RAD macromodel) are determined.

Translated from Izmeritel’naya Tekhnika, No. 10, pp. 55–60, September, 2016 [read more...]

Friday, February 17, 2017

[call for papers] 2017 IEEE S3S Conference

S3S Conference 2017
Overview: This industry - wide event has gathered, for over 30 years, industry leaders and widely known experts, in a social - oriented environment. Our contributed papers and invited talks are focused on SOI Technology, Low - Voltage Devices/Circuits/Architectures, and 3D Integration. These 3 technologies will play a major role in tomorrow's industry as they enable application - tailored and Energy / Cost efficient circuit designs.
Important Dates
Paper Submission Deadline: May 22, 2017
Acceptance Notification: July 1, 2017

The conference at a glance
Monday to Wednesday, Oct. 16-18, 2017: Technical Sessions
Thursday, Oct.19: Fully - Depleted SOI Circuit Design; Full-day Tutorial
Tuesday, Oct.17: Monolithic 3D Half-day Tutorial

Scope: We welcome papers in the following areas:
Silicon On Insulator (SOI)
• Advanced Materials, Substrate and Processes
• Device Physics, Characterization and Modeling
• Device/Circuit Integration
• SOI Design, Circuits and Applications
• Non-Digital Devices and Applications (RF,
HV, Photonics, NEMS, MEMS, Analog...)
• New SOI Structures, Circuits and Applications
Low-Voltage Microelectronics
• Space-Based and Unattended Remote Sensors
• Biomedical Devices
• Low-Voltage Handheld/wireless systems
• Ultra-Low-Power Digital Computation
• Analog and RF Technologies
• Low Voltage Memory Technologies
• Energy Harvesting Techniques
• Asynchronous Circuits
• Novel Device and Fabrication Technology
3D Integration
• Low Thermal Budget Processing
• Fabrication Techniques and Bonding Methods
• Design and Test Methodologies
• Processes for Multi Wafer Stacking
• 3D IC EDA and Design Technology
• Heterogeneous Structures
• 3D Manufacturing and Logistics
• Reliability of 3D Circuits
• Fault Tolerant 3D Designs

Paper Submission:
Prospective authors should prepare a 2page abstract (follow online guidelines).
Acceptance is based on paper’s technical quality and relevance.

Conference manager contact Joyce Lloyd
6930 De Celis Pl., #36
Van Nuys, CA 91406
Tel: +1 818 795 3768
Fax: +1 818 855 8392

Thursday, February 16, 2017

HiSIM-HV and HiSIM2 implemented into ngspice

ngspice (Open Source SPICE Circuit Simulator) supports latest versions of HiSIM_HV and HiSIM2 [read more...]
[2] T. Ezaki, D. Navarro, Y. Takeda, N. Sadachika, G. Suzuki, M. Miura-Mattausch, H. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Non-quasi-static Analysis with HiSIM, a Complete Surface-potential-based MOSFET Model”, Proceedings of the 12 th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES’2005), 923-928 (2005.6), Invited Paper
[3] M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, “MOSFET Modeling for RF Circuit Era”, Proceedings of the 11 th International Conference on Mixed Design Mixed Design of Integrat ed Circuits and Systems (MIXDES’2004), 62-66 (2004), Invited Paper
[5] Mattausch,  H.J.;  Umeda,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The  HiSIM compact models of high-voltage/power semiconductor devices for circuit simulation," in Solid-State and Integrated Circuit Technology (ICSICT), 2014 12th IEEE International Conference on , vol., no., pp.1-4, 28-31 Oct. 2014
[6] Mattausch,  H.J.;  Miyake,  M.;  Ii zuka,  T.;  Kikuchihara,  H.;  Miura-Mattausch,  M.,  "The Second-Generation  of  HiSIM_HV  Compact  Models  for  High-Voltage  MOSFETs,"  in Electron Devices, IEEE Transactions on , vol.60, no.2, pp.653-661, Feb. 2013

Friday, February 10, 2017

[paper] Model for Organic Thin-Film Transistor

Physically Based Compact Mobility Model for Organic Thin-Film Transistor
T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch and H. J. Mattausch
in IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 2057-2065, May 2016.
doi: 10.1109/TED.2016.2540653

Abstract: A physically based compact mobility model for organic thin-film transistors (OTFTs) with an analysis of bias-dependent Fermi-energy (EF) movement in the bandgap (Eg) is presented. Mobility in the localized and extended energy states predicts the drain-current behavior in the weak and strong accumulation operations of OTFTs, respectively. A hopping mobility model as a function of the surface potential is developed to describe the carrier transport through localized energy states located inside Eg. The Poole-Frenkel parallel-field-effect mobility and vertical-field-effect mobility are considered to interpret the bandlike carrier transport in the extended energy states. The parallel field effect on mobility is more pronounced for shorter channel length OTFTs and is considered by developing a channel-length-dependent mobility model. The vertical field effect on mobility is included to account for the effect of mobility on carrier transport at high gate-voltage-induced fields. We also compared the model results with 2-D device simulations and measurements to verify the developed mobility model [read more...]

Workshop on biomedical applications at EPFL Lausanne

Data communication and remote powering for biomedical applications 
Workshop organized by Prof. Catherine Dehollain and Dr. Maria-Alexandra Paun
on February 24, 2017 at 09:00-17:00 in Room BC 01, EPFL Lausanne

Workshop Program
Invited Speaker
Presentation Title
Professor Catherine DEHOLLAIN,
EPFL, Lausanne, RF IC group
“Remotely powered sensor networks for medical applications”
Dr. Maria-Alexandra PAUN, EPFL, Lausanne, RF IC group
“Modeling and analysis of antennas in cochlear implants”
Dr. Gürkan YILMAZ, EPFL, Lausanne, RF IC group
“Wireless Power Transfer and Data Communication for Intracranial Neural Implants. Case Study: Epilepsy Monitoring”
Coffee Break (30 minutes)
Dr. Mehrdad GHANAD,
EPFL, Lausanne, RF IC group
“Remotely-Powered Batteryless Implantable Local Temperature Monitoring System for Freely Moving Mice”
EPFL, Lausanne, LSI laboratory
“On-line monitoring of aesthetics during surgery: opportunities and challenges”
Professor Adrian M. IONESCU, EPFL, Lausanne, Nanolab laboratory
“Wearable biosensors and their applications in future digital health”
LUNCH (90 minutes)
MOS-AK Association (EU)
“FOSS TCAD/EDA simulation tools with molecular/bio/med modeling examples”
Valtronic Technologies SA
“Ear infection, drug injectors and blood donation: innovative medical device development”
Dr. Qing WANG,
CHUV, Lausanne
“Development of a flow-through telemetry implant for monitoring cardiovascular blood pressure in small rodents and human”
Professor Philippe RYVLIN, CHUV, Lausanne
“Wearable devices for neurological diseases: Towards more rigorous clinical evaluation”
Concluding remarks (10 minutes)

Thursday, February 9, 2017

[paper] RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz

RF-MEMS for Future Mobile Applications: Experimental Verification of a Reconfigurable 8-Bit Power Attenuator up to 110 GHz
Jacopo Iannacci1 and Christian Tschoban2
1Center for Materials and Microsystems - CMM, Fondazione Bruno Kessler , Trento, ITALY
2Fraunhofer Institut für Zuverlässigkeit und Mikrointegration IZM , Berlin, GERMANY
Journal of Micromechanics and Microengineering
Accepted Manuscript online 8 February 2017
RF-MEMS technology is indicated as a key enabling solution to realise the high-performance and highly-reconfigurable passive components that future 5G communication standards will demand for. In this work, we present, test and discuss a novel design concept of an 8-bit reconfigurable power attenuator manufactured in the RF-MEMS technology available at the CMM-FBK, in Italy. The device features electrostatically controlled MEMS ohmic switches, in order to select/deselect resistive loads (both in series and shunt configuration) that attenuate the RF signal, and comprises 8 cascaded stages (i.e. 8-bit), thus implementing 256 different network configurations. Fabricated samples are measured (S-parameters) from 10 MHz to 110 GHz in a wide range of different configurations, and modelled/simulated in Ansys HFSS. The device exhibits attenuation levels (S21) in the range from -10 dB to -60 dB, up to 110 GHz. In particular, the S21 shows flatness from 15 dB down to 3-5 dB, from 10 MHz to 50 GHz, while less linear traces up to 110 GHz. Comprehensive discussion is developed around the Voltage Standing Wave Ratio (VSWR), employed as quality indicator for the attenuation levels. Margins of improvement at design level are also discussed, in order to overcome the limitations of the presented RF-MEMS device. The results of S-parameter simulations performed in the Quite Universal Circuit Simulator (QUCS: qucs.sourceforge.net) for a few significant configurations of the RF-MEMS attenuator from 10MHz to 110GHz are reported, too. [read more...]

[SemiWiki] What are the future technology trend for SPICE Modeling?

CEO Interview: Albert Li of Platform Design Automation, Inc (PDA)
by Daniel Nenni Published on 11-27-2016 02:00 PM

[SemiWiki] What are the future technology trend for SPICE Modeling?
[PDA] Having sufficient data is really the key to the problem, if data is sufficient, model can be automatically generated or synthesized. The concept has already been applied to the case of passive device modeling, such as modeling inductors. EM solvers play the role of proving more “data” or the synthesizers to generate models automatically. We’ve been working with the same concept for the active devices for quite a while, one way is to enable faster measurements, so that a lot more data can be collected and the other way is to achieve huge amount of data based on limited silicon through machine learning, which requires deep understanding of device behaviors, device modeling knowledge, data for the training and years of training experiences, we have already successfully applied the methodologies to our service projects, and tedious tasks such as model re-targeting is now purely done by machines. Machine Learning enabled model targeting from tweaking model parameters to just defining the targets and let the machine finish the job automatically

[SemiWiki] What are other areas in semiconductor you see that Machine Learning can help?
[PDA] We’ve published 3 papers in the past few years related to machine learning, and we used machine-learning algorithms to help on speeding up soft error simulation of logic circuits, automatic statistical modeling, and automatic RF front-end design,so the areas of machine-learning applications are massive. Algorithms, expertise, data and risk are the four key components to access Machine-Learning applications, take device characterization and modeling as examples, we have been working on the machine learning algorithms for over a decade, and we are definitely the experts in device characterization and modeling, we also have huge amount of data and models from previous projects, and these enabled us to train our software or instrument to achieve faster measurements and automatic model generations. 

[Book] Low-power HF Microelectronics: a unified approach

Low-power HF Microelectronics: a unified approach 
ISBN: 9780852968741 e-ISBN: 9781849193610
Editor: Gerson A. S. Machado
Department of Electronic Engineering
Imperial College of Science, Technology and Medicine
London, UK
Front Matter
1 Low-power HF microelectronics: a unified approach
Part 1: Process technology
2 Device structures and device simulation techniques
3 Stanford's ultra-low-power CMOS technology and applications
4 SOI technology
5 Radiation effects on ICs and a mixed analog CMOS-NPN-PJFET-on-insulator technology
Part 2: Device modelling/characterisation and circuit simulation
6 Modelling and characterisation of GaAs devices
7 The EKV Model: a MOST Model Dedicated to Low-Current and Low-Voltage Analogue Circuit Design and Simulation
8 Non-linear dynamic modelling of RF bipolar transistors
9 APLAC - object-oriented circuit simulator and design tool
10 Noise coupling in mixed-signal ASICs
Part 3: Reliability and test
11 Robust design and reliability analysis
12 Dynamic reliability of systems
13 Fault modelling and simulation for the test of integrated analog and mixed-signal circuits
Part 4: Circuit and system design methodology
14 High-speed and low-power techniques in CMOS and BiCMOS
15 Ultra-low-power digital design
16 Matched delay technique for high-speed digital design
17 Statistical design and optimisation for high-yield BiCMOS analog circuits
18 Design considerations for high-speed amplifiers using complementary BJTs
19 S2I techniques for analog sampled-data signal processing
20 Design of wireless portable systems
21 Low-power radio-frequency ICs and system architectures for portable communications
22 Analog and digital CMOS design for spread-spectrum wireless communications
23 Design considerations for BJT active mixers
24 Distortion in short channel FET circuits
25 Intelligent sensor systems and smart sensors: concepts, focus points and technology
26 Intelligent sensor systems and smart sensors: applications
Back Matter

Tuesday, February 7, 2017

[paper] Semiempirical Modeling of Reset Transitions in Unipolar, Resistive-Switching Based Memristors

Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors
Rodrigo Picos, Juan Bautista Roldan, Mohamed Moner Al Chawa, Pedro Garcia-Fernandez, Francisco Jimenez-Molinos, Eugeni Garcia-Moreno 
Radioengineering, 24(2): 420-424 (2015)

We have measured the transition process from the high to low resistivity states, i.e., the reset process of resistive switching based memristors based on Ni/HfO2/Si-n+ structures, and have also developed an analytical model for their electrical characteristics. When the characteristic curves are plotted in the current-voltage (I-V) domain a high variability is observed. In spite of that, when the same curves are plotted in the charge-flux domain (Q-f), they can be described by a simple model containing only three parameters: the charge (Qrst) and the flux (frst) at the reset point, and an exponent, n, relating the charge and the flux before the reset transition. The three parameters can be easily extracted from the Q-f plots. There is a strong correlation between these three parameters, the origin of which is still under study [read more...]

Picos, R.; et al. Semiempirical Modeling of Reset Transitions in Unipolar Resistive-Switching Based Memristors; Radioengineering, 24(2): 420-424 (2015). [http://hdl.handle.net/10481/36994]

[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422
We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]

Publication stats: 1260 Reads

1260 Reads: Open-source circuit simulation tools for RF compact semiconductor device modelling
Article · Sep 2014 · International Journal of Numerical Modelling Electronic Networks Devices and Fields

[paper] Impact of technology scaling on analog and RF performance of SOI–TFET

Impact of technology scaling on analog and RF performance of SOI–TFET
P Kumari, S Dash and G P Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology, Volume 6, Number 4 
Published 9 October 2015

This paper presents both the analytical and simulation study of analog and RF performance for single gate semiconductor on insulator tunnel field effect transistor in an extensive manner. Here 2D drain current model has been developed using initial and final tunneling length of band-to-band process. The investigation is further extended to the quantitative and comprehensive analysis of analog parameters such as surface potential, electric field, tunneling path, and transfer characteristics of the device. The impact of scaling of gate oxide thickness and silicon body thickness on the electrostatic and RF performance of the device is discussed. The analytical model results are validated with TCAD Sentaurus device simulation results [read more...]

[1] Extensive electrostatic investigation of workfunction-modulated SOI tunnel FETs Subhrasmita Panda et al  2016 Journal of Computational Electronics 15 1326
[2] S. Sahoo et al  2016 337
[3] A comprehensive investigation of silicon film thickness (T SI) of nanoscale DG TFET for low power applications Rajeev Ranjan et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 03500
[4] A complete analytical potential based solution for a 4H-SiC MOSFET in nanoscale M K Yadav et al  2016 Advances in Natural Sciences: Nanoscience and Nanotechnology 7 025011
[5] S. Dash et al  2015 447

Sunday, February 5, 2017

[paper] Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers

Processes of AM-PM Distortion in Large-Signal Single-FET Amplifiers
S. Golara, S. Moloudi and A. A. Abidi, " 
in IEEE Transactions on Circuits and Systems I: Regular Papers
vol. 64, no. 2, pp. 245-260, Feb. 2017; doi: 10.1109/TCSI.2016.2604000
Abstract: Using an appropriate formulation of field-effect transistor (FET) current as a nonlinear function of terminal voltages, and a simplified model of gain compression in common source amplifiers, we are able to identify four principal sources of amplitude-to-phase (AM-PM) distortion. A new analysis shows the varactor effect of gate-source capacitance on AM-PM distortion, and the changing Miller-multiplied gate-drain capacitance as the field-effect transistor (FET) is driven into compression. The phase shift in the load impedance at the frequency of operation and incomplete suppression of 2nd harmonic by a resonant load of limited Q are explained and analyzed. We are able to identify the dominant mechanism of AM-PM distortion in various practical circuits, which then suggests methods of remediation. The analysis was put to test by predicting the measured AM-PM distortion of power amplifiers reported in the literature. Good agreement is found in all cases, with insights gained into the dominant cause of distortion in each case. In this paper, AM-PM distortion is first defined in Section II. In Section III, the EKV model of the MOSFET is briefly presented and dominant mechanisms are explained. In Section IV the analysis is compared against measured data to validate the theory and Section V summarizes the conclusions [read more...]

Wednesday, February 1, 2017

IEEE Workshop on Compact Modeling

IEEE Workshop on Compact Modeling
March 3, 2017
Technical Sponsorship by: IEEE Electron Devices Society UP Chapter
Organized by: Department of Electrical Engineering, IIT Kanpur
Coordinator: Prof. Yogesh Singh Chauhan
Venue: Outreach Auditorium, IIT Kanpur

IEEE Workshop on Compact Modeling Agenda:
Time Topic Speaker
8:00 - 8:15 Workshop inauguration by Director IIT Kanpur and IEEE-UP Chairman
8:15 - 9:00 Industry Standard Compact Modelling Dr. Yogesh Singh Chauhan
IIT Kanpur
9:00 - 9:30 Modelling of mismatch and process variations Dr. Abhisek Dixit
9:30 - 10:00 TBA Dr. Nihar Ranjan Mohapatra
10:00 - 10:30 Modelling of normally-off GaN based MOSHEMT Dr. Trupti Ranjan Lenka
NIT Silchar
10:30 - 10:45 ASM-HEMT: Industry standard compact model for GaN HEMTs Dr. Sudip Ghosh
10:45 - 11:00 Modelling of quasi ballistic transport in nano-wire transistors Mr. Avirup Dasgupta
IIT Kanpur
11:00 - 11:15 TBA Mr. Priyank Rastogi
IIT Kanpur
11:15 - 11:30 Compact modelling of TMD based thin body transistors Mr. Chandan Yadav
IIT Kanpur
11:30 - 11:45 Tea Break
11:45 - 12:15 Qualification techniques for sim models for EEsof products Mr. Mohit Khanna
Keysight Technologies
12:15 - 12:45 High frequency device characterization and modeling for THz applications Prof. Thomas Zimmer
12:45 - 2:00 Lunch
2:00 - 2:30 Device design consideration: IoT perspective Dr. Santosh Kumar Vishvakarma
2:30 - 3:00 TBA Dr. Aditya Sankar Medury
3:00 - 3:30 Simulations, analysis and applications of doping- and junction- free transistors Dr. Jawar Singh
3:30 - 4:00 Design of radiation hardened 24-bit ADC for generic applications Mr. H.S.Jattana
4:00 - 4:15 Tea Break
4:15 - 4:45 Role of Feynman diagrams in energy band structure of materials - A post density functional theory approach Dr. Sitangshu Bhattacharya
4:45 - 5:15 TBA Dr. Swaroop Ganguly
5:15 - 5:45 TBA Dr. Saurabh Lodha
5:45 - 6:15 TBA Dr. Udayan Ganguly
6:15 - 6:45 TBA Dr. Manoj Saxena
Delhi University
6:45 - 7:00 Closing Keynote