Tuesday, September 26, 2017

[mos-ak] [press note] 15th MOS-AK Workshop at ESSDERC/ESSCIRC September 11, 2017 Leuven

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
September 11, 2017 Leuven

 The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 15th consecutive workshop as an integral engineering event at the ESSDERC/ESSCIRC on September 11, 2017 in Leuven (B). The event was coorganized by Jean-Michel Sallese, EPFL and Daniel Tomaszewski ITE (PL); its technical program was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. Technical MOS-AK program promotion was provided by the Eurotraining and NEEDS of nanoHUB.org

A group of the international academic researchers and modeling engineers attended 13 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts [1-12]. The presentations are available online for download at <http://www.mos-ak.org/leuven_2017/>. Selected best presentation will be recommended for further publication in the IJHSES.

The ESSDERC Track4 Devices and Circuit Compact Modeling has followed the MOS-AK workshop. The Track4 has been organized for very first time to highlight importance of the international compact/SPICE modeling R&D and foster its Verilog-A standardization. The ESSDERC Conference participants have attended four subsequent modeling sessions: Cross-Domain Compact Modeling [13-15]; Parameter Extraction [16-19]; Modeling of Emerging Devices [20-23]; Traps and Noise [24-28]. All the conference papers are available at IEEE Xplore and selected best papers will be recommended for further publication in J-EDS.

The MOS-AK Modeling Working Group has various deliverable and initiatives including a book entitled "Open Source TCAD/EDA Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD/EDA software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2017/2018 including:
  • 10th International MOS-AK Workshop in Silicon Valley (US) Dec. 2017
  • Spring MOS-AK Workshop in Strasbourg (F) March 2018
  • 3rd Sino MOS-AK Workshop in Beijing (CN) June, 2018
  • 16th MOS-AK ESSDERC/ESSCIRC Workshop in Dresden (D) Sept, 2018
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution. For more information please visit: mos-ak.org


MOS-AK/Leuven 2017 Workshop; Sept. 11, 2017
[1] ASCENT: Access to Leading European Nanoelectronics Technology
Jim Greer Tyndall (IRL)
[2] Junctionless Nanowire Transistors Performance: Static and Dynamic Modeling
Marcelo Antonio Pavanello Centro Universitario FEI (BR)
[3] Modeling and Analysis of Full-Chip Parasitic Substrate Currents
Renaud Gillon and Wim Schoenmaker ONSEMI (B), MAGWEL (B)
[4] Small- and large-signal RF modeling of silicon-based substrates
Martin Rack and Jean-Pierre Raskin Université catholique de Louvain (B)
[5] Tunnel FET C-V modeling: Impact of TFET C-V characteristics on inverter circuit performance
Chika Tanaka, Tetsufumi Tanamoto, and Masato Koyama, Toshiba (J)
[6] ASCENT Open Access to 14nm PDKs
T. Chiarella, N. Cordero, O. Faynot, Tyndall (IRL)
[7] Modelling of Surface Traps Effect on Semiconductor Nanowires
Ashkhen Yesayan*, Stepan Petrosyan*, Jean-Michel Sallese** *IRa, Armenia, **EPFL (CH)
[8] Measurement and modelling of specific behaviors in 28nm FD SOI UTBB MOSFETs of importance for analog / RF amplifiers
D. Flandre, V. Kilchytska, B. Kazemi, C. Gimeno and J.-P. Raskin UC Louvain
[9] IEEE EDS Compact Model Standardization
Benjamin Iniguez URV (SP)
[10] Is it possible to reduce the PDK development cost when demand for data is continuously increasing?
Andrej Rumiantsev MPI Corporation
[11] Optimal measurement parameters for accurate time-domain and spectral analyses of RTN
Léopold Van Brandt*, Valeriya Kilchytska*, Jean-Pierre Raskin*, Bertrand Parvais** and Denis Flandre*  *ELEN department, ICTEAM Institute, Université catholique de Louvain **imec
[12] Compact modeling for CMOS technology development and IC design
Daniel Tomaszewski ITE Warszaw (PL)

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (11:00-12:20)
Cross-Domain Compact Modeling 
Chair: Wladek Grabinski - MOS-AK; Cristell Maneux – LIMS;
[13] INVITED: SPICE Modeling in Verilog-a: Successes and Challenges
Colin McAndrew
[14] SPICE Modeling of Light Induced Current in Silicon with 'generalized' Lumped Devices
Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese
[15] Total Ionizing Dose Effects on Analog Performance of 28 nm Bulk MOSFETs
Chun-Min Zhang, Farzan Jazaeri, Alessandro Pezzotta, Claudio Bruschini, Gulio Borghello, Serena Mattiazzo

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (14:00-15:20)
Parameter Extraction 
Chair: Thierry Poiroux - CEA; Marco Bellini – ABB;
[16] Nanometer CMOS Characterization and Compact Modeling at Deep-Cryogenic Temperatures
Rosario Marco Incandela, Lin Song, Harald Homulle, Fabio Sebastiano, Edoardo Charbon, Andrei Vladimirescu
[17] Cryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing
Arnout Beckers, Farzan Jazaeri, Andrea Ruffino, Claudio Bruschini, Andrea Baschirotto, Christian Enz
[18] A New Method for Junctionless Transistors Parameters Extraction
Renan Trevisoli, Rodrigo Doria, Michelly de Souza, Sylvain Barraud, Marcelo Pavanello
[19] Avalanche Compact Model Featuring SiGe HBTs Characteristics Up to BVCBO
Mathieu Jaoul, Didier Céli, Cristell Maneux, Michael Schröter, Andreas Pawlak

ESSDERC Trac4: Compact Modeling; Tuesday September 12, 2017 (16:40-18:00)
Modeling of Emerging Devices 
Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;
[20] Equivalent Circuit Model for the Electron Transport in 2D Resistive Switching Material Systems
Enrique Miranda, Chengbin Pan, Marco Villena, Na Xiao, Jordi Suñe, Mario Lanza
[21] Analytical Drain Current Model for Schottky-Barrier CNTFETs
Igor Bejenari, Michael Schroter, Martin Claus
[22] A General Circuit Model for Spintronic Devices Under Electric and Magnetic Fields
Meshal Alawein, Hossein Fariborzi
[23] Compact Physical Model of a-IGZO TFTs for Circuit Simulation
Matteo Ghittorelli, Fabrizio Torricelli, Carmine Garripoli, Jan-Laurens van der Steen, Gerwin Gelinck, Sahel Abdinia

ESSDERC Trac4: Compact Modeling; Wednesday September 13, 2017 (14:20-15:40)
Traps and Noise 
Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;
[24] Modeling of Dynamic Trap Density Increase for Aging Simulation of Any MOSFET Circuits Mitiko Miura-Mattausch, Hidenori Miyamoto, Hideyuki Kikuchihara, Dondee Navarro, Tapas K. Maiti, Nezam Rohbani
[25] Comprehensive Compact Electro-Thermal GaN HEMT Model
Muhammad Alshahed, Mina Dakran, Lars Heuken, Mohammed Alomari, Joachim Burghartz
[27] Trap-Assisted Carrier Transport Through the Multi-Stack Gate Dielectrics of HKMG nMOS Transistors: a Compact Model
Apoorva Ojha, Nihar Ranjan Mohapatra
[28] A New Verilog-a Compact Model of Random Telegraph Noise in Oxide-Based RRAM for Advanced Circuit Design
Francesco Maria Puglisi, Nicolò Zagni, Luca Larcher, Paolo Pavan

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Tuesday, September 19, 2017

A Large-Signal Monolayer Graphene Field-Effect Transistor Compact #Model for RF-Circuit Applications https://t.co/zoPkw74IK2

from Twitter https://twitter.com/wladek60

September 19, 2017 at 03:55PM

Conduction Mechanisms in Metal-Base Vertical Organic Transistors by DC and LF-Noise Measurements https://t.co/ZSiOLFMquC #paper

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September 19, 2017 at 03:07PM

#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei https://t.co/748KTEgqk7

from Twitter https://twitter.com/wladek60

September 19, 2017 at 12:08PM

#Modeling of #Electromechanical Sensors & Systems https://t.co/K40OGzRV4U https://t.co/rdih9lNeei

from Twitter https://twitter.com/wladek60

September 19, 2017 at 12:08PM

Monday, September 18, 2017

[paper] Design techniques for low-voltage analog integrated circuits

Matej Rakus, Viera Stopjakova, Daniel Arbet
Institute of Electronics and Photonics, Faculty of Electrical Engineering
and Information Technology Slovak University of Technology in Bratislava, Slovakia,
Journal of ELECTRICAL ENGINEERING, Vol.68 (2017), No.4, 245–255
DOI: 10.1515/jee-2017–0036

ABSTRACT: In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.
Fig: Parameter gm/ID versus the normalized drain current. MOS transistor operates in weak inversion (WI) for ic < 0.1. Strong inversion (SI) is for ic < 10. Everything in between belongs to the moderate inversion (MI) with center in ic = 1 

Friday, September 15, 2017

[paper] Principles and Trends in Quantum Nano-Electronics and Nano-Magnetics for Beyond-CMOS Computing

Ian A. Young and Dmitri E. Nikonov 
Components Research, Technology & Manufacturing Group
Intel Corp., Hillsboro, Oregon, USA
ESSDERC/ESSCIRC Leuven Sept.12-14, 2017

Abstract: An analysis of research in quantum nanoelectronics and nanomagnetics for beyond CMOS devices is presented. Some device proposals and demonstrations are reviewed. Based on that, trends in this field are identified. Principles for development of competitive computing technologies are formulated. Results of beyond-CMOS circuit benchmarking are reviewed.

TABLE I: Voltage Limitations For Computation Variables

Principle 1: Beyond-CMOS circuits require CMOS as an integral part. They will work alongside and augment CMOS computing blocks.

Principle 2: Some devices utilize collective states; this confers advantages of non-volatility or more energy efficient operation.

Principle 3: The choice for an optimal beyond-CMOS device will be determined by compatibility with an efficient and effective interconnect.

Principle 4: Low voltage devices – most direct way to low energy operation.

Principle 5: Start benchmarking with bottom up modeling of devices, build up from simple to more complicated circuits.

Principle 6: Majority gates (if easily implemented in a certain technology) enable more efficient circuits, especially for more complex computation functions.

Principle 7: Use electrical interconnects for longer propagation spans.

Principle 8: To convince the wider community, a non- volatile computing paradigm needs to be general enough to prove that it is valid for more than one architecture; while it needs to be specific enough to dispel claims that an essential aspect is missed.

Principle 9: Neuromorphic computing can be done more efficiently with beyond-CMOS circuits.

Conclusions: In summary, we have presented our view on the recent trends in quantum nanoelectronics and nanomagnetics for beyond CMOS devices, and outlined a few principles to make them realize practical computing technologies. We can pose a question for ourselves: What are the most promising directions of research? Where to double down on the effort? Among many equally important thrusts, our subjective preference is for magnetoelectric switching and neuromorphic beyond-CMOS circuits.

Tuesday, September 12, 2017

[book] Systematic Design of Analog CMOS Circuits

Paul G. A. Jespers, Boris Murmann
Cambridge University Press; 31 Oct 2017; 342pp

Discover a fresh approach to efficient and insight-driven analog integrated circuit design in nanoscale-CMOS with this hands-on guide. Expert authors present a sizing methodology that employs SPICE-generated lookup tables, enabling close agreement between hand analysis and simulation. This enables the exploration of analog circuit tradeoffs using the gm/ID ratio as a central variable in script-based design flows, and eliminates time-consuming iterations in a circuit simulator. Supported by downloadable MATLAB code, and including over forty detailed worked examples, this book will provide professional analog circuit designers, researchers, and graduate students with the theoretical know-how and practical tools needed to acquire a systematic and re-use oriented design style for analog integrated circuits in modern CMOS.

Monday, September 11, 2017

Current state of the art in #modeling heating effects in nanoscale devices - Books - IOPscience https://t.co/E0UlkDDJVk

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September 11, 2017 at 06:43PM