Wednesday, October 30, 2019

[mos-ak] [2nd Announcement and C4P] 12th International MOS-AK Workshop, Silicon Valley, DEC.11, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
12th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 11, 2019

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 12th International MOS-AK Workshop which will be organized at Silvaco HQ on Dec. 11, 2019 (co-located with the IEDM and CMC Meetings)

Planned 12th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source (FOSS) TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2019
  • 2nd Announcement - Oct. 2019
  • Final Workshop Program - Nov. 2019
  • MOS-AK Workshop: Dec. 11, 2019
Online Abstract Submission is open 
(any related enquiries can be sent to

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2019 Heterogeneous Integration Roadmap (#HIR) Identifies Long-Term Technology Requirements to Inspire Collaboration in the Electronics Industry #paper

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October 30, 2019 at 02:37PM

Monday, October 28, 2019

6 signs you might be a Linux user - No.6 is: You have a passion for #opensource

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October 28, 2019 at 07:17PM

#China has set up a new national #semiconductor fund of 204.2 #billion yuan ($28.9 billion), as it seeks to nurture its domestic chip industry and close the technology gap with the U.S. #paper

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October 28, 2019 at 01:47PM

Friday, October 25, 2019

Wednesday, October 23, 2019

#Google scientists confirmed in a blog post that their #quantum #computer had needed just 200 seconds to solve a problem that they claim would take the world’s fastest supercomputer 10,000 years to complete. #paper

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October 23, 2019 at 03:46PM

Synthesis of an optimized control signal for an improved EMC switching behavior of MOSFETs using a system characterization approach; C Krause, A Bendicks, T Dörlemann, S Frei; On-board Systems Lab, TU Dortmund University; EMC EuropeLab #paper

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October 23, 2019 at 10:13AM

Thursday, October 17, 2019

3rd Symposium on Schottky barrier MOS devices was held on October 4th, 2019 at the Amphi Bloch, Orme de Merisiers-CEA, Gif-sur Yvette (F) #paper

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October 17, 2019 at 02:19PM

Interlligent UK’s RF & Microwave Design Seminar |7 November 2019 | Møller Centre, Cambridge, UK” #paper

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October 17, 2019 at 02:11PM

ESSCIRC/ESSDERC will take place in Grenoble from Sept 14th to 17th 2020, and the website in on-line. Watch-out for more. Looking forward to meet you there! #paper

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October 17, 2019 at 02:00PM

Open Position - SiNANO - To work on the EPSRC funded project: Quantum Simulator for Entangled Nano-Electronics – The main aim is to go beyond the state of the art in device modelling of resonant tunnelling diode and single electron transistors. #paper

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October 17, 2019 at 01:57PM

Do you know "flash memory"? It's a very small and important thing that comes in smartphones. But where and how is it used? #flashmemory that supports everyone's convenient life. Let's explore secrets with this book! A series by Gakken Manga #paper

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October 17, 2019 at 10:15AM

Wednesday, October 16, 2019

#Microsoft To Linux Community: ‘We Are An #OpenSource #Company’

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October 16, 2019 at 04:45PM

Top Ten (+2) Companies For US Patents #paper

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October 16, 2019 at 10:23AM

Tuesday, October 15, 2019

#Space #Radiation and Its Effects on #Electronic Systems #paper

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October 15, 2019 at 08:38PM

Your #Future #RaspberryPiCPU Could Be Made From #Bacteria #paper

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October 15, 2019 at 08:33PM

#TSMC to present 5nm CMOS, 22nm STT-MRAM at #IEDM #paper

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October 15, 2019 at 06:42PM

[#paper] S.M. Mohd Hassan, A. Marzuki; Millimeter-wave CMOS Transistor Design and Modelling: A Review; IJSAR , 6(10), 2019; 01-14

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October 15, 2019 at 09:04AM

Monday, October 14, 2019

#OpenSource Hardware Trends, #Arm Takes a Different Tack

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October 14, 2019 at 04:03PM

#OpenHardware #CfP #OpenSource Computer Aided Design #CAD and Modeling devroom at FOSDEM 2020

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October 14, 2019 at 10:23AM

[Open Hardware] [CfP] Open Source Computer Aided Design and Modeling devroom at FOSDEM 2020

We are pleased to announce the CfP for

Open Source Computer Aided Design and Modeling devroom 
at FOSDEM 2020
1-2 February 2020, Brussel, Belgium.

The devroom will take place on Saturday, 1 February 2020, at [ULB (Campus Solbosch)](, in Brussels, Belgium.

We hope you'll join us for a full day of talks, demos and interesting discussions on designing, modeling and testing hardware using Open Source tools. We welcome any talk proposals about the creation of physical objects. Topics of interest include, but are not limited to:

- Circuit Design
    * Printed circuit board design tools
    * Circuit simulation
- 3d modeling and analysis
    * Solid modeling tools
    * Meshing, modeling and transforming physical representations
    * Finite element analysis
- 3d printing
    * 3d slicing tools
    * Motor control
- Machine design and integration
    * Open Hardware projects
    * ECAD/MCAD integration
    * Thermal analysis
    * Wire modeling
- Physical Model Data storage
    * Data representation and optimization
    * Version control in hardware data storage
    * Collaborative and team-based hardware design techniques

Slots will be allocated for short (20 minutes) and long (40 minutes) talks. Speakers need to specify their preferred format. Both include time for questions and answers. Depending on the number of submissions, submitters may be asked to utilize an alternate time format.

The submission process
Please submit your proposals at before 20 November 2019.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one.

Please include the following information with your submission:

  • Abstract
  • Preferred Session length
  • Speaker bio
  • Link to any hardware / code /slides for the talk

When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Open Source Computer Aided Design and Modeling" in the track drop-down menu. Otherwise your proposal may go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Keep in mind that much of the value in these meetings comes from the discussions, so please allot at least 20% of the talk time for questions and answers.

Important dates
- Call for papers available: 13 October 2019
- Call for participation closes: 20 November 2019
- Devroom schedule available: 15 December 2019
- Devroom day: Saturday 1 February 2020 (09:00 to 17:00)

The talks will be recorded and live-streamed during FOSDEM20. The
recordings will be published under the same licence as all FOSDEM
content (CC-BY). Only presentations will be recorded, not informal
discussions and whatever happens during breaks between presentations.
By agreeing to present at FOSDEM, you give permission to be recorded.
Please contact us if you would like to request an exception to the
recording policy for your talk.

Mailing list
Feel free to subscribe to the [Open Source Computer Aided Design and
Modeling mailing list](
to submit ideas, ask questions and generally discuss about the event.
open-hardware-devroom mailing list

Friday, October 11, 2019

#GaN as a key material for establishing a #sustainable society by Hiroshi Amano is a Japanese physicist, engineer, and inventor, awarded the 2014 #Nobel Prize in Physics 14 October 2019 | 12:15pm-1pm | EPFL Forum Rolex #paper

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October 11, 2019 at 08:39PM

Thursday, October 10, 2019

article with 200 reads

Wladek Grabinski, Matt Bucher,Jean-Michel Sallese and François Krummenacher
Journal of Telecommunications and Information Technology 2000(3-4):31-42, March 2000

Mukku P.K., et al. (2020) Recent Trends and Challenges on Low-Power FinFET Devices. In: Smart Intelligent Computing and Applications. Smart Innovation, Systems and Technologies, vol 160. #paper

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October 10, 2019 at 11:21AM

#UNICEF Launches #Cryptocurrency Fund to Back #OpenSource Technology

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October 09, 2019 at 11:32PM

A modular point contact spectroscopy probe for sub-Kelvin applications #paper

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October 09, 2019 at 11:46PM

Tuesday, October 8, 2019

Today Is Ada Lovelace Day 2019 #ALD19 @findingada #paper

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October 08, 2019 at 11:49AM

Monday, October 7, 2019

#IHP #XFAB- #SiGe:C #BiCMOS technologies #paper

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October 07, 2019 at 06:37PM

2019 IEDM Tutorials with: Cryogenic MOSFET Modeling, Christian Enz, EPFL (Dec.7 4:30 pm – 6:00 pm) #paper

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October 07, 2019 at 06:36PM

The 31st IEEE ICM 2019 C4P The IEEE ICM has been held in numerous countries across the Middle East, Southern Europe, and Asia for the past 30 years. The conference will take place in the city of the world-famous Egyptian Pyramids #paper

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October 07, 2019 at 06:36PM

T. A. Oproglidis et al., "Upgrade of Drain Current Compact Model for Nanoscale Triple-Gate Junctionless Transistors to Continuous and Symmetric," in IEEE TED, vol. 66, no. 10, pp. 4486-4489, Oct. 2019. #paper

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October 07, 2019 at 06:36PM

Thursday, October 3, 2019

IEEE EDS Distinguished Lecturer by ED Poland Chapter

IEEE EDS Distinguished Lecturer by ED Poland Chapter
Krzysztof Górecki and Daniel Tomaszewski

EDS Distinguished Lecturer, Professor Mansun Chan (UST, Hong Kong) gave a talk titled “Simulation and Modeling of Dynamic Systems with Time Varying Device Characteristic” on May 21, 2019, at Łukasiewicz Research Network—Institute of Electron Technology (Łukasiewicz ITE), Warsaw, Poland. Approximately 15 persons from ITE and from abroad, traveled to Warsaw for the ESSDERC paper selection meeting and to attend the lecture.

The abstract of the Distinguished Lecture: The existing circuit simulation methodologies are based on time-invariant device models, electrical characteristics and parameters of which do not change over time. However, more recently, many new applications such as neuromorphic computing or artificial neural-network circuits require the use of devices with history dependent behavior. Due to such a behavior different from traditional transistors, which are the focus for the compact modeling community, a new approach to monitor the time dependent characteristics of these devices is necessary. In addition, a new simulation methodology is also required to predict the behavior of such system efficiently. In the presentation, a new approach to simulate dynamic systems was introduced. The proposed approach combined with the modification of simulation flow and compact model construction was introduced. The approach is very general and can be used to cover a wide class of devices with dynamic behavior such as memory function or device performance degradation during a prolonged operation.

A Mini-Colloquium was organized by the ED Poland Chapter in cooperation with: Gdynia Maritime University, Gdynia, Poland, Łukasiewicz Research Network—Instytut Technologii Elektronowej (Łukasiewicz-ITE), Warsaw, Poland, and a Department of Microelectronics and Computer Science, Lodz University of Technology, Lodz, Poland. Approximately 20 persons attended the full-day event. Nine interesting talks were presented by internationally recognized experts in the area of nanoelectronics, including three EDS Distinguished Lecturers (DLs).

Prof. Shinichi Takagi (The University of Tokyo) presented a talk “Tunneling FET technology for ultra-low power logic applications” addressing critical issues, technical challenges and viable technologies of TFETs using a variety of semiconductors such as Si, Ge and oxide semiconductors. Device engineering indispensable in improving the performance of TFETs were summarized with emphasis on the source junction formation technology and the optimal material design. The electrical characteristics of TFETs using Si and Ge homo junctions, Ge/strained SOI hetero-junctions and ZnO/(Si, Ge) hetero-junctions were presented as the viable examples.

Prof. Andrzej Strójwąs (PDF Solutions, and Carnegie Mellon University) had a talk “New Product Introduction Challenges in the Bleeding Edge Technology Nodes,” presenting a comprehensive methodology and a full suite of process-design design interaction characterization techniques to enable cost-effective introduction of new products in the 7 nm and below technologies.

Dr. Arkadiusz Malinowski (GlobalFoundries) gave a talk “Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodes,” in which challenges related to FinFET metrology/inspection, lithography/overlay, integration/variability, cycle time and cost were addressed.

Dr. Rajiv V. Joshi (DL, IBM Research Division Yorktown Heights) presented a lecture “Variability aware design in nm era.” He highlighted predictive analytical technique based on statistical analysis methodology targeting both memory and custom logic design applications is highlighted. Design case studies both in planar and non-planar technologies were discussed. Finally, the speaker discussed an efficient statistical methodology based on simulation and modeling to evaluate and minimize the aging of memory chips.

Prof. Henryk M. Przewłocki (DL, Łukasiewicz Research Network—ITE Warsaw) presented a talk “Expanding the horizon of photoelectric investigations of the MIS system properties,” in which he discussed an extended theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account. The theory is in agreement with the relevant experimental characteristics. This opens the possibilities of developing new measurement methods of the MIS system crucial parameters.

Prof. Marcelo Pavanello (DL, Centro Universitario FEI) presented a talk “Performance and modeling of Nanowire-based MOSFETs.” He discussed differences between double-gate, triple-gate and nanowire-based MOSFETs and their characteristics. Also junctionless nanowire transistors (JNTs) were introduced as one of the interesting alternatives for downscaling because of their relative process simplicity compared with inversion-mode nanowires. Different aspects of modeling of the JNT steady-state and dynamic operation was interestingly presented.

Dr. Farzan Jazaeri (EPFL) presented a talk “Cryogenic Electronics and Quantum Computing Architecture.” He made an interesting review of topics of a quantum computation that holds the promise to solve problems that are intractable even for the most powerful supercomputers. Quantum computers process the information stored in quantum bits (qubits). The information in the qubits is fragile, so the qubits must be typically cooled to cryogenic temperature. Spin qubits in silicon were reported that have already been proposed and experimentally demonstrated in academic research laboratories.

Prof. Mike Brinson (London Metropolitan University) presented a talk “Equation-Defined template and synthesis driven compact modelling of semiconductor devices.” He reported current research that links Equation-Defined Device modelling with Verilog-A modules, driven by code templates and synthesis, which in turn result in an improved interactive modelling techniques. Throughout the talk a series of compact device models were introduced to demonstrate the fundamentals and application of the new approach to compact device modelling.

Dr. Władek Grabiński (DL, MOS-AK and GMC) presented a talk “FOSS tools for support of IC modeling and design with special emphasis on Verilog-A standardization.” He discussed selected FOSS CAD tools along complete technology/design tool chain from nanoscaled technology processes. The talk was illustrated by application examples of the FOSS TCAD tools, like Cogenda TCAD and DEVSIM. Compact modeling was related to the parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce were presented.

~ Marcin Janicki, Editor

[IEEE EDS Update] MIXDES 2019, Rzeszów (PL)

26th International Conference “Mixed Design of Integrated Circuits and Systems"'
MIXDES 2019 
By Marcin Janicki

On June 27–29, 2019, Rzeszów, Poland, the International Conference MIXDES 2019 took place. The event was organized by the Lodz University of Technology together with the Warsaw University of Technology. The conference was co-sponsored by Poland Section IEEE ED & CAS Societies, Polish Academy of Sciences (Section of Microelectronics and Electron Technology), and Commission of Electronics and Photonics of Polish National Committee of International Union of Radio Science—URSI. The 3-day conference program included 97 presentations from 28 countries. The following six general invited talks were presented during the conference plenary sessions:
  • Advanced MOS Device Technology for Low Power Logic LSI Shinichi Takagi (The University of Tokyo, Japan)
  • Quantum Bits and Quantum Computing Architecture Farzan Jazaeri (EPFL, Switzerland)
  • Towards Energy-Autonomous Integrated Systems Through Ultra-low Voltage Analog IC Design Viera Stopjaková (Slovak University of Technology in Bratislava, Slovakia)
  • THz Technologies and Applications Thomas Skotnicki (Institute of High Pressure Physics PAS, Poland)
  • What is Killing Moore’s Law? Challenges in Advanced FinFET Technology Integration Arkadiusz Malinowski (GLOBALFOUNDRIES, USA)
  • Yield and Reliability Challenges at 7nm and Below Andrzej Strojwąs (Carnegie Mellon University, USA)
The sessions also included presentations in the frame of four special sessions:
  • Compact Modeling for Nanoelectronics organized by D. Tomaszewski (Institute of Electron Technology, Poland) and W. Grabiński (GMC, Switzerland)
  • Intelligent Distributed Systems organized by M. Drozd (LTC Sp. z o.o., Poland), R. Sztoch, P. Sztoch (FINN Sp. z o.o., Poland), B. Sakowicz and D. Makowski (Lodz University of Technology, Poland)
  • Large Scale Research Facilities organized by A. Napieralski, W. Cichalewski (Lodz University of Technology, Poland)
  • Thermonuclear Fusion Projects organized by S. Simrock (ITER, France), D. Makowski (Lodz University of Technology, Poland), D. Bocian and M. Scholz (Institute of Nuclear Physics, Poland
The next MIXDES 2020 Conference will take place in Wrocław, Poland. The Preliminary Call for Papers is available at More information about the past and next MIXDES Conferences can be found at
Edited by Mariusz Orlikowski
MIXDES 2019 Conference Secretary

[paper] Gallium Nitride FET Model

Gallium Nitride FET Model
V V Orlov, G I Zebrev
National Research Nuclear University MEPHI, Moscow, Russia

Abstract: We have presented an analytical physics-based compact model of GaN power FET, which can accurately describe the I-V characteristics in all operation modes. The model considers the source-drain resistance, different interface trap densities and self-heating effects. (read more

Introduction: Gallium nitride (GaN) high electron mobility transistor (HEMT) technology has many advantages, that make it a promising candidate for high-speed power electronics. It allows high-power operation at much higher frequencies than silicon laterally diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs), currently a staple for the cellular base station industry [1]. The high breakdown voltage capability (over 100 V), high electron mobility, and high-temperature performance of GaN HEMTs are the main factors for its use in power electronics applications. Circuits design in both application regimes requires the accurate compact device models that can describe the non-linear I-V characteristics. The current state-of-the-art GaN power transistor circuit models are mostly empirical in nature and contain a large number of fitting parameters. The source-drain series resistance and self-heating make the compact modeling difficult [2]. Currently available models are not enough accurate to describe the I-V characteristics of power GaN HEMTs in all operation modes. This means, that we need a compact physics-based analytical model based on the physical description of the device. In this paper, we present a physics-based GaN power transistor model based on generic approach The paper contains 3 parts. In the first part, we will give a concise description of the model. The specific power HEMT’s effects, such as series resistance and self-heating will be discussed in the second and third parts 

[paper] Prediction of DC-AC Converter Efficiency Degradation

Kenshiro Sato, Dondee Navarro, Shinya Sekizaki, Yoshifumi Zoka, Naoto Yorino,
Hans Jürgen Mattausch, Mitiko Miura-Mattausch, 
Prediction of DC-AC Converter Efficiency Degradation due to Device Aging
Using a Compact MOSFET-Aging Model
IEICE Transactions on Electronics
論文ID 2019ECP5010, [早期公開] 公開日 2019/09/02

Online ISSN 1745-1353, Print ISSN 0916-8524,,,

Abstract: The degradation of a SiC-MOSFET-based DC-AC converter-circuit efficiency due to aging of the electrically active devices is investigated. The newly developed compact aging model HiSIM_HSiC for high-voltage SiC-MOSFETs is used in the investigation. The model considers explicitly the carrier-trap-density increase in the solution of the Poisson equation. Measured converter characteristics during a 3-phase line-to-ground (3LG) fault is correctly reproduced by the model. It is verified that the MOSFETs experience additional stress due to the high biases occurring during the fault event, which translates to severe MOSFET aging. Simulation results predict a 0.5% reduction of converter efficiency due to a single 70ms-3LG, which is equivalent to a year of operation under normal conditions, where no additional stress is applied. With the developed compact model, prediction of the efficiency degradation of the converter circuit under prolonged stress, for which measurements are difficult to obtain and typically not available, is also feasible.

Wednesday, October 2, 2019

Ph D scholarship about semiconductor device modeling in Tarragona (Spain)

We want to get one fellowship for a Ph D student position in the Department of Electronic Engineering in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona , Spain. The subject of the Ph D would be o the development of new techniques of characterization and modeling of nanoscale semiconductor devices, in particular two-dimensional semiconductor FETs, which are one of the most promising device structures for downscaling to 1nm. It will be related to funding research projects in which the hosting group participates.

The duration of the grant will be 3 years.

The candidate should have a  Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics, obtained between January 1 2017 and October 14 2019. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

Applicants must send to my e-mail address (, and by October 19 2019, a CV together witha copy of the academic certificates indicating the grades obtained for all subjects during their studies (both Bachelor Degree and Master Degree).

Tarragona is a medium city (100000 inhabitants) with a pleasant Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport.

My research group in the Department of Electronic Engineering, Universitat Rovira i Virgili (URV) is one of the strongest groups in compact modeling in Europe. We have led or are leading several national and European projects targeting semiconductor device characterization, physics and modeling.

Tuesday, October 1, 2019

INNOVATORIUM Łukasiewicza #paper

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October 01, 2019 at 03:17PM

Indium gallium arsenide #InGaAs one-transistor dynamic random access #1TDRAM memory #paper

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October 01, 2019 at 01:52PM