[paper] Modeling a 2D Electrostatic Potential in MOS Devices

Francois Lim, Benjamin Iñiguez, Alexander Kloes

A new analytical method for modeling a 2D electrostatic potential in MOS devices, 

applicable to compact modeling

J. Appl. Phys. 28 January 2024; 135 (4): 044501

DOI: 10.1063/5.0188863

Abstract: This paper presents a new conformal mapping method to solve 2D Laplace and Poisson equations in MOS devices. More specifically, it consists of an analytical solution of the 2D Laplace equation in a rectangular domain with Dirichlet boundary conditions, with arbitrary values on the boundaries. The advantages of the new method are that all four edges of the rectangle are taken into account and the solution consists of closed-form analytical expressions, which make it fast and suitable for compact modeling. The new model was validated against other similar methods. It was found that the new model is much faster, easier to implement, and avoids many numerical issues, especially near the boundaries, at the cost of a very small loss in accuracy.

FIG: (a) The calculated 2D potential from the closed-form analytic model,
for a Double Gate MOSFET with tsc=12nm, tox=1.6nm, and L=25nm.
(b) Corresponding equipotentials. 

Acknowledgments: This work was funded by the Spanish Ministry of Science through Contract No. PRX21/00726.

[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.

[paper] Noise Degradation and Recovery in Gamma-irradiated SOI nMOSFET

S.Amora^b, V.Kilchytska^a, F.Tounsi^a, N.André^a, M.Machhout^b, L.A.Francis^a, D.Flandre^a

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET

with in-situ thermal annealing

Solid-State Electronics; 108300; online 7 April 2022, 

DOI: 10.1016/j.sse.2022.108300

   
a SMALL, ICTEAM Institute, Université catholique de Louvain (B)
b Faculté des Sciences de Université de Monastir (TN)

Abstract: This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365°C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Fig: Device under test : (a) cross-section schematic, (b) microscopic front view

showing the membrane and other embedded elements

[book] Fully Depleted SOI

Sorin Cristoloveanu; Fully Depleted Silicon-On-Insulator:

Nanodevices, Mechanisms and Characterization
2021 Elsevier B.V. 

ISBN: 978-0-12-819643-4

Fully Depleted Silicon-On-Insulator provides an in-depth presentation of the fundamental and pragmatic concepts of this increasingly important technology.

There are two main technologies in the marketplace of advanced CMOS circuits: FinFETs and fully depleted silicon-on-insulators (FD-SOI). The latter is unchallenged in the field of low-power, high-frequency, and Internet-of-Things (IoT) circuits. The topic is very timely at research and development levels. Compared to existing books on SOI materials and devices, this book covers exhaustively the FD-SOI domain. 

Key Features:

• Written by a top expert in the silicon-on-insulator community and IEEE Andrew Grove 2017 award recipient
• Comprehensively addresses the technology aspects, operation mechanisms and electrical characterization techniques for FD-SOI devices
• Discusses FD-SOI’s most promising device structures for memory, sensing and emerging applications

Table of Contents:

Front Matter

Preface

Part I: Technology

Chapter 1 - FD-SOI technology pp. 3-37

Part II: Mechanisms in FD-SOI MOSFET

Chapter 2 - Coupling effects pp. 41-70

Chapter 3 - Scaling effects pp. 71-114

Chapter 4 - Floating-body effects pp. 115-138

Part III: Electrical characterization techniques for FD-SOI structures

Chapter 5 - The pseudo-MOSFET pp. 141-177

Chapter 6 - Diode-based characterization methods pp. 179-200

Chapter 7 - Characterization methods for FD-SOI MOSFET pp. 201-238

Part IV: Innovative FD-SOI devices

Chapter 8 - Electrostatic doping and related devices pp. 241-265

Chapter 9 - Band-modulation devices pp. 267-298

Chapter 10 - Emerging devices pp. 299-348

FD-SOI teasers pp. 349-352

Index

[paper] Monolithic Pixel Detector in SOI Technology

High spatial resolution monolithic pixel detector in SOI technology 

R. Bugiel^a1, S. Bugiel^a2, D. Dannheim_b, A. Fiergolski^b, D. Hynds^b,3, M. Idzik^a, P. Kapusta^c, M. Munker^b, A. Nurnberg^b4, S. Spannagel^b,5, K. Swientek^a, W. Kucewicz^a

^aAGH-UST, Poland, ^bCERN, Switzerland, ^cIFJ PAN, Poland

CLICdp-Pub-2020-004

06 August 2020

¹Present: CNRS/IPHC, France.

²Present: CNRS/IPHC, France.

³Present: NIKHEF, Amsterdam, Netherlands.

⁴Present: KIT, Karlsruhe, Germany.

⁵Present: DESY, Hamburg, Germany.

Abstract: This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200nm Silicon-On-Insulator (SOI) CMOS technology studied in the context of high spatial resolution performance. The tested detectors were fabricated on a 500µm thick highresistivity Floating Zone type n (FZ-n) wafer and on a 300 µm Double SOI Czochralski type p (DSOI Cz-p) wafer. The pixel size is 30µm×30µm and two different front-end electronics architectures were tested, a source follower and a charge-sensitive preamplifier. The test-beam data analyses were focused mainly on determination of the spatial resolution and the hit detection efficiency. In this work different cluster formation and position reconstruction methods are studied. In particular, a generalization of the standard η-correction adapted for arbitrary cluster sizes, is introduced. The obtained results give in the best case a spatial resolution of about 1.5µm for the FZ-n wafer and about 3.0µm for the DSOI Cz-p wafer, both detectors showing detection efficiency above 99.5%.

Fig.: Simplified schematics of Silicon-On-Insulator structures. The Buried N(P)-Well (BN(P)W) is a layer dedicated to shielding the electronics from the sensors electric field.

Aknowlegement: This work was financed by the European Union Horizon 2020 Marie Sklodowska-Curie Research and Innovation Staff Exchange program under Grant Agreement no. 645479 (E-JADE) and also by the Polish Ministry of Science and Higher Education from funds for science in the years 2017 – 2018 allocated to an international co-financed project. The authors would like to thank also the operators of the CERN SPS beam line and North Area test facilities.