Wednesday, February 20, 2019

IIT Kanpur: open compact modeling position

Indian Institute of Technology, Kanpur
The Office of Research & Development

Date: 15-02-2019

Indian Institute of Technology, Kanpur an Institute of national importance, has been in the forefront of engineering & technology education and research & development. The Institute derives strength from its philosophy, vision and values that has led to achievement of academic excellence and promotion of high order technological research. The Institute's R&D Division is looking for suitable Indian nationals including Persons of Indian Origins (PIOs) and Overseas Citizens of India (OCIs) for appointment on the following positions for short-term R&D Projects on contractual basis for a period of maximum five years.

Please forward this job opening with following requirements to your friends/colleagues.
  • Hands-on experience of I-V (DC and Pulsed), CV, RF (CW and Pulsed)
  • Expertise in Semiconductor Device Modeling and Simulation softwares
  • PDK Development & Layout design
  • Knowledge of Verilog-A language, PEL/ Python script.
  • Strong background in semiconductor device physics
  • Good writing skills
  • Good Project Management skills

Sunday, February 17, 2019

#FOSDEM 2019 – Space and Meaning #paper

from Twitter

February 17, 2019 at 10:45PM

Saturday, February 9, 2019

[mos-ak] 2019 IEEE International Conference on Modeling of Systems Circuits and Devices

2019 IEEE International Conference on Modeling of Systems Circuits and Devices
(MOS-AK/India 2019)
Organized by Joint Chapters of CAS / EDS Societies
IEEE Hyderabad Section

Together with the lead sponsors and the conference organization committee we have pleasure to invite to consecutive, 2nd MOS-AK/India Compact Modeling Conference to be hosted at the IIT Hyderabad

Announced, subsequent 2nd MOS-AK/India Conference organized at the IIT Hyderabad, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <>

MOS-AK/India Conference - February 25-27, 2019
Feb. 25      - ONE day SPICE/Verilog-A Modeling Tutorials
Feb. 26-27 - TWO days SPICE/Verilog-A Modeling Conference

Indian Institute of Technology (IIT)
Hyderabad, Kandi
Telangana State, India

Online registration (any related enquiries can be sent or call 9652158557) 

W.Grabinski on the behalf of International MOS-AK Committee


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IEEE EDS MQ at Hotel Plaza, Begumpet (IN)

Joint Chapter of Electron Devices and Circuits and Systems Societies (ED/CAS)
IEEE Electron Devices Mini Colloquia
Date:  Sunday, 24 February 2019 Time:  3.00 P.M to 6.00 P.M
Venue: Hotel Plaza, Begumpet. Free Registration Link 

For any further details please contact the MQ Coordinators:
Registrations: 3:00PM to 3.15 PM

DL Talk 1: 3.15 PM to 4.00PM, Speaker: Prof. Charvaka Duvvury, iT2 Technologies (USA)
Topic: ESD Issues and Challenges for Advanced Semiconductor Technologies
Electro-static Discharge (ESD) has been a constant reliability concern for IC technologies for several decades and it is heading to be a roadblock to newer applications for electronic devices. The seminar will begin with a summary of the understanding about ESD and how this is applied to develop protection at the IC level for Digital, Analog, and RF circuits. This will be followed by a review of the problems posed by advanced technologies beyond the 32 nm node and the corresponding challenge of hitting the available ESD design window while meeting the IO high-speed performance requirements. The talk will conclude with a survey of the upcoming challenges from emerging technologies such as GaN and CNT, as well as IoT applications. 
Speaker Bio: Charvaka Duvvury was a Texas Instruments fellow while he worked in the Silicon Technology Development group at TI.  He received his PhD in engineering science from the University of Toledo and afterwards worked as a post-doctoral fellow in Physics at the University of Alberta. His experience at Texas Instruments spanned for 35 years in semiconductor device physics with pioneering development work in ESD design. He has also mentored PhD students at several leading US universities on their investigations in ESD research and received Outstanding Industry Mentor Award twice from the SRC. Charvaka has published over 150 papers in technical journals and conferences and holds more than US 75 patents. He co-authored and contributed to 5 books on the subject. He is a recipient of the IEEE Electron Devices Society’s Education Award and Outstanding Contributions Award from the EOS/ESD Symposium. Charvaka has been serving on Board of Directors of the ESD Association (ESDA) since 1997 promoting ESD education and research at academic institutes. He is co-founder and co-chair of the Industry Council on ESD since 2006. During 2015 he became a co-founder of the iT2 Technologies that utilizes software engine and machine learning for rapid ESD data analysis. Charvaka is also Fellow of the IEEE.

Hi Tea and Networking: 4.00 PM to 4.15 PM

DL Talk 2: 4.15 PM to 5.00PM Speaker: Dr. Wladek Grabinski, MOS-AK (Switzerland)
Topic: FOSS TCAD/EDA Process/Device Simulations for Compact/SPICE Modeling
Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present FOSS CAD simulation and design tools: ngspice, Qucs, GnuCap, Xyce.
Speaker Bio: Wladek Grabinski received the Ph.D. degree from the Institute of Electron Technology, Warsaw, Poland, in 1991. From 1991 to 1998 he was a Research Assistant at the Integrated Systems Lab, ETHZ, Switzerland, supporting the CMOS and BiCMOS technology developments by electrical characterization of the processes and devices. From 1999 to 2000, he was with LEG, EPFL, and was engaged in the compact MOSFET model developments supporting numerical device simulation and parameter extraction. Later, he was a technical staff engineer at Motorola, and subsequently at Freescale Semiconductor, Geneva Modeling Center, Switzerland. He is now a consultant responsible for modeling, characterization and parameter extraction of MOST devices for the IC design. Wladek is the chair of the ESSDERC Track4: "Device and circuit compact modeling" as well as has served as a member of organization committee of ESSDERC/ESSDERC, TPC of SBMicro, SISPAD, MIXDES Conferences; reviewer of the IEEE TED, IEEE MWCL, IJNM, MEE, MEJ/ Wladek is involved in activities of the MOS-AK Association and serves as a coordinating manager since 1999.

DL Talk 3: 5.00PM to 5.45 PM Speaker: Prof. Roberto Murphy, INAOE (Mexico)
Topic: Fundamental Aspects of CMOS RF Modeling and Characterization
As CMOS technology evolves, higher frequencies can be attained while more complex functions and operations become possible in Integrated Circuits. At the design stage, there are several fundamental aspects which have to be taken into account in order to have successful fabrication results, the closest to simulation predictions as possible. Furthermore, this evolution leads to more time-consuming characterization routines, which require both personnel and time to be performed. Some of the aspects dealt with in this talk refer to characterization techniques, substrate network effects, and geometry effects.
Speaker Profile:  Roberto S. Murphy-Arteaga (M´92, SM´02) received his B.Sc. degree in Physics from St. John’s University, Minnesota, and got his M.Sc. and Ph.D. degrees from the National Institute for Research on Astrophysics, Optics and Electronics (INAOE), in Tonantzintla, Puebla, México.  He has been a researcher at INAOE since 1988. Since then, he has presented over 110 talks at scientific conferences, directed nine Ph.D. theses, 16 M.Sc. and 2 B.Sc. theses, published more than 140 articles in scientific journals, conference proceedings and newspapers, and is the author of a text book on Electromagnetic Theory.  He is currently a senior researcher with the Microelectronics Laboratory.  Dr. Murphy’s research interests are the physics, modeling and characterization of the MOS Transistor and passive components for high frequency applications, especially for CMOS wireless circuits, and antenna design.  For the last 30 years, he has been active in the organization of conferences, mostly in Latin America, such as the IEEE International Caribbean Conference on Devices, Circuits and Systems; the Latin American Symposium on Circuits and Systems; VLSI-SoC, and others related to microelectronics and IC design. He is a Senior Member of IEEE, a Distinguished Lecturer of the Electron Devices Society, the President of ISTEC, a member of the Mexican Academy of Sciences, and a member of the Mexican National System of Researchers (SNI).

Tuesday, February 5, 2019

If #Software Is Funded from a #Public Source, Its Code Should Be #OpenSource

from Twitter

February 05, 2019 at 08:56PM

Monday, February 4, 2019

#MIXDES: #Paper submission deadline reminder (4 weeks left) This year the 26th MIXDES will take place between June 27-29, 2019 in Rzeszów (PL)

from Twitter

February 04, 2019 at 02:55PM

Sunday, February 3, 2019

GnuCap and ngspice at 2019 FOSDEM DevRoom CAD and Open Hardware

Today at #FOSDEM: Felix Salfelder presenting "#Gnucap -- The GNU circuit analysis package Architecture, Algorithms and Applications" addressing Compact Model license considerations

Holger Vogt presenting "#ngspice, current status and future developments" pointing to an obstacle in FOSS CAD/EDA adoption: The newer and more complex Libs/PDKs often come along with encrypted model files.

Friday, February 1, 2019