Saturday, December 30, 2017

The Essential #OpenSource Reading List: 21 Must-Read #Books https://t.co/Xxw3AyMNPf Shared from my Google feed


from Twitter https://twitter.com/wladek60

December 30, 2017 at 12:02PM
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Friday, December 29, 2017

Low Frequency Drain #Noise Characterization and #TCAD Physical Simulations of #GaN #HEMTs: Identification and analysis of physical location of traps https://t.co/yXvJjLeMe7 #paper


from Twitter https://twitter.com/wladek60

December 29, 2017 at 08:29PM
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Physics-Based #Modeling of TID Induced Global Static Leakage in Different #CMOS Circuits https://t.co/OLjRR8MFge https://t.co/xcJ8XFdkt9


from Twitter https://twitter.com/wladek60

December 29, 2017 at 03:16PM
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RT @Chip_Insider: Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond https://t.co/3m6l5Ce1Qp #modeling #10nm #7nm #simulation https://t.co/EEz5woRm86


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December 29, 2017 at 03:12PM
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Wednesday, December 27, 2017

#design for #reliability of generic #sensor interface circuits https://t.co/lzvuIsruXQ #paper https://t.co/PtL7tm0M6n


from Twitter https://twitter.com/wladek60

December 27, 2017 at 10:21AM
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#75Years of the #DRC- A History Worth Repeating https://t.co/ITLIEIpTDv #paper https://t.co/nz08VI5OGg


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December 27, 2017 at 10:18AM
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Charge-Based Modeling of Radiation Damage in Symmetric Double-Gate MOSFETs https://t.co/d99rQA4VTj #paper https://t.co/Fb6sNIGpa7


from Twitter https://twitter.com/wladek60

December 27, 2017 at 09:42AM
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Design and Characterization of a Silicon Photomultiplier in 0.35um CMOS https://t.co/o0SuZkWF7E #paper https://t.co/NpCRVFJBdZ


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December 27, 2017 at 09:28AM
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Tuesday, December 26, 2017

The High School Student Who’s Building His #Own Integrated Circuits #IC https://t.co/Ytmy1hpRC5 #paper


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December 26, 2017 at 09:58PM
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Saturday, December 23, 2017

Electrostatically Doped DSL #Schottky Barrier #MOSFET on #SOI for Low Power Applications - IEEE Journals & Magazine https://t.co/ylOD8eXELs #paper


from Twitter https://twitter.com/wladek60

December 23, 2017 at 01:52PM
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First #transistor created #70 #years ago: the device that changed the world https://t.co/97zm60GoFq #paper https://t.co/mn6PhVxXHg


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December 23, 2017 at 12:40AM
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Friday, December 22, 2017

[mos-ak] [press note] 10th International MOS-AK Workshop in the Silicon Valley

 Arbeitskreis Modellierung von Systemen und Parameterextraktion
 Modeling of Systems and Parameter Extraction Working Group
 10th International MOS-AK Workshop in the Silicon Valley
 San Jose, CA, December 6, 2017 

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 10th consecutive, international compact/SPICE workshop in the USA. The event was hosted on Dec.6, 2017, by Cadence Design Systems in the Silicon Valley with is a perfect place to celebrate a decade of the MOS-AK activities in the USA. The technical program of the event was coordination by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop has received full industrial sponsorship by Cadence Design Systems (lead sponsor) and Keysight Technologies with technical program promotion provided by the IEEE EDS SC-SF ChapterIJHSES as well as NEEDS of nanoHUB.org

The MOS-AK workshop was opened by Hany Elhak, Cadence Design Systems, who has welcomed all the attendees and shared Cadence view on the compact modeling and its importance in the TCAD/EDA modeling/design ecosystem. A group of 40+ international academic researchers and modeling engineers attended 13 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D.

The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including: [1] J. Xie, Cadence: Verilog-A debug tool: AHDL Lint; [2] R. Radojcic et al. PDA: A Complete Learning-Based Semiconductor Parametric Testing and Device Modeling Ecosystem, from Probing to Simulation; [3] D. Celi, STM: Generation of HICUM/L2 and HICUM/L0 Geometry Scalable Model Libraries; [4] I. Radu, SOITEC: SOI technology platforms for 5G: opportunity of collaboration; [5] Mierzwinski et al. Keysight: An Overview of the HiSIM SOI/SOTB Compact Models; [6] A. Pashkovich and B. Tudor, SILVACO: Featured Circuit Simulation Using SMARTSPICE Compact Models and Verilog-A; [7] A. Asenov, Uni. Glasgow: Compact Model Requirements for TCAD Based DTCO; [8] D. Yakimets et al. imec: Enablement of compact models for ultra-scaled CMOS technologies; [9] G. Hills et al. Uni. Stanford: Rapid Co-optimization of Processing & Circuit Design to Overcome Carbon Nanotube Variations; [10] W. Grabinski, EDS DL, MOS-AK (EU): FOSS/H Tools for Compact Modeling; [11] D. Navarro et al. Uni Hiroshima: A Normally-on MOSFET Compact Model based on Surface Potential Description; [12] K.-W. Pieper, Infineon: Aging simulation with variation of several model parameters; [13] T. Nigam and A. Kerber, GLOBALFOUNDRIES: Reliability characterization of discrete devices and modeling circuit level ageing in advanced CMOS technologies. All the presentations are available online for download at <http://www.mos-ak.org/silicon_valley_2017/>. Selected best presentation will be recommended for further publication in the IJHSES.

The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and open Verilog-A model directory with supporting FOSS TCAD/EDA tools. The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA and China throughout coming 2018 year, including:
  • Spring MOS-AK Workshop, Strasbourg (F) March 15-16, 2018
  • 3rd Sino MOS-AK Workshop, Beijing (CN) June, 2018
  • MIXDES Special CM Session, Gdynia (PL) June 21-23, 2018
  • 16th MOS-AK at ESSDERC/ESSCIRC, Dresden (D), Sept.3, 2018
  • 11th International MOS-AK Workshop, Silicon Valley (US) Dec.2018

About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

About Cadence Design Systems:
Cadence is the only company that provides the expertise and tools, IP, and hardware required for the entire electronics design chain, from chip design to chip packaging to boards and to systems. We enable electronic systems and semiconductor companies to create innovative products that transform the way people live, work, and play. Our products are used in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. For more information please visit: https://www.cadence.com

About Keysight Technologies
Keysight Technologies, Inc. (NYSE: KEYS) is a leading technology company that helps its engineering, enterprise and service provider customers accelerate innovation to connect and secure the world. Keysight's solutions optimize networks and bring electronic products to market faster and at a lower cost with offerings from design simulation, to prototype validation, to manufacturing test, to optimization in networks and cloud environments. Customers span the worldwide communications ecosystem, aerospace and defense, automotive, energy, semiconductor and general electronics end markets. Keysight generated revenues of $3.2B in fiscal year 2017. In April 2017, Keysight acquired Ixia, a leader in network test, visibility, and security. More information is available at www.keysight.com



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[Special Issue] TED on “Compact Modeling for Circuit Design"

Call for papers for 
a Special Issue of IEEE TED
on
Compact Modeling for Circuit Design

Submission deadline: April 30, 2018               Publication date: January 2019

In order to capture the full potential of semiconductor devices, compact device models and design software are critically needed. Predictive and physical device and circuit design software are required to accelerate development cycles and tackle issues of device efficiency, manufacturing yield and product stability. The performance/accuracy of the design software is dependent on the availability of accurate device models, and for circuit design, compact models.

In particular, compact device models are the vehicle that allows the design of circuits using the targeted devices. The compact model should not only accurately capture the physics of the device in all operation regimes, but at the same time should also have an analytical or semi-analytical formulation to be used in automated design tools for the simulation of circuits containing several or many devices. On the other hand, compact models can also be used as a tool to make clear estimations and predictions of the performances of future devices following technological trends. The lack of adequate compact models for a number of emerging devices is mostly due to the insufficient understanding of the physical mechanisms that govern their behaviours. Regarding many emerging non-silicon structures, devices, circuit and system designers very often rely on empirical behavioural macro-models and/or use existing silicon device compact models based on the conventional understanding of transport processes. However, for these emerging non-silicon devices, neither approach provides a fully adequate device description under all operation conditions, nor the quantitative predictive quality required for the accurate production quality design.

Therefore, the main objective of this dedicated special issue is to engage Electron Devices Community in a serious discussion with their scholarly contributions specifically focused on solving major challenges in the broad area of compact device modeling for circuit design.

Suggested topics include but not limited to:
  1. Silicon MOSFET modeling: Advanced Bulk MOSFETs; SOl MOSFETs; Multi-Gate MOSFETs: Double-Gate MOSFETs, Surrounding-Gate MOSFETs, FinFETs, UTB SOI MOSFETs; Junctionless MuGFETs; Power and High Voltage MOSFETs.
  2. Junction-based and compound semiconductor FET modeling: Advanced MESFETs; Advanced HEMTs; lIl-V and Ill-N; MOSFETs; Advanced IFETs.
  3. Diode and bipolar transistor modeling: Advanced BJTs; HBTs; IGBTs; pn and pin diodes; Varactors.
  4. Emerging transistor modeling: Tunnel FETs; Molecular transistors; Single Electron Transistors; Quantum Dot Transistors; Negative Capacitance Transistors.
  5. Emerging semiconductor devices: Memories, MRAM, PCRAM etc.; Spintronic devices; Layered/2D materials
  6. Thin-Film FETS (TFT): a-Si:H TFTs; Polycrystalline Si TFTs; OTFTs and OECTs; Oxide TFTs; Single-crystal TFTs.
  7. Modeling of physical effects: Noise; High frequency operation; Mismatch; Strain; High energy particle interactions in ICs (Cosmic rays and energy beams); ESD events; Ballistic and quasi-ballistic transport; Layout dependent effects.
  8. Photonic devices: LEDs and OLEDs; Photodiodes; Solar cells; Photodetectors; SPADs.
  9. Model implementation in EDA tools and applications: Model code adaptation to EDA tools; Computational model performances in design tools; Challenges of model implementation in design tools; Compact model applications to variation and statistical analysis; Compact model applications to thermal analysis; Compact model applications to design exploration; Compact model applications to design optimization; Compact model applications to device process improvements; Compact modeling for BSD prediction; Circuit design using new compact models.

Submission instructions: Manuscripts should he submitted in a double column format using an IEEE style file Please visit the following link to download the templates:
http://www,ieeeiorg/publicationsistandards/publications/authors/author7templates,html
In your cover letter, please indicate that your submission is for this special issue. Please submit papers using the website: http://mc.manuscriDtcentral.com/ted

Guest Editors:
  1. Benjamin Iniguez, URV, Tarragona (SP)
  2. Yogesh Chauan, IIT Kanpur (IN) 
  3. Andries Scholten, NXP Semiconductors, Eindhoven (NL)
  4. Ananda Roy, Intel Corporation, Portland, OR (USA)
  5. Slobodan Mijalkovic, Silvaco Europe Ltd, St. Ives (UK)
  6. Sadayuki Yoshitomi, Toshiba Corporation, Tokyo (J)
  7. Kejun Xia, NXP Semiconductors, Phoenix, AZ (USA) 
  8. Wladek Grabinski, GMC Consulting, Commugny (CH) 
  9. Kaikai Xu, UEST of China, Chengdu (CN) 



Thursday, December 21, 2017

Enhanced transconductance in a double-gate graphene field-effect transistor https://t.co/aVJlxjMHVj #paper https://t.co/DPbG4zxT1d


from Twitter https://twitter.com/wladek60

December 21, 2017 at 03:28PM
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Replication of Random Telegraph Noise by Using a Physical-Based Verilog-AMS #Model https://t.co/KQZ8JlQV8r https://t.co/jVdRwct9J3


from Twitter https://twitter.com/wladek60

December 21, 2017 at 01:14PM
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[call for papers] EUROSOI-ULIS2018, Granada

Joint International EUROSOI-ULIS Conference on SOI and Ultimate Integration on Silicon
Granada, Spain
on March 19-21, 2018

3rd Call for Papers 
Abstract Submission Deadline: January 12, 2018

The organizing committee invites scientists and engineers working in the above fields to actively participate by submitting high quality papers. Original 2-page abstracts with illustrations will be accepted for review in pdf format. The template is available at the conference website: congresos.ugr.es/eurosoi-ulis2018. The accepted abstracts will be published in a Proceedings book with an ISBN. The authors of the accepted contributions will be requested to provide a 4-page paper to appear in the conference proceedings, which will be submitted to the IEEE Xplore® digital library. A selection of the presented manuscripts in the conference will be invited to submit an extended version, which after a peer-review process, will be published as a Special Issue of Solid-State Electronics. A best paper award will be attributed to the best paper by the SINANO institute.

Papers in the following areas are solicited:
• Advanced SOI materials and wafers. Physical mechanisms and innovative SOI-like devices.
• New channel materials for CMOS: strained Si, strained SOI, SiGe, GeOI, III-V and high mobility materials on insulator; carbon nanotubes; graphene and other two-dimensional materials.
• Properties of ultra-thin films and buried oxides, defects, interface quality. Thin gate dielectrics: high-κ materials for switches and memory.
• Nanometer scale devices: technology, characterization techniques and evaluation metrics for high performance, low power, low standby power, high frequency and memory applications.
• Alternative transistor architectures including FDSOI, DGSOI, FinFET, MuGFET, vertical MOSFET, Nanowires, FeFET and Tunnel FET, MEMS/NEMS, Beyond-CMOS nanoelectronic devices.
• New functionalities in silicon-compatible nanostructures and innovative devices representing the More than Moore domain, nanoelectronic sensors, biosensor devices, energy harvesting devices, RF devices, imagers, etc.
• CMOS scaling perspectives; device/circuit level performance evaluation; switches and memory scaling. Three-dimensional integration of devices and circuits, heterogeneous integration.
• Transport phenomena, compact modeling, device simulation, front- and back-end process simulation.
• Advanced test structures and characterization techniques, parameter extraction, reliability and variability assessment techniques for new materials and novel devices.
• Emerging memory devices

Invited Speakers:
• Prof. Jesús del Alamo (MIT, USA): III-V CMOS: Quo vadis?
• Prof. Hiroshi Iwai (TIT, Japan): 3D scaling of Si-IGBT.
• Prof. Enrique Calleja (Uni Madrid, Spain): MBE growth of ordered InGaN/GaN nano/microrods: basics and applications.
• Prof. Edward Yi Chang (NCTU, Taiwan): High performance GaN HEMT technologies.
• Prof. Adrian Ionescu (EPFL, Switzerland): Millivolt technology for low power digital and sensing applications.
• Dr. Byungil Kwak (SK Hynix, Korea): DRAM Peripheral Transistor Scaling using logic technologies – Future Challenges.

Saturday, December 16, 2017

People Should Really Be Thankful For Free Software Developers – #FOSS Post https://t.co/6a2XhakKzM #opensource


from Twitter https://twitter.com/wladek60

December 16, 2017 at 04:18PM
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Surrogate #modeling and variability analysis of on‐chip spiral #inductors https://t.co/X2hm6rNKwd


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December 16, 2017 at 11:03AM
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Thursday, December 14, 2017

#AMD pushing out #opensource Vulkan driver https://t.co/wRk48P3MpN https://t.co/wX73QVJPrV


from Twitter https://twitter.com/wladek60

December 14, 2017 at 08:24AM
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#AMD pushing out #opensource Vulkan driver https://t.co/wRk48P3MpN


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December 14, 2017 at 08:24AM
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Tuesday, December 12, 2017

Attacks, Myths, and Defenses; Chapter 5: Hardware #Trojans in Analog, Mixed-Signal, and #RF #ICs https://t.co/LECOn4v6P3 #paper https://t.co/VGQ2WS3u3e


from Twitter https://twitter.com/wladek60

December 12, 2017 at 01:14PM
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Sunday, December 10, 2017

Kink effect in ultrathin #FDSOI #MOSFETs https://t.co/nOep8STDH9 #paper


from Twitter https://twitter.com/wladek60

December 10, 2017 at 11:08AM
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Friday, December 8, 2017

Out-of-equilibrium body potential measurements in pseudo-MOSFET for sensing applications https://t.co/BuunqVdHvy #paper


from Twitter https://twitter.com/wladek60

December 08, 2017 at 04:40AM
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How to use #Fossdroid to get #OpenSource Android apps https://t.co/tVb3nAeB6B


from Twitter https://twitter.com/wladek60

December 08, 2017 at 04:04AM
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Wednesday, December 6, 2017

Saturday, December 2, 2017

Not Your Father’s #Analog #Computer https://t.co/IPAF5TMHws #paper


from Twitter https://twitter.com/wladek60

December 02, 2017 at 08:58PM
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Demystifying #SPICE #noise #simulation https://t.co/er91QH6ub7 #paper


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December 02, 2017 at 08:54PM
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Sunday, November 26, 2017

[paper] Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s

Recent Developments in Qucs-S Equation-Defined Modelling of Semiconductor Devices and IC’s
Mike Brinson, and Vadim Kuznetsov
International Journal of Microelectronics and Computer Science
2017, Volume 8, Number 1 
ISSN 2080-8755 / eISSN 2353-9607

Abstract—The Qucs Equation-Defined Device was introduce roughly ten years ago as a versatile behavioural simulation component for modelling the non-linear static and dynamic properties of passive components, semiconductor devices and IC macromodels. Today, this component has become an established element for building experimental device simulation models. It’s inherent interactive properties make it ideal for device and circuit modelling via Qucs schematics. Moreover, Equation-Defined Devices often promote a clearer understanding of the factors involved in the construction of complex compact semiconductor simulation models. This paper is concerned with recent advances in Qucs-S/Ngspice/XSPICE modelling capabilities that improve model construction and simulation run time performance of Equation-Defined Devices using XSPICE model syntheses. To illustrate the new Qucs-S modelling techniques an XSPICE version of the EPFL EKV v2.6 long channel transistor model together with other illustrative examples are described and their performance simulated with Qucs-S and Ngspice [read more...]

Fig: EKV2.6 Qucs-S long channel static I/V model test bench and typical simulated I/V output characteristics as Qucs-S Equation-Defined Model



Assessment of Germanane Field-Effect Transistors for CMOS Technology https://t.co/9nONoZjS12 #paper


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November 26, 2017 at 12:25AM
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Saturday, November 25, 2017

#Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors https://t.co/Ql0DQWQ5hf


from Twitter https://twitter.com/wladek60

November 25, 2017 at 06:09PM
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Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond https://t.co/sGwqx6xw7E #paper


from Twitter https://twitter.com/wladek60

November 25, 2017 at 04:31PM
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TCAD Mobility #Model of III-V Short-Channel Double-Gate FETs Including Ballistic Corrections https://t.co/xAcLMzh4S9


from Twitter https://twitter.com/wladek60

November 25, 2017 at 06:04PM
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Friday, November 24, 2017

A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its... https://t.co/zg9x86qUaH


from Twitter https://twitter.com/wladek60

November 24, 2017 at 09:39PM
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A Compact Quasi-Static Terminal Charge and Drain Current #Model for Double-Gate Junctionless Transistors and Its Circuit Validation - IEEE Journals & Magazine https://t.co/NgDkKN8gxr


from Twitter https://twitter.com/wladek60

November 24, 2017 at 09:39PM
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Wednesday, November 22, 2017

Determination of well flat band condition in thin film FDSOI transistors using C-V measurement for accurate parameter extraction https://t.co/6djtGE7OZV #paper https://t.co/RYLH3fSGhg


from Twitter https://twitter.com/wladek60

November 21, 2017 at 11:54PM
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A 32 kb 9T near-threshold SRAM with enhanced read ability at ultra-low voltage operation https://t.co/R0t2mdhbMF #paper


from Twitter https://twitter.com/wladek60

November 21, 2017 at 11:18PM
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Tuesday, November 21, 2017

[mos-ak] [Final Program] 10th International MOS-AK Workshop in the Silicon Valley

10th International MOS-AK Workshop 
(co-located with the CMC Meeting and IEDM Conference) 
Silicon Valley, December 6, 2017 

Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.

Scheduled,10th subsequent MOS-AK modeling workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:
<http://www.mos-ak.org/silicon_valley_2017/>

Venue: 
Cadence Design Systems 
2655 Seely Ave
San Jose, CA 95134
Building 5 (map)

Online Workshop Registration is still open
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
WG211117

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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus... https://t.co/vekyZr5RmC


from Twitter https://twitter.com/wladek60

November 21, 2017 at 04:49PM
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Three-dimensional vertical Si nanowire MOS capacitor #model structure for the study of electrical versus geometrical Si nanowire characteristics https://t.co/OnvqDTh6l2


from Twitter https://twitter.com/wladek60

November 21, 2017 at 04:48PM
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Thursday, November 16, 2017

#Banks are increasingly turning to #opensource projects. Here’s why. https://t.co/FHoU5O7jdZ


from Twitter https://twitter.com/wladek60

November 16, 2017 at 12:54PM
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Innovations in Electronics and Communication Engineering

Proceedings of the Fifth ICIECE 2016
Volume 7 of Lecture Notes in Networks and Systems
H. S. Saini, R. K. Singh, K. Satish Reddy
Springer, 8 Nov 2017 - Technology & Engineering - 596 pages
ISBN 9811038120, 9789811038129

The book contains high quality papers presented in the Fifth International Conference on Innovations in Electronics and Communication Engineering (ICIECE 2016) held at Guru Nanak Institutions, Hyderabad, India during 8 and 9 July 2016. The objective is to provide the latest developments in the field of electronics and communication engineering specially the areas like Image Processing, Wireless Communications, Radar Signal Processing, Embedded Systems and VLSI Design. The book aims to provide an opportunity for researchers, scientists, technocrats, academicians and engineers to exchange their innovative ideas and research findings in the field of Electronics and Communication Engineering [read more...]

Tuesday, November 14, 2017

The Pentagon is set to make a big push toward #opensource software next year https://t.co/EMWCKvEoQM


from Twitter https://twitter.com/wladek60

November 14, 2017 at 10:45PM
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3 #opensource alternatives to AutoCAD https://t.co/ysUQCGiq8X https://t.co/V68oi64jF3


from Twitter https://twitter.com/wladek60

November 14, 2017 at 10:38AM
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7th All-Russian Workshop on CAD of IC Design

7th All-Russian Workshop on computer aided design (CAD) of integrated circuits (IC) to be held at NRNU MEPhI on December 12-14, 2017. The free workshop is organized by NRNU MEPhI jointly with Cadence Design Systems. The program and further information about the Workshop is available via site cad.mephi.ru.

Program 
(with timetable and detailed information in pdf format)
12 December 2017
08:45 - 09:15Registration (University entrance)
09:30 - 13:00Conference hall 3rd floor of the main lecture building
- Synthesis in Genus (28nm technology)
- Introduction to Joules
- Innovus 17.1 Topical Introduction
13:00 - 14:00
Lunch break
14:00 - 18:15Conference hall 3rd floor of the main lecture building
- Introduction to Stylus
- Physical verification with the help of PVS
- A new generation of verification software - Xcelium and Indago
- The history and future of megatrends in EDA
13 December 2017
9:00 - 18:00
Laboratory V-315 of the Department of Electronics
(Practical classes)
- Behavioral modeling
- Logical synthesis
- Simulation of a Verilog modules with element delays
- Physical design of the digital modules
- Verification of the digital modules
14 December 2017


10:00 - 12:00Laboratory V-315 of the Department of Electronics
- Working discussions, summarizing

Contact Event Secretary: E. Atkin
+7 495 7885699 ext. 9155
+7 499 3242597

Saturday, November 11, 2017

#paper A temperature‐dependent surface potential‐based algorithm for extraction of Vth in homojunction TFETs https://t.co/uhg1laMLY2


from Twitter https://twitter.com/wladek60

November 11, 2017 at 07:15PM
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#Tesla-inspired Chinese EV startup launches all-electric SUV using #opensource patents https://t.co/LYByI2RCyr


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November 11, 2017 at 09:39AM
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Tuesday, November 7, 2017

ngspice release 27, September 17th, 2017 https://t.co/0jSKnj19no #Modeling https://t.co/c5INhqX0yD


from Twitter https://twitter.com/wladek60

November 07, 2017 at 08:36PM
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Monday, November 6, 2017

A Near-Threshold Voltage Oriented Library for High-Energy Efficiency and Optimized Performance in 65nm CMOS https://t.co/OOQYhqgx9U #paper


from Twitter https://twitter.com/wladek60

November 06, 2017 at 08:26PM
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Friday, November 3, 2017

[paper] Validation of MOSFET Model Source–Drain Symmetry

Validation of MOSFET Model Source-Drain Symmetry
Colin C. McAndrew
IEEE TED, Vol. 53, No. 9, Sep. 2006
doi: 10.1109/TED.2006.881005

Abstract: Symmetry around Vds= 0 is a critical requirement for MOSFET models, e.g. as it affects the ability of a model to simulate distortion accurately for some RF CMOS mixers. The Gummel symmetry test (GST) has been the standard test used to evaluate the symmetry of MOSFET models. However, this test is only applicable to DC current, and is only valid when there is negligible gate or substrate current. This paper presents a DC symmetry test that is applicable in the presence of gate and substrate currents, and an AC symmetry test that is simple and effective in verifying symmetry of Cgs and Cgd.


FIG: Biasing scheme for dc symmetry testing. 

Thursday, November 2, 2017

Circuit-aging #modeling based on dynamic MOSFET degradation and its verification (#SISPAD) https://t.co/QgJ5UIe7Yx


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November 02, 2017 at 10:43AM
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Analytical #modeling is both science and art https://t.co/DBdMqRJqkU https://t.co/G45cufzKTb


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November 02, 2017 at 10:07AM
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#Modeling of flicker noise in quasi-ballistic FETs - IEEE Conference Publication https://t.co/JpropPaK27


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November 02, 2017 at 10:05AM
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Circuit-aging #modeling based on dynamic MOSFET degradation and its verification - IEEE Conference Publication https://t.co/QnZG525Y7R


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November 02, 2017 at 10:04AM
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Tuesday, October 31, 2017

[mos-ak] [2nd Announcement and Call for Papers] 10th International MOS-AK Workshop in the Silicon Valley

10th International MOS-AK Workshop
(co-located with the CMC Meeting and IEDM Conference)
http://www.mos-ak.org/silicon_valley_2017/
Silicon Valley, December 6, 2017
2nd Announcement and Call for Papers 

Together with local organization teams Cadence Design Systems and Keysight Technologies as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Compact Modeling Workshop which will be organized for consecutive 10th time in the timeframe of coming IEDM and CMC Meetings.

Planned,10th MOS-AK workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates: 
  • Call for Papers - Sept. 2017
  • 2nd Announcement - Oct. 2017
  • Final Workshop Program - Nov. 2017
  • MOS-AK Workshop - Dec.6, 2017 
Venue: 
Cadence Design Systems 
2655 Seely Ave
San Jose, CA 95134
Building 5 (map)

Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Prospective authors should submit abstract online
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

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[paper] Review of physics-based compact models for emerging nonvolatile memories

Nuo Xu1, Pai-Yu Chen2, Jing Wang1, Woosung Choi1, Keun-Ho Lee3, Eun Seung Jung3, Shimeng Yu2
Review of physics-based compact models for emerging nonvolatile memories
1Device Lab, Samsung Semiconductor Inc., San Jose, CA 95134, USA
2School of ECEE, Arizona State University, Tempe, AZ 85281, USA
3Semiconductor R&D Center, Samsung Electronics, Hwasung-si, Gyeonggi-do, Korea
Journal of Computational Electronics, 2017, pp. 1-13
https://doi.org/10.1007/s10825-017-1098-0

Abstract: A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development [read more...]

https://doi.org/10.1007/s10825-017-1098-0

SSCS Members Who Are 2017 IEEE Fellows


SSCS members who are IEEE Fellows pose with SSCS President, Jan Van der Spiegel and IEEE President, Karen Bartelson at ISSCC 2017. From left to right- Jan Van der Spiegel, Zhihua Wang, Andrei Vladimirescu, Carlo Samori, Borivoje Nikolic, Junichi Nakamura, Deog-kyoon Jeong, Hideto Hidaka, Payam Heydari, Edoardo Charbon, and Karen Bartleson 

Monday, October 30, 2017

How to pick a #winning #IoT #business #model https://t.co/YjMfxPAEZB https://t.co/SDOt080Ka6


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October 30, 2017 at 03:39PM
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FOSDEM 2018 CAD and Open Hardware Devroom Call for Participation


This is the call for participation in the FOSDEM 2018 devroom on Computer Aided Design (CAD) tools and Open Hardware, to be held on Saturday 3 February 2018 in Brussels, Belgium. We are looking for contributions under the form of talks and tutorials covering the following main topics:
  • Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  • Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce,GHDL, Icarus and Verilator)
  • Any other EDA tools such as high-level tools for digital hardware design (e.g. Migen) and HDL synthesis tools (e.g. Yosys)
  • Field solvers such as openEMS
  • Mechanical 2D and 3D CAD tools such as LibreCAD, FreeCAD, OpenSCAD andSolveSpace
  • Open Hardware projects such as the Teres laptop and the lowRISC SoC
  • Inter-project opportunities for collaboration
We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS CAD and Open Hardware developments, share knowledge and identify opportunities to collaborate on development tasks. This devroom is an evolution of the EDA devroom we organised in 2015, 2016 and 2017.

The submission process: Please submit your proposals at

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself under Person -> Description -> Abstract. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "CAD and Open Hardware Devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates
  • 1 December 2017: deadline for submission of proposals
  • 8 December 2017: announcement of final schedule
  • 3 February 2018: devroom day
Recordings: The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.

Mailing list: Feel free to subscribe to the mailing list of the CAD and Open Hardware devroom to submit ideas, ask questions and generally discuss about the event:

Spread the word!

Thursday, October 26, 2017

#Modeling the Performance of Nano Machined CMOS Transistors for Uncooled IR Sensing https://t.co/p4RnuHkJiZ


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October 26, 2017 at 11:26AM
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Wednesday, October 25, 2017

UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper... https://t.co/WSUSekJ1ky


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October 25, 2017 at 08:47PM
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UNIST Researchers Develop Highly Stable #Perovskite #Solar #Cells https://t.co/g1CN5I44r1 #paper https://t.co/p6Jr0nPqF1


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October 25, 2017 at 08:47PM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper https://t.co/LglxkaZ9PP


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October 25, 2017 at 11:59AM
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Novel Superjunction #LDMOS (>950 V) With a Thin Layer #SOI https://t.co/1NqFJ4rAZB #paper


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October 25, 2017 at 11:59AM
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A Planar Junctionless FET Using SiC With Reduced Impact of Interface Traps: Proposal and Analysis https://t.co/g3qPsLKIqB #paper


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October 25, 2017 at 11:34AM
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Tuesday, October 24, 2017

Cryogenic characterization of CMOS technologies

A. Beckers, F. Jazaeri, A. Ruffino, C. Bruschini, A. Baschirotto and C. Enz
Cryogenic characterization of 28 nm bulk CMOS technology for quantum computing
47th ESSDERC, Leuven, Belgium, 2017, pp. 62-65.

Abstract: This paper presents the first experimental investigation and physical discussion of the cryogenic behavior of a commercial 28 nm bulk CMOS technology. Here we extract the fundamental physical parameters of this technology at 300,77 and 4.2 K based on DC measurement results. The extracted values are then used to demonstrate the impact of cryogenic temperatures on the essential analog design parameters. We find that the simplified charge-based EKV model can accurately predict the cryogenic behavior. This represents a main step towards the design of analog/RF circuits integrated in an advanced bulk CMOS process and operating at cryogenic temperature for quantum computing control systems [read more...doi: 10.1109/ESSDERC.2017.8066592



R. M. Incandela, L. Song, H. A. R. Homulle, F. Sebastiano, E. Charbon and A. Vladimirescu
Nanometer CMOS characterization and compact modeling at deep-cryogenic temperatures
47th ESSDERC, Leuven, Belgium, 2017, pp. 58-61.

Abstract: The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK [read more...doi: 10.1109/ESSDERC.2017.8066591