Saturday, 19 August 2017

Performance Assessment of A Novel Vertical Dielectrically Modulated TFET-Based Biosensor - IEEE Xplore #paper https://t.co/jRvJS3MUTs


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August 19, 2017 at 10:11AM
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Friday, 18 August 2017

A Threshold Voltage #Model of Tri-Gate Junctionless Field-Effect Transistors Including Substrate Bias Effects https://t.co/sEviQXJbB3


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August 18, 2017 at 01:42PM
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[paper] Improvements to a compact MOSFET model for design by hand

Improvements to a compact MOSFET model for design by hand
A. de Jesus Costa, F. Martins Cardoso, E. Pinto Santana and A. I. Araújo Cunha
15th IEEE NEWCAS
Strasbourg, France, 2017, pp. 225-228
doi: 10.1109/NEWCAS.2017.8010146

Abstract: In this work, an improved version of the basic structure of a compact MOSFET model and the respective parameters extraction methodology are proposed. The aim of this approach is to increase accuracy in hand calculations for analog circuit design without significantly increasing its complexity. The influences of both inversion level and channel length are considered in the modeling of a few features such as mobility, threshold voltage and onset of saturation. Simple design examples of current sinks and sources are accomplished to compare the basic and the improved models [read more...]

Thursday, 17 August 2017

[mos-ak] [Workshop Program] 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven Sept.11 2017

15th MOS-AK ESSDERC/ESSCIRC Compact Modeling Workshop
Leuven; Monday Sept.11, 2017 (8:30-17:00)
Workshop Program online http://www.mos-ak.org/leuven_2017/ 

Together with International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and Jean-Michel Sallese, EPFL (CH), Daniel Tomaszewski, ITE (PL), MOS-AK Technical Program Coordinators as well as all the Extended MOS-AK TPC Members, we have pleasure to invite to the 15th consecutive MOS-AK workshop organized as an integral part of the ESSDERC/ESSCIRC Conferences in Leuven on Sept.11, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Final Program of 15th MOS-AK ESSDERC/ESSCIC Workshop is available online:

(Parkstraat 45, 3000 Leuven) 
room AV 91.12

Online MOS-AK/Leuven Workshop Registration:
(any related inquiries can be sent to register@mos-ak.org)

The MOS-AK workshop will be followed by four session of the ESSDERC Track4 "Device and Circuit Compact Modeling". These four lecture sessions include one invited and 14 pear reviewed papers in the compact/SPICE modeling and Verilog-A standardization domain:

Tuesday September 12, 2017 (11:00-12:20)
Chair: Wladek Grabinski - MOS-AK; Cristell Maneux - U-Bordeaux;
Tuesday September 12, 2017 (14:00-15:20)
Chair: Thierry Poiroux - CEA
Tuesday September 12, 2017 (16:40-18:00)
Chair: Jean-Michel Sallese - EPFL; Daniel Tomaszewski - ITE;
Wednesday September 13, 2017 (14:20-15:40)
Chair: Benjamin Iniguez - URV; Sadayuki Yoshitomi - Toshiba;

MOS-AK Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication

WG170817

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Wednesday, 16 August 2017

Review of commercial SiC MOSFET models: Topologies and equations - IEEE Xplore #paper https://t.co/LS090HojeE


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Monday, 14 August 2017

[paper] Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System

Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System
T. K. Maiti, Member, IEEE, L. Chen, H. Zenitani, H. Miyamoto, Member, IEEE,
M. Miura-Mattausch, Fellow, IEEE, and H. J. Mattausch, Senior Member, IEEE
in IEEE Journal on Multiscale and Multiphysics Computational Techniques, 
vol. 2, no. , pp. 124-133, 2017.
doi: 10.1109/JMMCT.2017.2731878

Abstract: This paper presents a compact electro-mechanical-fluidic system-modeling method for multidomain system simulation based on multidomain physics that considers the total energy conservation condition, in terms of respective potential and flow quantities. Models for electrical, mechanical, and fluidic domains are developed to design the example of a blood pumping system, where the blood flow is driven by electrically controlled organic actuators. The electrical domain includes an organic mosfet-based control circuit, the mechanical domain includes organic actuators, and the fluidic domain includes a flexible fluid-flow channel. Control circuit, actuators, and fluid models are coupled through equivalent circuits, where interconnection relationships between two neighboring domains are expressed using the energy conservation concept. The model accuracy is verified with finite element method (FEM) based numerical simulation. Significantly faster simulation speed than with FEM and good accuracy were achieved [read more...]

TABLE: CORRESPONDING FORCE AND FLOW EQUATIONS FOR ELECTRICAL AND
MECHANICAL DOMAINS ARE SUMMARIZED [21]-[23]


[21] S. D. Senturia, Microsystems Design. Norwell, MA: Kluwer Academic Publisher, 2001.
[22] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Modeling of electrostatically actuated fluid flow system for mixed-domain simulation,” in 20th Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 190-193, Sept. 2015, USA.
[23] T. K. Maiti, L. Chen, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Mixed domain compact modeling framework for fluid flow driven by electrostatic organic actuators,” in 45th European Solid-State Device Research Conference (ESSDERC), pp. 52-55, Sept. 2015, Austria. 

A General and Transformable #Model Platform for Emerging Multi-Gate MOSFETs - IEEE Xplore Document https://t.co/q27OgRX5Fd


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August 14, 2017 at 02:01PM
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Mini-Colloquium (MQ) on Nanoelectronics

AGENDA
DATE: Saturday Aug. 26, 2016
VENUE: IIT Kanpur L16
This Mini-Colloquium (MQ) on Nanoelectronics is being hosted by the IEEE Electron Device Society UP Chapter in collaboration with the Department of Electrical Engineering at IIT Kanpur. Distinguished speakers from renowned universities will be presenting on wide range of topics in Nanoelectronics. The MQ will be organized into 1 hour talks by the speakers. The agenda would be as follows:

TimeTopicSpeaker
9:00 - 9:15Inauguration
9:15 - 9:30High Tea
9:30 - 10:30Nanotransistors with 2D materials: Opportunities and ChallengesProf. Navkanta Bhat
IISc
10:30 - 11:30Revisiting gate C-V characterization for high mobility semiconductor MOS devicesProf. Anisul Haque
East West Univ.
11:30 - 11:45Tea
11:45 - 12:45Prof. V. Ramgopal Rao
IIT Delhi
12:45 - 14:15Lunch
14:15 - 15:15ASM-HEMT - First Industry Standard Compact Model for GaN HEMTsProf. Yogesh Singh Chauhan
IIT Kanpur
15:15 - 16:15Spintronics - Perspectives and ChallengesProf. Brajesh Kumar Kaushik
IIT Roorkee
16:15 - 16:30Tea
16:30 - 17:30Advanced Hetero structure based Nano Scale MOSFETsProf. Chandan Kumar Sarkar
Jadavpur Univ.
Coordinator: Dr. Yogesh S.Chauhan IIT Kanpur, India
Website: http://www.iitk.ac.in/nanolab/MQ/index.html

Monday, 7 August 2017

ICCDCS 2017

Tenth International Caribbean Conference on Devices, Circuits and Systems (ICCDCS 2017)

June 5-7 2017, Cozumel, México
08:00 to 9:00RegistrationRegistrationRegistration 
08:45 to 9:00Opening Ceremony
09:00 to 10:00Key Note 1: "Adaptive Heterogenous Multi-Core Technologies- Intelligent, Interconnected and Integrated Cyber-Physical Systems (I3CPS)"Jürgen BeckerKey Note 3: "The Life and Times of Eugeni García"Benjamín ÍñiguezKey Note 6: "On the Extraction Methods for MOSFET Series Resistance and Mobility Degradation using a Single Test Device",Adelmo Ortiz Conde
10:00 to 10:30BreakBreakBreak
10:30 to 12:30Session 1Session 3Session 5
10:30 to 10:50"Model Based Photopic Electroretinogram Source Separation: A Multiresolution Analysis Approach"Prashanth Chetlur Adithya, Alaql Abdulrahman, Radouil Tzekov, Ravi Sankar and Wilfrido Moreno"A Programmable CMOS Voltage Controlled Ring Oscillator for Radio-Frequency Diathermy On-chip Circuit"Antonio Corres- Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez"Health Index Assessment for Power Transformers with Thermal Upgraded Paper up to 230kV, Using Fuzzy Inference. Part II: A Sensibility Analysis"Diego Chacón, Juan Pablo Lata and Ricardo Medina
10:50 to 11:10"Analytical Model Parameter Determination for Microwave On-Chip Inductors up to the Second Resonant Frequency"José Valdés Rayón, Reydezel Torres and Roberto Murphy"A logarithmic CMOS image sensor with wide output voltage swing range"Fernando Campos, Mário Bordon, Marcelo Silva and Jacobus Swart"Implementation Model Using a Hippocratic Protocol in Mobile Terminals with NFC Technology"Carlos Kowalevicz, Jose Pirrone Puma and Monica Huerta
11:10 to 11:30"Energy Consumption Improvement based on Distance Adaptive Modulation in Optical Elastic Network"Sabi Bandiri, Rafael Braga, Tales Pimenta and Danilo Spadoti"Improving Magnitude Response in Two-Stage Corrector Comb Structure"Gordana Jovanovic Dolecek and Lyda Herrera Sepulveda"Internet of Things as an Attack Vector to Critical Infrastructures of Cities"Pablo Leonidas Gallegos-Segovia, Jack Fernando M. Larios-Rosillo and Erwin Jairo Sacoto-Cabrera
11:30 to 11:50"Switching Region Analysis for SOTB Technology"Carlos Cortes Torres, Nobuyuki Yamasaki and Hideharu Amano"Analysis of the influence of the buffer layer in the characteristic impedance of electro-optic modulators"Ana Gabriela Correa Mena, Luis Alejandro González Mondragón, Leidy Johana Quinteros Rodríguez, José Valdés Rayón and Ignacio Enrique Zaldívar Huerta"Sensors for Parkinson's Disease Evaluation"Raquel Torres, Monica Huerta, Ricardo Gonzalez, Roger Clotet and Juan Pablo Bermeo
11:50 to 12:10"Scalable Models to Represent the Via-Pad Capacitance and Via-Traces Inductance in Multilayer PCB High-Speed Interconnects"Abraham Isidoro Muñoz, Miguel Angel Tlaxcalteco Matus, Reydezel Torres Torres and Gaudencio Hernandez Sosa"Impact of neglecting the metal losses on the extraction of the relative permittivity from PCB transmission line measurements"Erika Yazmin Teran Bahena and Reydezel Torres Torres"QoS Evaluation of VPN in a Raspberry Pi devices over Wireless Network"Luis Caldas, Juan Jara and Mónica Huerta
12:10 to 12:30"Implementation of a Reconfigurable Neural Network in FPGA"Janaina Oliveira, Robson Moreno, Odilon Dutra and Tales Pimenta"Reconfigurable FIR Filter Coefficient Optimization in Post-Silicon Validation to Improve Eye Diagram for Optical Interconnects",Ismael Duron-Rosales, Francisco E. Rangel-Patino, Jose E. Rayas-Sanchez, Jose L. Chavez-Hurtado and Nagib Hakim"A Proposed Digital Predistorter Based on NLMS and PSO Algorithms"Omar Alngar, Walid El-Deeb and El-Sayed El-Rabaie
12:30 to 15:00LunchLunchClosing remarks
15:00 to 16:00Key Note 2: "Following the Path of 3D Integration"Malgorzata Chrzanowska-JeskeKey Note 4: “Modeling and Verification of Heterogeneous Systems”Filipe Vinci
16:00 to 16:15BreakPoster Introduction*
16:15 to 17:55Session 2Session 4
16:15 to 16:35"MRAM control Transistor Resilience against Heavy-Ion Impacts", Walter Enrique Calienes Bartra, Raphael Brum, Guilherme Flach and Ricardo ReisBreak w/poster session (16:15 to 17:00)
16:35 to 16:55"A Charge-controlled Memristor Model for Image Edge Detection with a Memristive Grid"Arturo Sarmiento and Yojanes Rodríguez-Velásquez
16:55 to 17:15"Characterization and modelling of Ag/TiO2/ITO devices exhibiting bipolar memristive properties", Jesús Jiménez-León, Arturo Sarmiento, Carlos De La Cruz Blas and Cristina Gomez-Polo
17:15 to 17:35"Assessing the accuracy of the open, short and open-short de-embedding methods for on-chip transmission line s-parameters measurements"Juan Garcia Santos and Reydezel TorresKey Note 5: (17:00 to 18:00) "Innovation by ASIC design and emerging substream markets"Jacobus Swart
17:35 to 17:55"Evaluation of Interconnects Based on Electromigration Criteria and Circuit Performance"Rafael Nunes, Roberto Orio and Jacobus Swart
19:00Welcome Cocktail
19:30Conference Banquet
Poster Session:
"Differentiated synchronization plus FHIR a solution for EMR's Ecosystem", Roger Clotet, Emilio Hernández and Monica Karel Huerta
"Design and Validation of a Portable Radio-Frequency Diathermy Prototype", Antonio Corres-Matamoros, Esteban Martinez-Guerrero and Jose E. Rayas-Sanchez
"Stimulating social interaction among elderly people through sporadic social networks", Jorge Osmani Ordoñez-Ordoñez, Jack Fernando Bravo-Torres, Oscar David Sari-Villa, Esteban Fernando Ordoñez-Morales, Martín López-Nores and Yolanda Blanco-Fernández
"Sensing Climatic Variables in a Orchid Greenhouse", Luis Fernandez, Mónica Huerta, Giovanni Sagbay, Roger Clotet and Angel Soto
"Low cost system for monitoring physiological signals using FPGA and Android Tablet", J. Bucheli, D. Rivas, J. Gavilema, D. Mullo, J. L. Carrillo, M. Huerta

Thursday, 3 August 2017

Basics of MOSFET Modeling


Basics of MOSFET Modeling with LabVIEW/LTspice 
  • Introduction to MOSFET Models 
  • Functions and Parameter Extraction
  • visit http://mosfet-engineer.blogspot.com

[paper] On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices

On the Physical Behavior of Cryogenic IV and III–V Schottky Barrier MOSFET Devices
Mike Schwarz, Member, IEEE, Laurie E. Calvet, Member, IEEE, John P. Snyder, Member, IEEE, Tillmann Krauss, Udo Schwalke, Senior Member, IEEE, and Alexander Kloes, Senior Member, IEEE
in IEEE TED , vol.PP, no.99, pp.1-8
doi: 10.1109/TED.2017.2726899

Abstract: The physical influence of temperature down to the cryogenic regime is analyzed in a comprehensive study and the comparison of IV and III-V Schottky barrier (SB) double-gate MOSFETs. The exploration is done using the Synopsys TCAD Sentaurus device simulator and first benchmarked with experimental data. The important device physics of both SB-MOSFETs and conventional MOSFETs are reviewed. The impact of temperature on device performance down to the liquid-nitrogen regime is then explored. We find reduced drive currents in SB-MOSFETs fabricated on small effective mass materials and that SB lowering can significantly improve SB-MOSFETs, especially at low temperatures [read more...]

This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination

Tuesday, 1 August 2017

[paper] Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS


T. Komawaki, M. Yabuuchi, R. Kishida, J. Furuta, T. Matsumoto and K. Kobayashi
Circuit-level simulation methodology for Random Telegraph Noise by using Verilog-AMS
2017 IEEE ICICDT, Austin, TX, USA, 2017, pp. 1-4.
doi: 10.1109/ICICDT.2017.7993526

Abstract: As device sizes are downscaled to nanometer, Random Telegraph Noise (RTN) becomes dominant. It is indespensable to accurately estimate the effect of RTN. We propose the RTN simulation method for analog circuits. It is based on the charge trapping model. We replicate the RTN-induced threshold voltage fluctuation to attach a variable DC voltage source to the gate of MOSFET by using Verilog-AMS. We confirm that drain current of MOSFETs temporally fluctuates. The fluctuations of RTN are different for each MOSFET. Our proposed method can be applied to estimate the temporal impact of RTN including multiple transistors. We can successfully replicate RTN-induced frequency fluctuations in 3-stage ring oscillators as similar as the measurement results [read more...]

Circuit Design and Simulation Project using eSim

Invitation to participate in Circuit Design and Simulation Project using eSim

The FOSSEE (Free and Open Source Software for Education) project based at lIT Bombay has initiated a Circuit Design and Simulation Project using esim (an open source EDA tool for circuit design, simulation, analysis and PCB design).

Interested candidates can take any solved electronic circuit from any source and redesign it using eSim and submit it to us. Candidates will be rewarded with certificates and honorarium after a review process. These circuits will also be published on our website under an appropriate open source license. 

For more details, please visit: http://esim.fossee.in/circuit-simulation-project









Wednesday, 26 July 2017

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw


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July 26, 2017 at 11:39AM
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[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten
"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 
in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

Tuesday, 25 July 2017

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow
Compact On-Wafer Test Structures for Device RF Characterization
in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]



Saturday, 8 July 2017

[mos-ak] [2nd Announcement and Call for Papers] 15th MOS-AK ESSDERC/ESSCIRC Workshop

MOS-AK ESSDERC/ESSCIRC Workshop
http://www.mos-ak.org/leuven_2017/
September 11, 2017 Leuven
2nd Announcement and Call for Papers


Together with the ASCENT Network represented by Profs Jim Greer and Nicolas Cordero as well as  International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 15th MOS-AK Compact Modeling Workshop which will be organized for consecutive 15time as in integral part of the ESSDERC/ESSCIRC Conference in Leuven on Sept.11, 2017.

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:
  • Preannouncement - March 2017
  • Call for Papers - June 2017
  • Final Workshop Program - August 2017
  • MOS-AK Workshop - Sept.11, 2017

Venue: Leuven (B) <http://www.esscirc-essderc2017.org/venue>

Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Speakers: (tentative list in alphabetic order)
  • Nicolas Cordero, Tyndal (IRL)
  • Denis Flandre, CUL (B)
  • Jim Greer, Tyndal (IRL)
  • Benjamin Iniguez URV (SP)
  • Marcelo Pavanello, FEI (BR)
  • Jean-Pierre Raskin, CUL (B)
  • Wim Schoenmaker, Magwel (B)
  • Chika Tanaka, Toshiba (J)
  • Ashkhen Yesayan, IRPhE (AM)
Prospective authors should submit abstract online
Manuscript submission deadline: 31sth July 2017 (Monday)
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration
using online registration form <http://www.esscirc-essderc2017.org/howtoregister>
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
WG080717

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Tuesday, 4 July 2017

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping
M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;
in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]

Sunday, 25 June 2017

Multiple Honors for E3S Theme Leader, Professor Tsu-Jae King Liu

(March 1, 2017) –   The Center for Energy Efficient Electronics Science is proud to announce Prof. Tsu-Jae King Liu has been named a newly elected member of the National Academy of Engineering. Prof. King Liu, who leads the E3S Nanomechanics theme was elected this year as one of only three members from UC Berkeley to this highest professional honor to an engineer. Last year in August, Prof. King Liu has also been chosen to serve on the Board of Directors at Intel Corporation. She was welcomed by Intel Chairman Andy Bryant: “[Prof. King Liu] brings a wealth of expertise in silicon technology and innovation that will be valuable for Intel in many areas as we navigate a significant business transition while continuing to lead in advancing Moore’s Law and harnessing its economic value.”In addition to this distinguished honor by Intel, last year the Semiconductor Research Corporation (SRC) announced Prof. King Liu has been selected to receive the 2016 SRC Aristotle Award. This esteemed award was created by the SRC Board of Directors in March 1995 with the intent "to acknowledge outstanding teaching in its broadest sense, emphasizing student advising and teaching." Heartiest congratulations from the entire E3S community to Prof. King Liu for these prestigious honors!

Thursday, 22 June 2017

[paper] Design Strategies for Ultralow Power 10nm FinFETs

Design Strategies for Ultralow Power 10nm FinFETs
Abhijeet Walkeaa, Garrett Schlenvogtbb, Santosh Kurinecaa
aDepartment of Electrical & Microelectronic Engineering, RIT, New York, USA
bTCAD Application Engineer, Silvaco

Received 12 June 2017, Accepted 19 June 2017, Available online 20 June 2017

Abstract: In this work, new design strategies for 10nm node NMOS bulk FinFET transistors are investigated to meet low power (LP) (20pA/μm< IOFF <50pA/μm) and ultralow power (ULP) (IOFF <20pA/μm) requirements using three dimensional (3D) TCAD simulations. The punch-through stop implant, source and drain junction placement and gate workfunction are varied in order to study the impact on the OFF-state current (IOFF), transconductance (gm), gate capacitance (Cgg) and intrinsic frequency (fT). It is shown that the gate length of 20nm for the 10nm node FinFET can meet the requirements of LP transistors and ULP transistors by source-drain extension engineering, punch-through stop doping concentration, and choice of gate workfunction.

[read more https://doi.org/10.1016/j.sse.2017.06.012]

Rising SOI tide lifts Soitec into profit

Soitec SA (Bernin, France), developer of the "smart cut" method of silicon-on-insulator (SOI) wafer production, has reported its first profit for many years and is preparing to invest in facilities in France and possibly Singapore to meet rising demand for SOI wafers...

https://shar.es/1BtAZy


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Wednesday, 14 June 2017

[C4P] IEDM 2017

2017 IEDM CALL FOR PAPERS

The Annual International Electron Devices Meeting will be held at the Hilton San Francisco Union Square San Francisco, CA December 2-6, 2017

Abstract Deadline (four page final paper): August 2nd, 2017

To provide faster dissemination of the conference’s cutting-edge results, the abstract submission deadline has been moved to August 2nd for submission of four-page, camera-ready abstracts. Accepted papers will be published as-is in the proceedings

A Call for Papers flyer is available here: IEDM 2017 Call For Papers.

Customized Call for Papers for each of the technical subcommittee areas are also available:

[paper] Well-Posed Device Models for Electrical Circuit Simulation

Well-Posed Device Models for Electrical CircuitSimulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues [read more...]

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models1:
NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.

NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

1For more information about NEEDS please visit https://nanohub.org/groups/needs/.

Tuesday, 13 June 2017

[mos-ak] [Workshop Program] 2nd Sino MOS-AK Workshop in Hangzhou June 29-30, 2017

2nd Sino MOS-AK Workshop
Hangzhou June 29-30, 2017

Workshop Program online http://www.mos-ak.org/hangzhou_2017/
 
Together with the Honorary Committee Chair LingLing Sun, HangZhou Dianzi University and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as the local coordinator Min Zhang, XMOD (Shanghai) and all the Extended MOS-AK TPC Members, we have pleasure to invite to the 2nd Sino MOS-AK Workshop in Hangzhou on June 29-30, 2017. The MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to the compact/SPICE modeling and its Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
Venue:
会议场所:杭州电子科技大学科技馆
Hangzhou Dianzi University; Science & Technology Museum
Final Program of 2nd Sino MOS-AK Workshop is available online
http://www.mos-ak.org/hangzhou_2017/
http://www.xmodtech.cn/Agenda (local link)
Note: 
Above topic and time arrangement sequence could be with tiny variation due to presenter's personal reason
(演讲顺序可能有改变,敬请留意)


Online MOS-AK/Hangzhou Workshop Registration
http://www.xmodtech.cn/registration
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG13062017

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Tuesday, 16 May 2017

Working Student in Power Management (Intel Munich)

Working Student in Power Management f/m

Job Description: You will be responsible for developing a tool framework to breakdown and manage the power consumption of the Power Management ICs across all projects. The so-called power KPIs Key Performance Indicator are indeed strategic data critical for the competitiveness of battery powered system likes mobiles phones, wearables, IoT devices. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams.

Your main tasks in this full time position will be to:
- Setup a new framework to manage the power data in a new tool and environment
- Migrate existing project power consumption specifications and measurements currently in Excel
- Measure and correlate power KPIs on engineering samples in the post-silicon lab.
- Validate current power modelling approach and propose further model optimizations
- Contribute to the reporting and documentation for other teams and management

[read more...]

Monday, 15 May 2017

A Guide to Creating Robust Device Models

Well-Posed Device Models for Electrical Circuit Simulation
A Guide to Creating Robust Device Models
A. Gokcen Mahmutoglu, Tianshi Wang, Archit Gupta and Jaijeet Roychowdhury
March 25, 2017

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models1:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.
NEEDS Team: Purdue, MIT, UC Berkeley, and Stanford.”

1For more information about NEEDS please visit https://nanohub.org/groups/needs/
https://nanohub.org/resources/26200/download/well-posed_device_models-29453e4.pdf

Tuesday, 25 April 2017

[mos-ak] [C4P] IJHSES / MOS-AK Special Issue

The IJHSES Call for Papers

Special Issue on Advances in the Compact/SPICE Modeling

and its Verilog-A Standardization


Compact/SPICE models for circuit level simulation are essential element of supporting CAD/EDA tools for advanced integrated circuit designs. Rapid mainstream CMOS technology expansion and its scaling into the nanometer regime demands development of a fully physical as well as technology predictive compact/SPICE models for circuit simulation which provides adequate, full range DC, AC, RF, and noise characteristics and its geometry, bias, temperature scaling. These tasks becomes a major R&D challenge. Fast new technology nodes developments also impose new challenges on the compact/SPICE models maintenance and development as well as on its Verilog-A standardization for the model implementation, validation and dissemination.


Standard, core compact models should include and update noise/mismatch and reliability/variability models as well as proximity effects to adequately model nanoscale devices and technologies including nonclassical MOSFETs, multigate FinFETs and nanowire FETs partially/fully-depleted ultra thin body (UTB) SOI, and thin-film transistors (TFTs). High-frequency, high-voltage high-power, high-temperature devices have been extensively investigated, and their compact models to be reviewed, too. Heterogeneous integration opens a new perspectives to the CMOS platform to integrate different materials (III-V/Ge channel, organic and different source/drain injection mechanisms (Schottky-barrier, tunneling, junctionless FETs, and others) and new nonclassical devices, high GHz/THz range detectors, Bio/Med sensors, actuators, MEMS, among others, to support emerging device in future VLSI, IoT applications and beyond.


Therefore, there is an emerging need for an new special issue to review status, challenge and advancement in the compact/SPICE modeling for nanoscaled and emerging technologies as well as beyond. The IJHSES Editors seek original manuscripts for a special issue on advanced in the Compact/SPICE Modeling and its Verilog-A standardization.


Topics to be covered include the following, but are not limited to:

  • Advances in semiconductor technologies and processing

  • Compact Modeling (CM) of the electron devices

  • Verilog-A language for CM standardization

  • New CM techniques and extraction software

  • FOSS TCAD/EDA modeling and simulation

  • CM of passive, active, sensors and actuators

  • Emerging Devices, TFT CMOS and SOI-based memory cells

  • Organic, Bio/Med devices/technology modeling

  • Microwave, RF device modeling, HV/Power device modeling

  • Nanoscale CMOS devices and circuits

  • Technology R&D, DFY, DFT and IC Designs

  • Foundry/Fabless Interface Strategies


Paper Submission and Review Schedule:

  • First call for papers:    April 2017

  • Second announcement:    June 2017

  • Special Issue Due:    Dec. 2017


IJHSES Editor-in-Chief

Co-Editors-in-Chiefs

Guest Editors

Michael Shur

Rensselaer Polytechnic Institute (USA)


Wladek Grabinski

MOS-AK Association (EU)

Benjamin Iñiguez

DEEEA, ETSE, URV (SP)

Jean-Michel Sallese

EPFL Lausanne (CH)

Daniel Tomaszewski

ITE Warsaw (PL)


WG250417

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