Lin Fujian Optoelectronic Device Modeling Laboratory

Yangtze River Delta Integrated Circuit Industrial Application Technology Innovation Center

Jiangsu Jicui Integrated Circuit Application Technology Innovation Center

Lin Fujian Optoelectronic Device Modeling Laboratory

Optoelectronic Device Modeling Laboratory Services

• SPICE model development, characterization, and parameter extraction for silicon photonic waveguides and micro modulators and optical splitters/combiners
• Compact modeling, characterization, and parameter extraction for other advanced photonic devices
• GaN device characterization, EEHemt, ASM model and Angelov models
• InP‑HEMT device characterization, EEHemt model
• SiGe HBT device characterization, SPG/VBIC/HICUM model
• Characterization of micro‑/nano‑devices, internal/external parameter consistency studies, and high‑quality enhancement of existing models
• Ultra‑wideband SPICE models for electrical interconnects, packaging, and passive components
• Modeling of 1/f noise, noise parameters, avalanche effects, self‑heating, channel temperature, and related physical effects
• CNAS‑certified testing and final acceptance testing for major projects
• Other practical modeling services based on customer requirements

Laboratory Contact Information

联系人：小葛，18334212431，邮箱：gemy@jitric.cn

地址：无锡市锡山区凤威路与春江东路交叉口，长三角工业芯谷 A 栋 4 楼

定位：轻资产、高专业、全流程建模验证平台

合作模式：仪器有偿使用、可靠提参、技术赋能

[MEAD] Low-Power Analog IC Design

MEAD Education

June 22-26, 2026

Registration deadline: May 22, 2026

Payment deadline: June 12, 2026

MONDAY, June 22
8:30-12:00 am	MOS Transistor Modeling for Low-Voltage and Low-Power Circuit Design	Christian Enz
1:30-5:00 pm	Design of Low-Power Analog Circuits using the Inversion Coefficient	Christian Enz
TUESDAY, June 23
8:30-10:00 am	Noise Performance of Elementary Circuits	Boris Murmann
10:30-12:00 am	Noise Performance of Filters, Feedback & SC Circuits	Boris Murmann
1:30-3:00 pm	Opamp Topologies and Design: Single-Stage Circuits	Boris Murmann
3:30-5:00 pm	Opamp Topologies: Cascoded and Two-Stage Circuits	Boris Murmann

[Read more and REGISTER]

[papers] Compact/SPICE Modeling

Sun, Jing, Daquan Liu, Hang Li, Wensheng Qian, Jiye Yang, Yabin Sun, Bingyi Ye, Yuhang Zhang, Yang Shen, and Xiaojin Li. "A physics-based and accurate STI-LDMOS compact subcircuit model with modified drift region resistance and gate-drain capacitance." 

Semiconductor Science and Technology (2026).

Abstract: This paper develops a physics-based and accurate shallow trench isolation lateral double-diffused MOS (STI-LDMOS) compact subcircuit model. In the proposed direct-current (DC) model, the drift-region resistances beneath both the STI region and the drain electrode are incorporated, thereby significantly improving its physical fidelity and predictive accuracy of the DC characteristics. For the proposed alternating-current model, the gate–drain capacitance model is decomposed into two components: a gate–drift-region overlap charge model with modified bias dependence derived from BSIM4.5, and a parallel-plate capacitance model for the gate–STI overlap region. In addition, the gate–source capacitance and drain–source charge models are further extended to match the physical structure and to more accurately capture the dynamic characteristics of an STI-LDMOS device. The model parameters are extracted and calibrated, and the proposed subcircuit model is implemented in Verilog-A. Excellent agreement is achieved between the proposed model and both the technology computer-aided design (TCAD) simulation results and the measured data from a 40 V STI-LDMOS device, demonstrating its accuracy and efficiency for circuit-level simulation of STI-LDMOS devices.

Nakos, Miltiadis Κ., Theodoros Α. Oproglidis, Dimitrios Η. Tassis, Constantinos Τ. Angelis, Charalabos Α. Dimitriadis, and Andreas Tsormpatzoglou. "Symmetric physics-based compact core model for double-gate junctionless transistors with ungated extensions." (2026).

Abstract: This work presents a physics-based compact model for double-gate junctionless field-effect transistors, with emphasis on accurately capturing the impact of ungated source/drain extensions on the drain current characteristics. The model is validated against two-dimensional device simulations performed using Silvaco ATLAS for two channel doping concentrations and a wide range of ungated extension lengths. To isolate the contribution of the access regions and clarify the effective channel length, all mobility degradation models were disabled in the simulations, allowing the observed current degradation to be attributed solely to the series resistance of the ungated extensions. The proposed formulation includes an analytical factor ξ that accounts for the reduced electrostatic influence of the source and drain terminals on the channel potential, as well as a closed-form expression for the fringe capacitance associated with the ungated regions. The resulting drain current model demonstrates very good agreement with numerical simulations across different geometries and doping levels. Model symmetry is further verified through a Gummel symmetry test, confirming the physical consistency of the formulation. Owing to its analytical nature and physical transparency, the proposed model is well suited to serve as a core building block for higher-level compact models of JL devices.

Y. Liu, L. Tian, Y. Niu, Y. Xia and W. Chen, "A SPICE-Compatible High-Efficiency Equivalent Mechanical Circuit Method for Electro-Thermal-Mechanical Coupling Simulation," in IEEE Transactions on Electron Devices

doi: 10.1109/TED.2026.3671249.

Abstract: Accurate and efficient modeling and simulation of electro-thermal-mechanical field coupling is essential for evaluating multiphysics effects on devices/circuits’ performance and reliability, as the multiphysics coupling effects become severe in advanced integrated circuits. In our previous work, we developed the equivalent mechanical circuit (EMC) method, thereby constructing a SPICE-compatible equivalent multiphysics circuit framework to simulate electro-thermal-mechanical coupling processes in advanced integrated circuits. However, the computational efficiency of the previous EMC (pEMC) method remains limited compared with the finite element method (FEM), since the pEMC method requires multiple iterations to simulate thermal expansion, even in linear equation systems. In this article, we develop a novel EMC method by proposing voltage-controlled current sources (VCCSs) into the pEMC. Therefore, the novel EMC method can simulate thermal expansion without iteration in linear equation systems. The results demonstrate that the computational efficiency of the novel EMC method achieves a tenfold improvement compared to the pEMC method and exhibits computational efficiency comparable to the FEM under the same number of nodes.

F. Yu et al., "Precise Surface Potential Modeling for Compact DC Models of a-IGZO Thin Film Transistors," in IEEE Transactions on Electron Devices, 

doi: 10.1109/TED.2026.3671772.

Abstract: Many thin film transistor (TFT) models that consider the free and trapped charges, including models for amorphous InGaZnO (a-IGZO) TFTs, rely on the accurate determination of surface potential. In this work, a physically-based initial solution and fast-converging iterative procedure with logarithmic increment are utilized for the precise determination of the surface potential model in TFTs with channels of noncrystalline semiconductors, which have exponentially distributed tails and deep traps in the semiconductors. In particular, the surface potential model does not use special functions, such as the Lambert W function. The precision of the proposed scheme of analytical model and iterative procedure is verified against reference simulations of surface potential, and against measured current–voltage DC characteristics of a-IGZO TFTs, employing a well-established surface-potential-based charge sheet model. The precision of the iterative procedure is in the range of few nV, converging approximately for less than half of the number of iterations of other schemes for the calculation of the surface potential. Accordingly, the proposed analytical model for surface potential and the iterative scheme for the determination of the values of the surface potential are suitable for implementation in TFTs’ circuit simulators.

K. Ohmori and S. Amakawa, "Variable-Temperature Broadband Noise Characterization of MOSFETs for Cryogenic Electronics: From Room Temperature down to 3 K," 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, 

doi: 10.1109/EDTM55494.2023.10103124.

Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3 K and 300 K. Using the system, wideband noise spectroscopy (WBNS) from 20 kHz to 500 MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3 K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.

Jeong, Junhwa, Ilho Myeong, and Ickhyun Song. "Impact of MOSFET source/drain resistance on channel thermal noise calculation and noise performance." 

Results in Physics (2026): 108634.

Abstract: For sub-micron metal oxide semiconductor field effect transistors (MOSFETs), parasitic series source/drain resistance has a significant impact on channel thermal noise (Sid) and noise parameters. In this work, we propose an improved analytical channel thermal noise model considering parasitic resistance, based on physical thermal noise models of sub-micron intrinsic MOSFETs. To validate the proposed model, measurements were performed at room temperature (25°C) on nMOSFETs fabricated in a commercial 130-nm (0.13-µm) bulk RF CMOS technology. All RF S-parameter and noise measurements were conducted on-wafer at room temperature, with open/short de-embedding applied to accurately remove pads and interconnect parasitics. The model was calibrated by extracting parameters in a spice with the standard BSIM4 model as a baseline and validated against measured data such as Sid, Rn, NFmin, Gopt, and Bopt. Furthermore, the proposed model is extended to a circuit-level analysis by deriving the noise figure of a high-frequency amplifier (HFA) using Cadence Virtuoso (Spectre). A good agreement between the measurement and the developed model is observed, particularly under high gate bias (Vgs) conditions where the potential drop at the parasitic resistance becomes apparent. The analysis demonstrates that accurate modeling of parasitic resistance is essential for predicting the accurate noise figure of the HFA in high-current regimes. The improved model predicts the thermal noise of both the extrinsic MOS device and the HFA circuit well, thereby supporting accurate noise simulations for high-frequency circuits that operate under a wide range of gate bias conditions.

Fig. (a) 3D image of LDD MOSFET (b) equivalent circuits of (a) where

Rlds + Rss = RS and Rldd + Rdd = RD (c) equivalent circuit of intrinsic MOSFET.

[chapter] Compact/SPICE Modeling

Wladek Grabinski and Daniel Tomaszewski

Compact/SPICE Modeling

In: Rudan, M., Brunetti, R., Reggiani, S. (eds) 

Springer Handbook of Semiconductor Devices

DOI 10.1007/978-3-030-79827-7_34

Abstract: The microelectronics and nano-electronics industry strongly relies on compact models to reduce a new microelectronic product development costs. The goals of this review are to highlight critical issues for the development of compact models for microelectronics and nano-electronics. In this chapter, we’ve covered the main principles of the compact device modeling. Also discussed are the possibilities of integrating compact models into circuit simulation and design tools, with an emphasis on the Verilog-A standardization, which simplify model implementation into EDA tool.

 

[paper] Characterization and Modeling of SOI LBJTs at 4K

Yuanke Zhang, Yuefeng Chen, Yifang Zhang, Jun Xu, Chao Luo, and Guoping Guo

Characterization and Modeling of Silicon-on-Insulator 

Lateral Bipolar Junction Transistors at Liquid Helium Temperature

IEEE TED Vol. XX, No. XX, preprint arXiv:2309.09257 (2023).

University of Science and Technology of China (USTC), Hefei 230026, Anhui, China

CAS Key Lab ofQuantum Information, Hefei 230026, Anhui, China.

Abstract: Conventional silicon bipolars are not suitable for low-temperature operation due to the deterioration of current gain (β). In this paper, we characterize lateral bipolar junction transistors (LBJTs) fabricated on silicon-on insulator (SOI) wafers down to liquid helium temperature (4 K). The positive SOI substrate bias could greatly increase the collector current and have a negligible effect on the base current, which significantly alleviates β degradation at low temperatures. We present a physical-based compact LBJT model for 4 K simulation, in which the collector current (IC) consists of the tunneling current and the additional current component near the buried oxide (BOX)/silicon interface caused by the substrate modulation effect. This model is able to fit the Gummel characteristics of LBJTs very well and has promising applications in amplifier circuits simulation for silicon-based qubits signals.

Fig: IC (solid lines) and IB (dash lines) versus VBE of LBJT at different temperatures 

under (a) VBOX = 0 V; (b) VBOX = 12 V, VCE = 1 V.

Acknowledgement: The device fabrication was done by Prof. Zhen Zhang’s group in the Angstrom Microstructure Laboratory (MSL) at Uppsala University. Dr. Qitao Hu, Dr. Si Chen, Prof. Zhen Zhang are acknowledged for the device design and fabrication, and the technical staff of MSL are acknowledged for their process support.

[11k online viewers] 7th Sino MOS-AK/Nanjing

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

7th Sino MOS-AK Workshop in Nanjing (CN)

August 11-13, 2023 (online/onsite)

Recent, consecutive, 7th Sino MOS-AK/Nanjing Workshop discussing the Compact/SPICE modeling and its Verilog-A Standardization reached 11k online viewers. The MOS-AK participants and online attendees have followed one day SiC-related device modeling training on August 11 featured presentations by experts currently working at Robert Bosch GmbH and then two days workshop with 24 R&D Compact/SPICE modeling presentations:

[book] Negative Capacitance Field Effect Transistors

Negative Capacitance Field Effect Transistors

Physics, Design, Modeling and Applications

Edited By Young Suh Song, Shubham Tayal, Shiromani Balmukund Rahi, Abhishek Kumar Upadhyay

Pages 63 Color & 7 B/W Illustrations

ISBN 9781032445311 176 Sept. 29, 2023 by CRC Press

Description

This book aims to provide information in the ever-growing field of low-power electronic devices and their applications in portable device, wireless communication, sensor, and circuit domains. Negative Capacitance Field Effect Transistor: Physics, Design, Modeling and Applications, discusses low-power semiconductor technology and addresses state-of-art techniques such as negative-capacitance field-effect transistors and tunnel field-effect transistors. The book is broken up into four parts. Part one discusses foundations of low-power electronics including the challenges and demands and concepts like subthreshold swing. Part two discusses the basic operations of negative-capacitance field-effect transistor (NC-FET) and Tunnel Field-effect Transistor (TFET). Part three covers industrial applications including cryogenics and biosensors with NC-FET. This book is designed to be one-stop guidebook for students and academic researchers, to understand recent trends in the IT industry and semiconductor industry. It will also be of interest to researchers in the field of nanodevices like NC-FET, FinFET, Tunnel FET, and device-circuit codesign.

Table of Contents

Chapter 1 Recent Challenges in IT and Semiconductor Industry: From Von Neumann Architecture to the Future

Young Suh Song, Shiromani Balmukund Rahi, Navjeet Bagga, Sunil Rathore, Rajeewa Kumar Jaisawal, P. Vimala, Neha Paras, K. Srinivasa Rao

Chapter 2 Technical Demands of Low-Power Electronics

Soha Maqbool Bhat, Pooran Singh, Ramakant Yadav, Shiromani Balmukund Rahi, Billel Smaani, Abhishek Kumar Upadhyay, Young Suh Song

Chapter 3 Negative capacitance Field Effect Transistors: Concept and Technology

Ball Mukund Mani Tripathi

Chapter 4 Basic Operation Principle of Negative Capacitance Field Effect Transistor

Malvika, Bijit Choudhuri, Kavicharan Mummaneni

Chapter 5 Basic Operational Principle of Anti-ferroelectric Materials and Ferroelectric Materials

Umesh Chandra Bind, Shiromani Balmukund Rahi

Chapter 6 Basic Operation Principle of Optimized NCFET: Amplification Perspective

S. Yadav, P.N Kondekar, B. Awadhiya

Chapter 7 Spin Based Magnetic Devices With Spintronics

Asif Rasool, Shahnaz kossar, R.Amiruddin

Chapter 8 Mathematical Approach for Future Semiconductor Roadmap

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

Chapter 9 Mathematical Approach for Foundation of Negative Capacitance Technology

Shiromani Balmukund Rahi,Abhishek Kumar Upadhyay, Young Suh Song, Nidhi Sahni, Ramakant Yadav, Umesh Chandra Bind,Guenifi Naima,Billel Smaani,Chandan Kumar Pandey,Samir Labiod, T.S. Arun Samul,Hanumanl Lal, H. Bijo Josheph

[book] Circuit Simulation and Modeling with Phyton

Circuit Simulation and Modeling with Phyton

Hardcover – April 9, 2021

by Kenji Mori (author), Akira Matsuzawa (author)

This book is written for people who are learning Python. Circuit simulation and modeling are selected as subjects for programming using Python. The process of building a net" is attached to Chapter 5 appendix "Diode/MOSFET Coding Flow Diagram". Text Python source code suitable for learning by students and companies / corporations can be downloaded from the web.

About the Authors

Akira Matsuzawa: Professor Emeritus, Tokyo Institute of Technology President of Tech Idea Co., Ltd. 1978; Completed master's course at Graduate School of Engineering, Tohoku University. Joined Matsushita Electric Industrial (now Panasonic) in the same year 1997; Completed doctoral program at Graduate School of Engineering, Tohoku University 2003; Professor, Graduate School of Science and Engineering, Tokyo Institute of Technology 2018 Retired from Tokyo Institute of Technology Professor Emeritus at the same university

His books:
"First analog electronic circuit basic circuit edition" Kodansha (2015)
"First Analog Electronic Circuit Practical Circuit Edition" Kodansha (2016)
"Analog RFCMOS Integrated Circuits Basic Edition" Baifukan (2010)
"Analog RFCMOS Integrated Circuits Application Edition" Baifukan (2011)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

Kenji Mori: Part-time Lecturer, Tokyo Institute of Technology March 1979. Graduated from Tokushima University Graduate School of Electrical Engineering, joined NEC Corporation in the same year, engaged in circuit simulator development, automatic filter design program development, and circuit check program development. Joined Nippon Steel Corporation in November 1990, engaged in parameter extraction of MOSFET models. April 2009 Developed a prototype program for automatic design of mixed-signal LSI with Mr. Sugawara, an industry-academia-government collaboration researcher at Tokyo Institute of Technology. April 2014 Part-time Lecturer, Tokyo Institute of Technology

His books:
"Circuit Simulation Technology and MOSFET Modeling" Realize Riko Center (2003)
"Learning Circuit Simulation and Modeling with MATLAB" Torikagesha (2020)

[Program] MINI-COLLOQUIUM ON CAD/EDA MODELING

MINI-COLLOQUIUM ON CAD/EDA MODELING

Sala de Graus, Campus ETSE/ETSEQ

Department of Electronic, Electrical and Automatic Control Engineering, 

University Rovira i Virgili Tarragona, Catalonia, Spain

Chairperson: 

Benjamin Iñiguez, EDS BoG Member and Chair of the ED Spain Chapter

Tuesday, June 28 2022

8:20-8:30 Overview, B. Iñiguez
8:30-9:30 “Characterization and TCAD modeling based design assessment of ultra-high voltage SiC devices,” Muhammad Nawaz (Hitachi Energy, Sweden)
9:30-10:30 “Nanoscale InGaAs FinFETs: Band-to-Band Tunneling and Ballistic Transport,” Jesús del Alamo (MIT, USA)

10:30-11:00 Coffee break

11:00-12:00 “Physics-Based Parameter Extraction for Thin Film Transistors,” Arokia Nathan (Darwin College, University of Cambridge, UK)
12:00-13:00; “Characterization and modeling of organic solar cells,” Lluís F. Marsal (University Rovira I Virgili, Tarragona, Spain)

13:00-15:00 Lunch

15:00-19:00 Meeting of the EDS SRC Region 8 Executive Committee

Wednesday, June 29 2022

11:00-12:00 “Trends and challenges in Nanoelectronics for the next decade,” Elena Gnani (University of Bologna, Italy)
12:00-13:00,“SPICE and Verilog-A Modelling Using FOSS TCAD/EDA Tools: Technology - Devices – Applications” (virtual), Wladek Grabinski (GMC, Switzerland)

13:00-14:20 Lunch

Joint Session 

• MQ on CAD Modeling
• Graduate Student Meeting on Electronic Engineering

14:20-14:30 Overview, B. Iñiguez and J. Ferré-Borrull
14:30-15:30 “Compact modeling of memristive devices for neuromorphic computing,” (virtual) Enrique Miranda (Autonomous University of Barcelona, Spain)
15:30-16:30 Physical Principles to Formulate Thin Film Transistor Models for Circuit Design (virtual), Samar Saha (Prospicient Devices, USA)

16:30-16:35 Closing remarks, B. Iñiguez

[paper] p-Type Doped Silicene-based

Mu Wen Chuan, Munawar Agus Riyadi, Afiq Hamzah, Nurul Ezaila Alias, Suhana Mohamed Sultan, Cheng Siong Lim, Michael Loong Peng Tan

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model

PLoS ONE 17(3): e0264483.: March 3, 2022

DOI: 10.1371/journal.pone.0264483

   
Universiti Teknologi Malaysia, Skudai, Johor, Malaysia
Diponegoro University, Semarang, Indonesia

Abstract: Moore’s Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Fig: Schematic diagrams of AlSi3 FET: (a) the structure and 

(b) the ToB nanotransistor circuit model. 

Acknowledgements: 1.) Michael Tan Loong Peng - Ministry of Higher Education (MOHE) of Malaysia through the Fundamental Research Grant Scheme(FRGS/1/2021/ STG07/ UTM/02/3); The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript. 2.) Munawar Agus Riyadi - World Class Research Universitas Diponegoro (WCRU) 2021 Grant no. 118-16/UN7.6.1/PP/2021; The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

[book] Nano Interconnects: Device Physics, Modeling and Simulation

Afreen Khursheed and Kavita Khare

Nano Interconnects: Device Physics, Modeling and Simulation

CRC Press; 1st edition (2021)

ISBN: ‎ 978-0367610487

This textbook comprehensively covers on-chip interconnect dimension and application of carbon nanomaterials for modeling VLSI interconnect and buffer circuits. It provides analysis of ultra-low power high speed nano-interconnects based on different facets such as material modeling, circuit modeling and the adoption of repeater insertion strategies and measurement techniques. It covers important topics including on-chip interconnects, interconnect modeling, electrical impedance modeling of on-chip interconnects, modeling of repeater buffer and variability analysis. Pedagogical features including solved problems and unsolved exercises are interspersed throughout the text for better understanding. Aimed at senior undergraduate and graduate students in the field of electrical engineering, electronics and communications engineering for courses on Advanced VLSI Interconnects, Advanced VLSI Design, VLSI Interconnects, VLSI Design Automation and Techniques, this book:

• Provides comprehensive coverage of fundamental concepts related to nanotube transistors and interconnects.
• Discusses properties and performance of practical nanotube devices and related applications.
• Covers physical and electrical phenomena of carbon nanotubes, as well as applications enabled by this nanotechnology.
• Discusses the structure, properties, and characteristics of graphene-based on-chip interconnect.
• Examines interconnect power and interconnect delay issues arising due to downscaling of device size.

[paper] ACM Model for CMOS Analog Circuits Hand Design

Ademirde Jesus Costa^ab, Eliyas Mehdipour^b, Edson PintoSantana^b,

and Ana Isabela Araújo Cunha^b

Application of Improved ACM Model to the Design by Hand of CMOS Analog Circuits

Microelectronics Journal

Available online 16 November 2021, 105309

DOI: 10.1016/j.mejo.2021.105309

   
a Instituto Federal da Bahia, Santo Amaro, Brazil
b DEEC, Escola Politécnica, Universidade Federal da Bahia, Salvador, Brazil

Abstract: This work aims to provide solutions and perspectives for CMOS analog designers by reducing the time spent in iteratively dimensioning the devices and simulating the circuits. For this purpose, by-hand design methodologies for a few analog cells are proposed employing a MOSFET compact model which has been earlier improved by adding sub-models for some second order effects. A semiempirical sub-model and characterization method is presented for the Early voltage, thus enhancing the set of model equations for hand calculations. The accomplishment of several by-hand design examples and the comparison between simulation results and specifications succeeded in demonstrating the usefulness and advantages of using the improved MOSFET compact model in the proposed methodologies.

Fig: gm/Id Plot

Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model

Francisco J. García-Sánchez, Life Senior Member, IEEE,

and Adelmo Ortiz-Conde, Senior Member, IEEE

IEEE TED Aug 9. 2021

DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela

Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.

Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of V_GB versus ID_sat (lines) comes from denormalization and the explicit ID_sat versus V_GB (symbols) comes from denormalization of the proposed explicit expressions

[special issue] on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems

Guest editorial for the special issue 

on Modeling of μmWave and mmWave Electronic Devices for Wireless Systems: 

Connecting technologies to applications

Valeria Vadalà, Giovanni Crupi

First published: 27 July 2021; DOI: 10.1002/jnm.2940

The μmWave and mmWave frequencies have been historically associated with niche applications such as space and defense; however, in the last years wireless communications have caused a rapid growth of interest in mass-market applications, representing the enabling technology for the new Information Age where all “things” need to be connected. Internet of Things, Industry 4.0, and Smart Cities are portraits of this concept in different contexts, from entertainment to healthcare applications. This exciting scenario triggers the continuous increase of performance requirements such as huge bandwidth, low latency, and very high data rate of emerging wireless technologies (i.e., 5G and 6G). This special issue takes a step forward in the different branches of knowledge related to μmWave and mmWave devices, circuits, and systems, oriented to wireless applications from the device level up to the application level. From the reader's point of view, the goal is to drive to a comprehensive overview on salient aspects of these topics and to provide interesting hints to overcome the upcoming technological challenges.

REFERENCES:
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[2] Tang X, Yang T, Jia Y, Xu Y. FW-EM-based approach for scalable small-signal modeling of GaN HEMT with consideration of temperature-dependent resistances. Int J Numer Model El. 2021; 34(5):e2882. DOI: 10.1002/jnm.2882
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[8] Wu M, Cai J, King J, Chen S, Su J, Cao W. Design of a multi-octave power amplifier using broadband load-pull X-parameters. Int J Numer Model El. 2021; 34(5):e2878. DOI: 10.1002/jnm.2878
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[11] Qas Elias BB, Soh PJ, Abdullah Al-Hadi A, Vandenbosch GAE. Design of a compact, wideband, and flexible rhombic antenna using CMA for WBAN/WLAN and 5G applications. Int J Numer Model El. 2020; 34(5):e2841. DOI: 10.1002/jnm.2841
[12] Zhang X, Cunjun R, Dai J, Ding Y, Ullah S, Kosar Fahad A. Design of a reconfigurable antenna based on graphene for terahertz communication. Int J Numer Model El. 2021; 34(5):e2911. DOI: 10.1002/jnm.2911
[13] Gatte MT, Soh PJ, Kadhim RA, Abd HJ, Ahmad RB. Modeling and performance evaluation of antennas coated using monolayer graphene in the millimeter and sub-millimeter wave bands. Int J Numer Model. 2021; 34(5):e2929. DOI: 10.1002/jnm.2929
[14] Xing C, Qi F, Liu Z, Wang Y, Guo S. Terahertz compressive imaging: understanding and improvement by a better strategy for data selection. Int J Numer Model El. 2021; 34(5):e2863. DOI: 10.1002/jnm.2863

[paper] NCFET CMOS Logic

Reinaldo Vega, Senior Member, IEEE, Takashi Ando*, Senior Member, IEEE,  

Timothy Philip, Member, IEEE

Junction Design and Complementary Capacitance Matching 

for NCFET CMOS Logic 

IEEE J-EDS 2021

DOI 10.1109/JEDS.2021.3095923

IBM Research, Albany, NY 12203

* IBM T.J. Watson Research Center, Yorktown Heights, NY 10598

Abstract: Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device Vt menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization (Pr) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ ferroelectric/ metal/ insulator/ semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over > 6 decades. In a CMOS circuit, due to CCM, low-Vt pairs provide steeper subthreshold swing (SS) than high-Vt pairs. Transient power/performance is also modeled, and it is shown that a DC optimal NCFET design, employing broad junctions, CCM, and a low-Vt NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Fig: Equivalent capacitance network and illustrative C-V curve showing NMOS and NC curves. CNC > CINV results in non-hysteretic switching, but low voltage gain in the off-state due to CNC >> COV. Setting CNC to CNC2, which is matched more closely to COV, results in very low SS, but also hysteretic switching as CNC2 < CINV. 

Acknowledgment: The authors would like to thank Paul Solomon and Prof. Sayeef Salahuddin for insightful discussions, as well as Synopsys for technical support.

[paper] Generalized Devices for SPICE Simulation of Soft Errors

Chiara Rossi, André Chatel and Jean-Michel Sallese*

Modeling Funneling Effect With Generalized Devices for SPICE Simulation of Soft Errors

in IEEE Transactions on Electron Devices,

doi: 10.1109/TED.2021.3076028 

* EPFL, 1015 Lausanne (CH)

Abstract: Recent advances in CMOS scaling have made circuits more and more sensitive to errors and dysfunction caused by ionizing radiation, even at ground level, requiring accurate modeling of such effects. Besides generation, transport, and collection of radiation-induced excess carriers, another phenomenon, called funneling, has to be modeled for an accurate prediction of soft errors. The funneling effect occurs when the radiation track crosses a space charge region and generates excess carriers with a density higher than the doping close to it. These carriers distort the electric field of the space charge region, deeply changing the transport mechanism, from diffusion in a field-free semiconductor to drift. The objective of this work is to include funneling as part of the generalized lumped devices model in order to obtain a complete tool for SPICE-compatible simulations of single-event effects (SEEs). The latter approach has been recently proposed to simulate radiation-induced charges in the silicon substrate and is based on the so-called generalized lumped devices that simulate charge generation, propagation, and collection using standard circuit simulators. The generalized devices are here extended to include funneling and used to simulate an alpha particle impinging on the bulk of nMOS and pMOS transistors. The results obtained are validated with TCAD numerical simulations. Finally, a static random-access memory (SRAM) struck by an alpha particle is analyzed. The model predicts that the occurrence of a soft error, i.e., flipping of memory state, may depend on whether or not there is funneling. This justifies the need for accurate modeling of funneling phenomena to predict SEEs in ICs.

FIG: Generalized devices network obtained for the pMOS substrate. The mesh is drawn in gray dashed lines. The network is not shown around the radiation track; only the mesh is reported, which is denser to linearize the generation profile and excess carrier gradients.

Aknowlwdgement: This work was supported by the Swiss National Science Foundation (NSF) under Grant 200021_165773.

[papers] Compact Modeling

[1] Zhang, Yuanke, Tengteng Lu, Wenjie Wang, Yujing Zhang, Jun Xu, Chao Luo, and Guoping Guo. "Characterization and Modeling of Native MOSFETs Down to 4.2 K." arXiv:2104.03094 (2021).

Abstract: The extremely low threshold voltage (VTH) of native MOSFETs (VTH≈0 V @ 300 K) is conducive to the design of cryogenic circuits. Previous research on cryogenic MOSFETs mainly focused on the standard threshold voltage (SVT) and low threshold voltage (LVT) MOSFETs. In this paper, we characterize native MOSFETs within the temperature range from 300 K to 4.2 K. The cryogenic VTH increases up to ∼0.25 V (W/L = 10 µm/10 µm) and the improved subthreshold swing (SS) ≈ 14.30 mV/dec @ 4.2 K. The off-state current (IOFF) and the gate-induced drain leakage (GIDL) effect are ameliorated greatly. The step-up effect caused by the substrate charge and the transconductance peak effect caused by the energy quantization in different subbands are also discussed. Based on the EKV model, we modified the mobility calculation equations and proposed a compact model of large size native MOSFETs suitable for the range of 300 K to 4.2 K. The mobility-related parameters are extracted via a machine learning approach and the temperature dependences of the scattering mechanisms are analyzed. This work is beneficial to both the research on cryogenic MOSFETs modeling and the design of cryogenic CMOS circuits for quantum chips.

Fig: I-V curves of native MOSFETs with W/L= 10/10µm measured (symbol) and calculated (solid line) at various temperatures. (a) Acomparison of the calculation results between this model and the  EKV2.6 model at 77K and 4.2K. (b) Measurement and calculation results of  the output characteristic at 4.2 K.

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[2] Qixu Xie  Guoyong Shi; An analytical gm/ID‐based harmonic distortion prediction method for multistage operational amplifiers; Int J Circ Theor Appl. 2021; 1– 27. DOI: 10.1002/cta.3012

Abstract: An analytical stage‐based harmonic distortion (HD) analysis method for multistage operational amplifiers (Op Amps) is developed in this work. This work contributes two fundamental methods that make the analytical HD prediction possible at the circuit level. Firstly, we propose that the traditionally used first order small‐signal transistor quantities gm (transconductance) and go (output conductance) in the gm/ID design methodology for bulk complementary metal‐oxide‐semiconductor (CMOS) technology can be extended to the higher order quantities gm(k) and go(k) (k=1,2,3). With proper normalization, these quantities become neutral to the device dimensions and operation currents, hence can be precharacterized by sweeping simulations and used as lookup tables. Secondly, we further develop analytical nonlinearity expressions for a set of commonly used amplifier stages, represented as the functions of the nonlinearity parameters gm(k) and go(k) of the transistors that form a stage circuit. A combination of these two fundamental methods on hierarchical nonlinearity modeling enables us to apply the existing analytical HD estimation methods for the stage‐form macromodels to predict the circuit‐level HD behavior, overcoming the need of running repeated simulations under device resizing and rebiasing. The proposed harmonic distortion analysis method has been validated by application to real multistage amplifiers, achieving HD prediction results in excellent agreement to fully transistor‐level circuit simulation results but with substantial speedup.

[C4P] DevIC 2021

DevIC 2021: Call for Papers

IEEE KGEC Student Branch Chapter in association with Department of ECE, KGEC, technically co-sponsored by IEEE EDS Kolkata Chapter  organizes International conference 4th Int. Conference DevIC 2021 “Devices for Integrated Circuit (DevIC)”.  There will be keynote lectures/talks, tutorials, and oral presentations  by eminent researchers. The conference organizers invite original papers in the research areas of various aspects of semiconductor technology and circuits that creates an opportunity to symbiosis on topic ranging from process technology to system-on-chip. Articles announcing significant and original results are highly requested. Papers are solicited across the general field of electronic devices. Topics of interest include, but are not limited to;

• CMOS Processes, Devices and Integration;
• VLSI Technology and Circuits;
• Innovative Systems;
• Emerging Non-CMOS Devices & Technologies;
• Device Modelling & Simulation; 
• Device Characterization, Reliability & Yield; 
• Devices with New material systems;
• Devices for Low power applications;
• Low dimensional devices;
• Low dimensional Semiconductors; 
• Design and Simulation of Circuits with nanoscale devices;
• MEMS, Sensors & Display Technologies;
• Advanced & Emerging Memories; 
• High frequency wireless communication;

DevIC 2021 Conference Committee

[papers] Compact/SPICE Modeling

[1] Wang, Jie; Chen, Zhanfei; You, Shuzhen; Bakeroot, Benoit; Liu, Jun; Decoutere, Stefaan; "Surface-Potential-Based Compact Modeling of p-GaN Gate HEMTs" Micromachines (2021) 12, no. 2: 199; https://doi.org/10.3390/mi12020199

Abstract: We propose a surface potential (SP)-based compact model of p-GaN gate high electron mobility transistors (HEMTs) which solves the Poisson equation. The model includes all possible charges in the GaN channel layer, including the unintended Mg doping density caused by out-diffusion. The SP equation and its analytical approximate solution provide a high degree of accuracy for the SP calculation, from which the closed-form I–V equations are derived. The proposed model uses physical parameters only and is implemented in Verilog-A code.

Fig: The equivalent circuit of the capacitance of field plates (FPs) of a p-GaN gate HEMT.

[2] Chen, H. and He, L.,  The spatial and energy distribution of oxide trap responsible for 1/f noise in 4H-SiC MOSFETs. Journal of Physics Communications, JPCO-101816.R1 (2021)

Abstract: Low-frequency noise is one of the important characteristics of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) that is susceptible to oxide traps. Drain-source voltage noise models of 4H-SiC MOSFETs under low–drain-voltage and inverse condition were proposed by considering the spatial and energy non-uniform distribution of the oxide trap, based on the McWhoter model for uniform trap distribution. This study performed noise experiments on commercial 4H-SiC MOSFETs, and revealed that the non-uniform spatial and non-uniform energy distribution caused new 1/f noise phenomenon, different from that under uniform spatial and energy distribution. By combining experimental data and theoretical models, the spatial and energy distribution of oxide traps of these samples were determined.

Fig: Adaptive circuit for 4H-SiC MOSFET noise measurement

in the frequency 1 Hz-10kHz ranged

[papers] Compact/SPICE Modeling

[1] Peled, A, Amrani, O, Rosenwaks, Y.; DC and transient models of the MSET device; Int J Numer Model. 2021;e2869. https://doi.org/10.1002/jnm.2869

Abstract: As a multigate device, the multiple‐state electrostatically formed nanowire transistor (MSET) exhibits a rather complex characteristic on account of the coupling between each of its two adjacent terminals. The MSET has shown promise across a steadily growing range of applications and integrated circuit components. However, an analytical model of the MSET has not been formulated. The objective of this work was to develop practical DC and transient models of the MSET. The modeling approach comprises two stages: the first stage consists of a bottom‐up derivation of the I–V characteristics from the fundamental physical level using the physical processes within the device to derive equations that describe its steady‐state behavior; the second stage proposes a set of analytical equations more applicable to simulation environments. A transient model that considers device parasitic capacitance is also established. The models are validated against robust model simulations in TCAD Sentaurus and Cadence Virtuoso.

[2] Ciou, Jhang-Yan, Sourav De, Wallace Lin, Yao-Jen Lee, and Darsen Lu. "Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control in Short-Channel FinFETs." arXiv e-prints (2020): arXiv-2007.

Abstract: This study simulated negative-capacitance double gate FinFETs with channel lengths ranging from 25nm to 100nm using TCAD. The results show that negative capacitance significantly reduces subthreshold swing as well as drain induced barrier lowering effects. The improvement is found to be significantly more prominent for short channel devices than long ones, which demonstrates the tremendous advantage of negative capacitance gate stack for scaled MOSFETs. A compact analytical formulation is developed to quantify sub-threshold swing improvement for short channel devices.

Fig: (a) Three-dimensional NC FinFET structure studied insimulation. (b) List of nominal device parameters used in TCAD simulation.

[3] Ahmed, Sheikh Z., Samiran Ganguly, Yuan Yuan, Jiyuan Zheng, Yaohua Tan, Joe C. Campbell, and Avik W. Ghosh. "A Physics Based Multiscale Compact Model of pin Avalanche Photodiodes." arXiv preprint arXiv:2102.04647 (2021).

Abstract: III-V material based digital alloy Avalanche Photodiodes (APDs) have recently been found to exhibit low noise similar to Silicon APDs. The III-V materials can be chosen to operate at any wavelength in the infrared spectrum. In this work, we present a physics-based SPICE compatible compact model for APDs built from parameters extracted from an Environment-Dependent Tight Binding (EDTB) model calibrated to ab-initio Density Functional Theory (DFT) and Monte Carlo (MC) methods. Using this approach, we can accurately capture the physical characteristics of these APDs in integrated photonics circuit simulations.

Fig: Schematic diagram of avalanche photodiode model and testbench used in the SPICE simulations.