[paper] Nanowire Biosensor Analytical Model

Ashkhen Yesayan, Aleksandr Grabski, Farzan Jazaeri, Jean-Michel Sallese

Design-Oriented Analytical Model for Nanowire Biosensors Including Dynamic Aspects

IEEE TED (2025) DOI 10.1109/TED.2025.3526113

Abstract: Nanowire Field Effect Transistor (NWFET) biosensors are known to be highly sensitivity devices that can detect extremely low concentrations of biomolecules. In this paper, we present an analytical model alongside with numerical simulations to calculate the sensitivity of NWFET biosensors. The model accounts for biosensing dynamics as well as diffusion of ions in the solution and across the functionalized layer. The signal-to-noise ratio is also estimated, which gives a lower limit in terms of sensitivity. The model is physics based and is validated against a commercial multiphysics simulations and experimental data. It predicts the bio-sensitivity down to femtomolar concentration of biomolecules without any fitting parameter.

FIG: Schematic structure of device (a), the charge distribution in theoretical model (b) 

and Si NWFET sensitivity simulated with presented model (c)

Acknowledgement: This work was supported by the Science Committee of RA, in the frames of the research project No:21T-2B321.

[paper] Compact Model of Linear Passive IPD

Zhang, Zijian

Compact Model of Linear Passive Integrated Photonics Device

for Photon Design Automation

arXiv preprint: 2501.06774 (2025)

1 University of Electronic Science and Technology of China, Chengdu, 611731, China

Abstract: As integrated photonic systems grow in scale and complexity, Photonic Design Automation (PDA) tools and Process Design Kits (PDKs) have become increasingly important for layout and simulation. However, fixed PDKs often fail to meet the rising demand for customization, compelling designers to spend significant time on geometry optimization using FDTD, EME, and BPM simulations. To address this challenge, we propose a data-driven Eigenmode Propagation Method (DEPM) based on the unitary evolution of optical waveguides, along with a compact model derived from intrinsic waveguide Hamiltonians. The relevant parameters are extracted via complex coupled-mode theory. Once constructed, the compact model enables millisecond-scale simulations that achieve accuracy on par with 3D-FDTD, within the model’s valid scope. Moreover, this method can swiftly evaluate the effects of manufacturing variations on device and system performance, including both random phase errors and polarization-sensitive components. The data-driven EPM thus provides an efficient and flexible solution for future photonic design automation, promising further advancements in integrated photonic technologies.

Fig: Photon design automation workflow based on compact model

of linear passive optical waveguide

Supplementary information:

The time evaluations were conducted on a system equipped with an Intel i9-10850K processor, 64 GB DDR4 memory, and NVIDIA Quadro RTX 5000 professional graphics processor.

[paper] Compact Model of IDG BEOL Transistor for Capacitorless Memory

Lihua Xu, Kaifei Chen, Zhi Li, Yue Zhao, Lingfei Wang and Ling LiPhysics-Based 

Compact Model of Independent Dual-Gate BEOL-Transistors

for Reliable Capacitorless Memory

in IEEE Journal of the Electron Devices Society

DOI: 10.1109/JEDS.2024.3393418  

School of Microelectronics, University of Science and Technology of China, Hefei (CN)
State Key Lab of FTIC, Institute of Microelectronics of Chinese Academy of Sciences, Beijing (CN)
University of Chinese Academy of Sciences, Beijing (CN)

Abstract: Capacitorless DRAM architectures based on Back End-of-Line (BEOL)-transistors are promising for long retention, high-density and low-power 3D DRAM solutions due to its low leakage, operational flexibility, and monolithic integration capability. Different from classical silicon-based devices, in-depth studies on the performances of nanoscale multi gate transistors (e.g., a-InGaZnO-FET) are still barely conducted for physical description, due to the complicated multi-gating principle, finite-size effects on transport, increased variation sources and enlarged parasitic effect. Hence, high-performance multi-nanoscale (down to ~ 50 nm) dual-gate a-IGZO transistors are fabricated, and a physical compact model is developed based on the surface potential for dual-gated coupling and the disordered transport with finite-size-correction. The short channel behaviors on sub-threshold swing, mobility and threshold voltage are investigated, and contact effects are validated by the transfer-line method (TLM). Regarding the specific challenge of dual-gate alignment, possible misalignment and parasitic effects on multi-device fluctuations are important of large-scale circuit design and analyzed by TCAD simulations. Besides, the bias-temperature instability (BTI) has been comprehensively investigated. In awareness of the above effects, this model bridges fabrication-based material properties and structural parameters, assisting in a threshold fluctuation resistant operation scheme for capacitorless multi-bit memory, showing a great potential in future monolithic integration circuit design using BEOL-transistor.

Fig: (a) Schematic illustration of the IDG a-IGZO FETs with a thickness of ~5nm. (b) Agreement between analytical and numerical results of back gate surface potentials at different VDS with errors in the inset. VTG & VBG denotes DG synchronized-sweep with the same voltage.

Acknowledgements: This work was supported in part by National key research and development program (Grant Nos. 2021YFB3600704), the National Natural Science Foundation of China (Grant Nos. 62274178, 92264204), CAS Interdisciplinary Innovation Team [JCTD-2022-07].

[paper] Symmetric BSIM-SOI

Chetan Kumar Dabhi, Dinesh Rajasekharan, Girish Pahwa, Debashish Nandi, Naveen Karumuri, Sreenidhi Turuvekere, Anupam Dutta, Balaji Swaminathan, Srikanth Srihari, Yogesh S. Chauhan, Sayeef Salahuddin, and Chenming Hu

Symmetric BSIM-SOI: A Compact Model for Dynamically Depleted SOI MOSFETs 

 in IEEE TED (2024)

Part I DOI: 10.1109/TED.2024.3363110

Part II DOI: 10.1109/TED.2024.3363117

1 Department of Electrical Engineering and Computer Sciences, UCB, CA, USA

2 Department of Electrical Engineering, IIT Kanpur, India

3 GlobalFoundries, Bengaluru, India

Abstract: In this article, we present a symmetric surface-potential-based model for dynamic depletion (DD) device operation of silicon-on-insulator (SOI) FETs for RF and analog IC design applications. The model accurately captures the device behavior in partial depletion (PD) and full depletion (FD) modes, as well as in the transition from PD to FD, based on device geometry, doping, and bias conditions. The model also exhibits an excellent source–drain symmetry during dc and small-signal simulations, resulting in error-free higher order harmonics. The model is fully scalable with bias, temperature, and geometry and has been validated extensively with real device data from the industry. The symmetric BSIM-SOI model is developed in Verilog-A and compatible with all commercial SPICE simulators.

FIG: (a) Schematic of a typical SOI MOSFET

(b) Cgg versus Vgb for different substrate bias, with the PD-to-FD transition 

Acknowledgment: The authors thanks the members of the Compact Model Coalition (CMC), particularly Geoffrey J. Coram and Jushan Xie, for testing the model and suggesting improvements. The authors appreciate the CMC QA team’s efforts in conducting a model quality check. Caixia Han and Xiao Sun from Cadence provided a few useful test cases. They thank Ananth Sundaram and Anamika Singh Pratiyush from GlobalFoundries India for the help and discussion regarding DDSOI model intricacies and development. Model code is available at BSIM Website <https://bsim.berkeley.edu/models/bsimsoi/>

[paper] Compact Model of Graphene FETs

Nikolaos Mavredakis, Anibal Pacheco-Sanchez, Oihana Txoperena,

Elias Torres, and David Jiménez

A Scalable Compact Model for the Static Drain Current of Graphene FETs

IEEE TED, Vol. 71, No. 1, January 2024

DOI:  10.1109/TED.2023.3330713

1 Departament d’Enginyeria Electrònica, Escola d’Enginyeria, UAB, 08193 Bellaterra, Spain
2 Graphenea Semiconductor SLU, 20009 San Sebastián, Spain.

Abstract: The main target of this article is to propose for the first time a physics-based continuous and symmetric compact model that accurately captures I–V experimental dependencies induced by geometrical scaling effects for graphene field-effect transistor (GFET) technologies. Such a scalable model is an indispensable ingredient for the boost of large-scale GFET applications, as it has been already proved in solid industry-based CMOS technologies. Dependencies of the physical model parameters on channel dimensions are thoroughly investigated, and semi-empirical expressions are derived, which precisely characterize such behaviors for an industry-based GFET technology, as well as for others developed in the research laboratory. This work aims at the establishment of the first industry standard GFET compact model that can be integrated in circuit simulation tools and, hence, can contribute to the update of GFET technology from the research level to massive industry production.

Fig: Graphenea GFET schematic cross-section not drawn to scale. Graphene under metal contacts is not shown.The drain current has explicit derivation in respect to Qgr, where Qt and Qp(n) are the transport sheet and p(n)-type charges, respectively; Vc is the chemical potential, h is the reduced Planck constant, uf is the Fermi velocity, e is the electron charge, and k is a coefficient. Qt and, thus, ID can be calculated according to Vc polarity at source (Vcs) and drain (Vcd), respectively. Hence, at n-type region where Vcs, Vcd > 0 and Qp = 0

Acknowledgements: This work was supported in part by the European Union’s Horizon 2020 Research and Innovation Program GrapheneCore3 under Grant 881603; in part by the Ministerio de Ciencia, Innovación y Universidades under Grant RTI2018-097876-B-C21 (MCIU/AEI/ FEDER, UE), Grant FJC2020-046213-I, and Grant PID2021-127840NBI00 (MCIN/AEI/FEDER, UE); in part by the European Union Regional Development Fund within the Framework of the ERDF Operational Program of Catalonia 2014–2020 with the Support of the Department de Recerca i Universitat, with a grant of 50% of Total Cost Eligible; and in part by the GraphCAT Project under Grant 001-P-001702. 

[paper] Lorentzian noise spectra in compact models

Nikolaos Makris*†, Loukas Chevas* and Matthias Bucher*

Verilog-A based implementation of Lorentzian noise spectra in compact models

26th International Conference on Noise and Fluctuations - ICNF

17th-20th October 2023 - Grenoble - France

DOI: 10.1109/ICNF57520.2023.10472771

* School of Electrical & Computer Engineering, Technical University of Crete (TUC), GR-73100 Chania, Greece        European University on Responsible Consumption and Production (EURECA-PRO) (Joint affiliation)
† Institute of Electronic Structure and Laser, Foundation for Research and Technology-Hellas (IESL-FORTH), GR-71110 Heraklion, Greece

Abstract:In this paper, a simple Verilog-A implementation of Lorentzian noise spectra is introduced that can be used in compact models for the frequency-domain simulation of low-frequency noise in electronic devices. For this purpose, a thermal noise source is combined with a low-pass filter as realized using laplace_nd Verilog-A function in order to achieve Lorentzian noise behavior. This modeling approach can be implemented in any Verilog-A compact model and provides the means for bias-dependent Lorentzian trap modeling. This approach is evaluated in commercial simulator. Application examples are provided to demonstrate the capabilities of this approach.

FIG: Bias dependent model implemented in the EKV3 MOSFET model

Acknowledgements: This work was co-funded by the ERASMUS+ Programme of the European Union (Contract number: 101004049 - EURECA-PRO - EAC-A02-2019 / EAC-A02-2019-1). This research has been co-financed by the European Regional Development Fund of the European Union and Greek national funds through the Operational Program Competitiveness, Entrepreneurship and Innovation, under the call RESEARCH - CREATE - INNOVATE (project code: T2EDK-00340).

[paper] Fast and Expandable ANN-Based Extraction

Jeong, HyunJoon, SangMin Woo, JinYoung Choi, HyungMin Cho, Yohan Kim,

Jeong-Taek Kong, and SoYoung Kim

Fast and Expandable ANN-Based Compact Model and Parameter Extraction for Emerging Transistors IEEE Journal of the Electron Devices Society (2023)

DOI 10.1109/JEDS.2023.3246477

Abstract: In this paper, we present a fast and expandable artificial neural network (ANN)-based compact model and parameter extraction flow to replace the existing complicated compact model implementation and model parameter extraction (MPE) method. In addition to nanosheet FETs (NSFETs), our published ANN based compact modeling framework is easily extended to negative capacitance NSFETs (NC-NSFETs), which are attracting attention as next-generation devices. Each device is designed using a technology computer-aided design (TCAD) simulator. Using device structure parameters, temperature, and channel doping depth as input variables, we construct a dataset of electrical properties used for machine learning (ML)-based modeling. The accuracy of predicting device electrical characteristics with the proposed ANN-based compact model is less than a 1% error compared to TCAD, and simulation results of digital and analog circuits using the proposed compact model show less than a 3% error. This allows the ANN-based modeling framework to achieve accurate DC, AC, and transient simulations without restrictions on device technology. In particular, temperature and process variables such as channel doping depth, which are not defined in the compact model parameters, are easily added to the previously presented five key parameters. Instead of conventional complex compact modeling and MPE work, we propose a method to create fast, accurate, flexible, and expandable ML-based Verilog-A SPICE models with design technology co-optimization (DTCO) capabilities.

Fig A: Conventional model parameter extraction flow

Fig B: The proposed ANN-based model parameter extraction flow

Acknowledgments: We thank the reviewers for improving the contents of the paper. This work was supported by an Institute of Information & communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No.2021-0- 00754, Software Systems for AI Semiconductor Design) and by a National Research Foundation of Korea grant funded by the Korean government (MISP) (NRF-2020R1A2C1011831). The EDA tool was supported by the IC Design Education Center (IDEC), Korea

[paper] Circuit-Based Compact Model of Electron Spin Qubit

Mattia Borgarino

Circuit-Based Compact Model of Electron Spin Qubit

Special Issue Recent Advances in Silicon-Based RFIC Design;

Electronics 2022, 11(4), 526; 

DOI: 10.3390/electronics11040526

   
University of Modena and Reggio Emilia, Modena (IT)

Abstract: Today, an electron spin qubit on silicon appears to be a very promising physical platform for the fabrication of future quantum microprocessors. Thousands of these qubits should be packed together into one single silicon die in order to break the quantum supremacy barrier. Microelectronics engineers are currently leveraging on the current CMOS technology to design the manipulation and read-out electronics as cryogenic integrated circuits. Several of these circuits are RFICs, as VCO, LNA, and mixers. Therefore, the availability of a qubit CAD model plays a central role in the proper design of these cryogenic RFICs. The present paper reports on a circuit-based compact model of an electron spin qubit for CAD applications. The proposed model is described and tested, and the limitations faced are highlighted and discussed.

FIG: Compact model of the electron spin qubit.

Funding: This research received no external funding.

[paper] Multi-Segment TFT Compact Model for THz Applications

Xueqing Liu¹,Trond Ytterdal² and Michael Shur^1,3

Multi-Segment TFT Compact Model for THz Applications

Nanomaterials 2022, 12(5), 765; 

DOI: 10.3390/nano12050765

  
1 RPI, Troy, NY 12180, USA
2 Norwegian University of Science and Technology, Trondheim, Norway
3 Electronics of the Future, Inc., USA

Abstract: We present an update of the Rensselaer Polytechnic Institute (RPI) thin-film transistor (TFT) compact model. The updated model implemented in Simulation Program with Integrated Circuit Emphasis (SPICE) accounts for the gate voltage-dependent channel layer thickness, enables the accurate description of the direct current (DC) characteristics, and uses channel segmentation to allow for terahertz (THz) frequency simulations. The model introduces two subthreshold ideality factors to describe the control of the gate voltage on the channel layer and its effect on the drain-to-source current and the channel capacitance. The calculated field distribution in the channel is used to evaluate the channel segment parameters including the segment impedance, kinetic inductance, and gate-to-segment capacitances. Our approach reproduces the conventional RPI TFT model at low frequencies, fits the measured current–voltage characteristics with sufficient accuracy, and extends the RPI TFT model applications into the THz frequency range. Our calculations show that a single TFT or complementary TFTs could efficiently detect the sub-terahertz and terahertz radiation.

FIG: (a) quivalent circuit of the multi-segment SPICE model for TFT and
(b) equivalent circuit for each segment including leakage components

Acknowledgements: The work was supported by Office of Naval Research (N000141712976, Project Monitor Paul Maki).

[paper] Modeling of SIC VDMOS FET

Anirban Kar∗, Ahtisham Pampori∗, Noriyoshi Hashimoto† and Yogesh Singh Chauhan∗

A Charge-Based Silicon Carbide MOSFET Compact Model for Power Electronics Applications

2021 IEEE 8th Uttar Pradesh Section UPCON)

DOI: 10.1109/UPCON52273.2021.9667643

∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)

Abstract: This paper presents a charge-based compact model for Silicon Carbide (SiC) power MOSFETs, which captures the static characteristics of the device over a wide range of voltages and currents. The drift region resistance and charges in the channel have been formulated to calculate the drain current in a self-consistent manner. The proposed model has been validated against the measured transfer and output characteristics of a commercial 1.2kV power MOSFET (Infineon IMW120R045M1) with a maximum current rating of 52A.

Fig: a) Transfer characteristics of SiC MOSFET with Vd=1 to 20V

b) Transconductance of SiC MOSFET with Vd=1 to 20V 

Acknowledgement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA02/2017-18 and in part by the Department of Science and Technology through the FIST Scheme under Grant SR/FST/ETII-072/2016 and Keysight Technologies, USA. The measurement of the device was carried out at Keysight Technologies, Japan.

[paper] Automatic Parameter Extraction of MOSFET Compact Models

Gazmend Alia^1,2, Andi Buzo¹, Hannes Maier-Flaig¹, Klaus-Willi Pieper¹, 

Linus Maurer²  and Georg Pelz¹

Automatic Parameter Extraction of MOSFET Compact Models using Differential Evolution with Population Prediction (DEpred)

6th EDTM; March 6 to 9, 2022 

   
1 Infineon Technologies AG, Munich (D)
2 Bundeswehr University Munich (D)

Abstract: Parameter extraction of MOSFET compact models with hundreds of parameters is not a trivial task. Differential evolution (DE) has proven to be very effective in such highly dimensional parameter spaces. However, DE needs a large number of iterations to converge. This paper proposes a novel method to accelerate the convergence of DE by predicting tens of iterations ahead where the population will be, based on the knowledge from the already finished iterations. The method is validated with BSIM4 and HiSIM-HV compact models, where up to 50% of the iterations are saved.

Fig: DE vs DEpred cost function for BSIM4 and HiSIM-HV models.
DEpred reaches the target 50% faster.

[paper] Analytical Compact Model Of Cylindrical Junctionless Nanowire FETs

Adelcio M. de Souza, Daniel R. Celino, Regiane Ragi, Murilo A. Romero

Fully analytical compact model for the Q–V and C–V characteristics 

of cylindrical junctionless nanowire FETs

Microelectronics Journal (2021): 105324

DOI: 10.1016/j.mejo.2021.105324

   

University of Sao Paulo (EESC/USP), Sao Carlos (BR)

Abstract: This paper develops a new compact model for the Q–V and C–V characteristics of cylindrical junctionless nanowire FETs in which the nanowire radius is large enough, in such a way that quantum confinement effects can be neglected. Our model is fully analytical and valid for all bias regimes, i.e., subthreshold, partial depletion, and accumulation. The obtained Q-V and C–V characteristics, as well as their derivatives, are continuous across the full range of bias voltages. The model is fully physics-based, with no fitting parameters, and it is very intuitive, since it relies on the understanding of the device as a gated resistor. Model validation is performed against previous results in the literature, demonstrating very good agreement.

Fig.  Validation of our C–V model (solid lines) in comparison to numerical results, highlighting the effect of parasitic capacitance. The free-carrier capacitance component from new model is shown in dashed lines. Simulation parameters: tox = 4.5nm, Nd = 1.6E18 cm−3, L = 200nm, VFB = 1.09V and Vds = 0.05V.

Acknowledgments: The authors would like to thank the Brazilian funding agencies CAPES, CNPq, and Fapesp for their financial support: Conselho Nacional de Desenvolvimento Científico e Tecnologico. Grant Number: 303708/2017-4; Coordenaçao de Aperfeiçoamento de Pessoal de Nível Superior; Fundaçao de Amparo a Pesquisa do Estado de Sao Paulo. Grant Number: 18/13537-6.

[paper] Automated Compact Model Parameter Extraction

Marc Huppmann∗, Klaus-Willi Pieper†, Andi Buzo†, Linus Maurer∗ and Georg Pelz†

Utilizing Differential Evolution for an Automated Compact Model Parameter Extraction

In 2021 International Semiconductor Conference (CAS), pp. 231-234. IEEE, 2021.

   
∗ Universitat der Bundeswehr Munchen, Neubiberg, Germany
† Infineon Technologies AG, Neubiberg, Germany

Abstract: Parameter extraction is a challenging task, as it searches for a solution inside a high dimensional plus non- convex space. To be able to apply well known gradient based optimizers, the problem is dissected into multiple simpler yet intertwined tasks, which yields a complex and manual labour intensive procedure. On the contrary to gradient based methods, genetic algorithms perform excellent on global search problems, which eliminates the need for such a sophisticated workflow. In this paper, a highly automated methodology is presented that is capable of replacing the standard manual extraction sequence for the BSIM MOSFET compact model. Due to its superior extreme finding behaviour, the Differential Evolution algorithm is applied in combination with a special error metric to ensure a high fitting quality, in all regions of the output and transfer curves. Repeatably good results for 20k measurement points are obtained, with a reduction of factor 10 in total fitting duration, while coincidentally consuming mostly computation instead of manual labour time.

Fig: With every iteration, the errors approach each other till

they meet in roughly one point and σi terminates the fitting.

[paper] Verilog-A Compact MTJ Model

Etienne Becle, Philippe Talatchian, Guillaume Prenat, Lorena Anghel, Ioan-Lucian Prejbeanu 

Fast Behavioral VerilogA Compact Model for Stochastic MTJ  

51st European Solid-State Device Research Conference; Grenoble 2021

  

CEA-Spintec (F)

Abstract: Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator. 

Fig: Schematic representation of the implemented algorithm

Acknowledgement: This work is supported by the French National Research Agency in the framework of the "Investissements d’avenir” program (ANR-15-IDEX-02). 

[paper] Charge-based Modeling of FETs

Jean-Michel Sallese 

Charge-based modeling of field effect transistors, Make it easy

Joint International EUROSOI and EuroSOI-ULIS Workshop (Sept.2020)

DOI: 10.1109/EuroSOI-ULIS53016.2021.956068

 
EDLab, EPFL,  Lausanne  (CH)
 

Abstract: In this presentation, we revisit some charge voltage dependencies for different architectures of field effect transistor, emphasizing on compactness and simplicity while maintaining a close link with physics, which makes these models predictive and accurate for general purposes of compact modeling.

Fig: The gm/I invariant versus the inversion coefficient IC. 

The operation modes of the MOSFET are clearly defined. 

Acknowledgements: I (JMS) would like to thank F. Jazaeri, C. Lallement, W. Grabinski, B. Iniguez and M. Bucher for their constructive interactions. 

[paper] Compact model of 3D NAND

Kul Lee and Hyungcheol Shin

Distinguishing capture cross section parameter between 

in GIDL erase compact model and TCAD

Japanese Journal of Applied Physics. 2021 Oct 14.

 
ISRC and School of Electrical Engineering and Computer Science, Seoul National University, (KR)
 

Abstract: Compact model of 3D NAND enables simulation at circuit- or system- level. Although compact model for gate-induced-drain-leakage(GIDL)-assisted erase has been proposed in previous study, it is difficult to be used practically because it has not been properly validated. In particular, capture-cross-section (CCS) value that is far from the real value is used. Also, it doesn’t consider the latest device structure and its operation. In this paper, conventional GIDL-assisted erase compact model is validated using TCAD and improved more practically. It is confirmed that CCS should be distinguished in TCAD and compact model due to their different definition in each of them. Based on their physical differences, equation that can interconvert them is proposed and the model is successfully validated with proper CCS. Finally, the advanced GIDL-assisted erase compact model considering tapered angle, single-side injection and word-line voltage is suggested.

Fig: Schematic cross section of 3D NAND string considering tapered angle. Double stacking and singe-side GIDL injection are assumed. It is assumed that the upper and lower stacks have the same dimension parameters.

[paper] VNWFET Including Tied Compact Model

Arnaud Poittevin1, Chhandak Mukherjee2, Ian O’Connor1, Cristell Maneux2, Guilhem Larrieu3,4, Marina Deng2, Sebastien Le Beux1, Francois Marc2, Aurélie Lecestre3, Cedric Marchand1, 

and Abhishek Kumar3

3D Logic Cells Design and Results Based on Vertical NWFET Technology 

Including Tied Compact Model

In: Calimera A. (eds) VLSI-SoC: Design Trends. VLSI-SoC 2020. IFIP Advances in Information and Communication Technology, vol 621. pp 301-321 Springer, Cham.

DOI: 10.1007/978-3-030-81641-4_14

1 Lyon Institute of Nanotechnology, University of Lyon, France
2 University of Bordeaux, CNRS UMR 5218, Bordeaux INP Talence, Bordeaux, France
3 Université de Toulouse, LAAS, CNRS, INP Toulouse, Toulouse, France
4 Institute of Industrial Science, LIMMS-CNRS/IIS, The University of Tokyo, Japan

Abstract. Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET) are emerging devices, which are well suited to pursue scaling beyond lateral scaling limitations around 7 nm. This work explores the relative merits and drawbacks of the technology in the context of logic cell design. We describe a junctionless nanowire technology and associated compact model, which accurately describes fabricated device behavior in all regions of operations for transistors based on between 16 and 625 parallel nanowires of diameters between 22 and 50 nm. We used this model to simulate the projected performance of inverter logic gates based on passive load, active load and complementary topologies and to carry out a performance exploration for the number of nanowires in transistors. In terms of compactness, through a dedicated full 3D layout design, we also demonstrate a 48% reduction in lateral dimensions for the complementary structure with respect to 7 nm FinFET-based inverters.

Fig: Perspective view of the Gate-all-around Vertical Nanowire Field Effect Transistors (VNWFET)

Acknowledgments: This work was supported by the French RENATECH network (French national nanofabrication platform) and by the LEGO project through ANR funding (Grant ANR-18-CE24-0005-01).

[paper] 11.8 GHz Fin Resonant Body Transistor

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor 

in a 14nm FinFET CMOS Process 

Udit Rawat, Student Member, IEEE, Bichoy Bahr*, Member, IEEE, 

and Dana Weinstein, Senior Member, IEEE

arXiv:2107.04502v1 [physics.app-ph] 9 Jul 2021

 

Department of Electrical Engineering, Purdue University, West Lafayette USA

*Kilby Labs - Texas Instruments, Dallas, TX, USA.

Abstract: In this work, a compact model is presented for a 14 nm CMOS-based FinFET Resonant Body Transistor (fRBT) operating at a frequency of 11.8 GHz and targeting RF frequency generation/filtering for next generation radio communication, clocking, and sensing applications. Analysis of the phononic dispersion characteristics of the device, which informs the model development, shows the presence of polarization exchange due to the periodic nature of the back-end-of-line (BEOL) metal PnC. An eigenfrequency-based extraction process, applicable to resonators based on electrostatic force transduction, has been used to model the resonance cavity. Augmented forms of the BSIM-CMG (Common Multi-Gate) model for FinFETs are used to model the drive and sense transistors in the fRBT. This model framework allows easy integration with the foundry-supplied process design kits (PDKs) and circuit simulators while being flexible towards change in transduction mechanisms and device architecture. Ultimately, the behaviour is validated against RF measured data for the fabricated fRBT device under different operating conditions, leading to the demonstration of the first complete model for this class of resonant device integrated seamlessly in the CMOS stack.

Fig: Complete 3D FEM Simulation model depicting two adjoining fRBT unit cells. Mx (x=1-3) and Cy (y=4-6) represent the first 6 metal levels that form a part of the BEOL PnC.

Acknowledgement: This work was supported in part by the DARPA MIDAS Program.

 

[paper] Compact Model for SiC Power MOSFETs

Cristino Salcines¹, Sourabh Khandelwal² and Ingmar Kallfass¹ 

A Compact Model for SiC Power MOSFETs 

for Large Current and High Voltage Operation Conditions 

(2021) arXiv-2104. 

1 University of Stuttgart Stuttgart, Germany

2 Macquarie University Sydney, Australia  

Abstract: This work presents a physics based compact model for SiC power MOSFETs that accurately describes the I-V characteristics up to large voltages and currents. Charge-based formulations accounting for the different physics of SiC power MOSFETs are presented. The formulations account for the effect of the large SiC/SiO2 interface traps density characteristic of SiC MOSFETs and its dependence with temperature. The modeling of interface charge density is found to be necessary to describe the electrostatics of SiC power MOSFETs when operating at simultaneous high current and high voltage regions. The proposed compact model accurately fits the measurement data extracted of a 160 milli ohms, 1200V SiC power MOSFET in the complete IV plane from drain-voltage Vd = 5mV up to 800 V and current ranges from few mA to 30 A.

Fig: Output characteristics up to high current and high voltage in logarithmic scale for VGS = 6V to 20V in steps of 0.5V. Symbols are measurements and solid lines simulations of the proposed model. The logarithmic scale eases the visualization of both low and high VDS voltages in a single graph.

[Si2 CMC] to Standardize SPICE Model for SiC MOSFET

May 03, 2021 // By Peter Clarke [eenewsanalog.com] 

The Compact Model Coalition (CMC) working group of the Silicon Integration Initiative (SI2) has agreed to standardize a model for the behaviour of a silicon-carbide MOSFET.

Silicon-carbide offers higher efficiency and faster operation than silicon and has been adopted for several power applications including photovoltaic inverters and converters, industrial motor drives, electric vehicle powertrain and EV charging, and power supply and distribution. A CMC working group will oversee the model development with Analog Devices, Cadence Design Systems, Infineon, Qualcomm, Siemens EDA, Silvaco and Synopsys set to participate.

"I'd encourage companies with a stake in silicon-carbide devices to join this effort and help guide selection of the model which best represents their intended use," 

advised Peter Lee, chair of the CMC.

Now in its 25th year, the Si2 Compact Model Coalition provides semiconductor manufacturers, designers, and simulation tool providers a means to pool resources to fund standardization and optimization of standard compact SPICE models and standard interfaces to promote simulation tool interoperability [Read more...]