Jul 26, 2017

Analysis of Short-Channel Effects in Junctionless DG MOSFETs #papers https://t.co/P2sqAueamw


from Twitter https://twitter.com/wladek60

July 26, 2017 at 11:39AM
via IFTTT

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

M. Banaszeski da Silva, H. P. Tuinhout, A. Zegers-van Duijnhoven, G. I. Wirth and A. J. Scholten
"A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping" 
in IEEE TED, vol. 64, no. 8, pp. 3331-3336, Aug. 2017.
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm [read more...]

Jul 25, 2017

[paper] Compact On-Wafer Test Structures for Device RF Characterization

B. Kazemi Esfeh, K. Ben Ali and J. P. Raskin IEEE Fellow
Compact On-Wafer Test Structures for Device RF Characterization
in IEEE TED, vol. 64, no. 8, pp. 3101-3107, Aug. 2017
doi: 10.1109/TED.2017.2717196

Abstract: The main objective of this paper is to validate the radio frequency (RF) characterization procedure based on compact test structures compatible with 50um pitch RF probes. It is shown that by using these new test structures, the layout geometry and hence the on-chip space consumption for complete sets of passive and active devices, e.g., coplanar waveguide transmission lines and RF MOSFETs, is divided by a factor of two. The validity domain of these new compact test structures is demonstrated by comparing their measurement results with classical test structures compatible with 100–150um pitch RF probes. 50um -pitch de-embedding structures have been implemented on 0.18um RF silicon-on-insulator (SOI) technology. Cutoff frequencies and parasitic elements of the RF SOI transistors are extracted and the RF performance of trap-rich SOI substrates is analyzed under small- and large-signal conditions [read more...]



Jul 8, 2017

[mos-ak] [2nd Announcement and Call for Papers] 15th MOS-AK ESSDERC/ESSCIRC Workshop

MOS-AK ESSDERC/ESSCIRC Workshop
http://www.mos-ak.org/leuven_2017/
September 11, 2017 Leuven
2nd Announcement and Call for Papers


Together with the ASCENT Network represented by Profs Jim Greer and Nicolas Cordero as well as  International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 15th MOS-AK Compact Modeling Workshop which will be organized for consecutive 15time as in integral part of the ESSDERC/ESSCIRC Conference in Leuven on Sept.11, 2017.

Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

Important Dates:
  • Preannouncement - March 2017
  • Call for Papers - June 2017
  • Final Workshop Program - August 2017
  • MOS-AK Workshop - Sept.11, 2017

Venue: Leuven (B) <http://www.esscirc-essderc2017.org/venue>

Topics to be covered include the following among other related to the compact/SPICE modeling :
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Speakers: (tentative list in alphabetic order)
  • Nicolas Cordero, Tyndal (IRL)
  • Denis Flandre, CUL (B)
  • Jim Greer, Tyndal (IRL)
  • Benjamin Iniguez URV (SP)
  • Marcelo Pavanello, FEI (BR)
  • Jean-Pierre Raskin, CUL (B)
  • Wim Schoenmaker, Magwel (B)
  • Chika Tanaka, Toshiba (J)
  • Ashkhen Yesayan, IRPhE (AM)
Prospective authors should submit abstract online
Manuscript submission deadline: 31sth July 2017 (Monday)
(any related inquiries can be sent to papers@mos-ak.org)

Online Workshop Registration
using online registration form <http://www.esscirc-essderc2017.org/howtoregister>
(any related inquiries can be sent to register@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee
WG080717

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Jul 4, 2017

[paper] A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping

A Compact Model for the Statistics of the Low-Frequency Noise of MOSFETs With Laterally Uniform Doping
M. Banaszeski da Silva; H. P. Tuinhout; A. Zegers-van Duijnhoven; G. I. Wirth; A. J. Scholten;
in IEEE Transactions on Electron Devices, vol.PP, no.99, pp.1-6
doi: 10.1109/TED.2017.2713301

Abstract: In this paper, we develop a compact physics-based statistical model for random telegraph noise-related low-frequency noise in bulk MOSFETS with laterally uniform doping. The proposed model is suited for modern compact device models, such as PSP, BSIM, and EKV. With our proposed model, one can calculate the expected value and the variability of the noise as a function of bias and device parameters. We validate the model through numerous experimental results from different CMOS nodes, down to 40 nm. [read more...]