Thursday, September 30, 2010

Shipments of silicon for semiconductor manufacturing raise more than 23%

I copy part of a post from EDN:

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, according to iSuppli estimates.

Global silicon shipments in terms of square inches are bouncing back in 2010, after suffering like most segments did in the 2008/2009 economy.

That's according to a report from iSuppli Corp, which estimated shipments will rise to record levels in 2010.

Shipments of silicon for semiconductor manufacturing in 2010 will grow by 23.6% year-over-year, reaching 8.9 billion total square inches, up from 7.2 billion square inches in 2009, iSuppli forecast. Growth is expected to continue and iSuppli projected that by 2014 12.4 billion total square inches of silicon will be shipped.

read more here....

Sunday, September 26, 2010

Ten Years of Scaling


Saturday, September 25, 2010

Nano antenna concentrates light

Condensed matter physicist Doug Natelson and graduate student Dan Ward have found a way to make an optical antenna from two gold tips separated by a nanoscale gap that gathers light from a laser. The tips "grab the light and concentrate it down into a tiny space," Natelson said, leading to a thousand-fold increase in light intensity in the gap. [more]

Friday, September 24, 2010

Wednesday, September 22, 2010

The pocket beamer is a reality!

Maher Kayal, professor at EPFL's Institute of Electrical Engineering presents the beamer of the future: 1 cm3 of technology that can be integrated into a portable computer or mobile telephone. Nicolas Abélé, technical director of Lemoptix, explains the future developments of this new device.

TSMC, Taiwan universities partner to cultivate semiconductor talent

TSMC, Taiwan universities partner to cultivate semiconductor talent: "TaiwanSemiconductor Manufacturing Co (TSMC), Taiwan's National Cheng ..."

Tuesday, September 21, 2010

Arana Behavioral Modeling Platform (as of Sept. 2010)

I copy part of the press release (by the way, the link in their home page doesn't work...):

Arana platform automates the process of behavioral model creation, generation, optimization, and validation for analog, custom digital, memory and mixed-signal integrated circuits. It features Arana Top-Down Designer, Arana Bottom-Up Designer, Arana Model Optimizer, and Arana Model Validator.

Arana Top-Down Designer supports behavioral model creation from specification or from templates, as well as automated calibration of model parameters against the transistor response and/or measurement data. Arana Bottom-Up Designer allows a circuit designer to automatically generate silicon-faithful parametric behavioral models—accounting for process, voltage, temperature, and loading variations—for functional verification.

Both Arana Bottom-Up Designer and Top-Down Designer support hierarchical modeling and automated generation of formal analog assertions and model test benches. Arana Model Optimizer and Model Validator optimize and validate behavioral models against transistor level responses and characterization and/or measurement data.


Tuesday, September 14, 2010

Paper in IEE Electronics Letters (September 2010)

Analytical modelling of gate tunnelling current of MOSFETs based on quantum tunnelling

Kazerouni, I.A.;   Hosseini, S.E.;   Parashkoh, M.K.;  
Engineering Department, Tarbiat Moallem University of Sabzevar, Sabzevar, Iran 
This paper appears in: Electronics Letters
Issue Date: September 2010
46 Issue:18
On page(s): 1277 - 1279
ISSN: 0013-5194
Digital Object Identifier: 10.1049/el.2010.1339 
Date of Current Version: 09 September 2010
Sponsored by: Institution of Engineering and Technology 


The gate tunnelling current of MOSFETs is an important factor in modelling ultra-small devices. In this reported work, the gate tunnelling current in present-generation MOSFETs is studied. Presented is a model for the gate tunnelling current in MOSFETs having ultra-thin gate oxides. In the proposed model, the electron wavefunction at the semiconductor-oxide interface is calculated and inversion charge by assuming the inversion layer as a potential well, including some simplifying assumptions. Then the gate tunnelling current is calculated using the calculated wavefunction. The proposed model results have excellent agreement with experimental results in the literature.

Monday, September 13, 2010

IEEE SCV EDS: LDMOS reminder & upcoming

Sept. 14th
LDMOS - Technology and Applications
Shekar Mallikarjunaswamy, Alpha Omega Semiconductor

Sept. 28th
The Makers of the Microchip: Creating the Planar Integrated Circuit, Establishing Silicon Valley
David Brock, Cristophe Lecuyer

Oct. 12th
Is it the End of the Road for Silicon in Power Management?
Dr. Alex Lidow, CEO Efficient Power Conversion Corporation

Details on IEEE SCV EDS website:

OLED simulation software

I'm copying here the press release (it must be takes as such, cum grano salis)

sim4tec announces the release of new version 3.0 of its OLED simulation software SimOLED.
New features include:
  • Enhanced powerful graphical representation of results - line and contour plots
  • Electronic, excitonic and optic module seamlessly combined
  • Faster calculation speed
  • Additional results for current, power, quantum efficiencies, CIE diagram and many more
  • Updated graphical user interface
A special highlight is the combination of our well-proven and reliable electronic module with the excitonic and optic modules. This allows users to simulate voltage-dependent optical quantities like the colour maintenance of white OLEDs.
The software is ideally suited for conducting basic research, arbitrary OLED stack design, material parameter extraction and process window identification. Included in the software is an in-depth tutorial containing more than 20 examples, ranging from simple single layer devices up to white hybrid OLEDs.

Friday, September 10, 2010

IDESA Training Courses Calendar

Implementation of widespread IC DEsign Skills in advanced deep submicron technologies at European Academia.

Advanced Analog Implementation flowAnalog circuit design simulation and layout for 90nm and below.

Advanced Digital Physical Implementation flowPower Aware physical design techniques, timing and power closure.

Advanced RF Implementation flowRF Implementation Flow in deep sub-micron CMOS technology.

Design for Manufacturing flowDFM issues are becoming increasingly important for 90nm and below.
The IDESA Course Booking System is managed and maintained by STFC Rutherford Appleton Laboratory, UK. If you have a booking enquiry, please email:

Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
IDESA Course Calendar 2010
Advanced Analog Implementation flow RAL
Advanced Digital Physical Implementation flow AGH
Advanced RF Implementation flow
Design for Manufacturing flow ERLN
IDESA Course Calendar 2011
Advanced Digital Physical Implementation flow ERLN
Design for Manufacturing flow TUL MONS

Course Location key:
AGH AGH University of Science and Technology, Poland CIME CIME, France
ERLN Fraunhofer IIS, Erlangen, Germany IMEC Interuniversitair Micro-Electronica Centrum, Belgium
LUND University of Lund, Sweden MONS Université de Mons, Belgium
MONT University Montpellier 2, France NAP Università degli Studi di Napoli Federico II
PPAZ Péter Pázmány Catholic University, Hungary RAL Rutherford Appleton Laboratory, UK
STU Slovak University of Technology in Bratislava, Slovakia TUL Technical University of Lodz, Poland

Wednesday, September 8, 2010

Where to study nanotech?

Marie Curie Fellows - Centro de Química da Madeira, Funchal, Madeira Island, Portugal.

Accelicon announces Context Dependent Modeling Platform

I copy a part of the original post:

Accelicon Technologies, Inc. announces the market’s first commercially available Context Dependent Modeling Platform based on Accelicon’s flagship device modeling solution MBP. The performance of FETs can vary significantly, at advanced process nodes, due to layout dependent proximity effects. Sources of LDEs include Well Proximity Effect (WPE), lithography distortions, un-intentional stress sources such as Shallow Trench Isolation (LOD Effect) and intentional stressors which are used to enhance the performance of the device. These enhancement techniques include dual-stress liners, embedded SiGe and stress memorization techniques. At advanced process nodes engineers must analyze LDEs to minimize undesirable proximity effects and lithography distortions, and effectively utilize stress enhancement techniques. This analysis can only be conducted after layout extraction, SPICE modeling alone is not sufficient. 

Read more at the original post in LinkedIn:

Accelicon announces Context Dependent Modeling Platform

Simulating the Memristor with spice (as of September 2010)

Here you have a list of papers where people model a memristor:

- H.H. Li and M. Hu, "Compact Model of Memristors and Its Application in Computing Systems," DATE, 2010.

- Á. Rak and G. Cserey, "Macromodeling of the Memristor in SPICE," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, 2010, pp. 632-636.

- D. Batas and H. Fiedler, "A Memristor Spice Implementation and a New Approach for Magnetic Flux Controlled Memristor Modeling," IEEE Transactions on Nanotechnology, 2010, pp. 1-1.

- "Modeling the HP memristor with SPICE,", 2010.

- Valsa, J., Biolek, D. and Biolek, Z. , "An analogue model of the memristor". International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, n/a. doi: 10.1002/jnm.786

Lot of work, isn't it?

Monday, September 6, 2010

8th International System-on-Chip (SoC) Conference, Exhibit & Workshops

Date: Nov. 3-4, 2010
Venue: Hilton Irvine/Orange County Airport
Agenda & Schedule

Early Bird Registration Is Now Open!

Three distinguished keynote speakers:

1. Dr. Ivo Bolsens, Senior Vice President and CCEO, Xilinx Inc.
2. Dr. J. Antonio Carballo, WW Manager, IBM Microelectronics Services, Semiconductor Partner, IBM VC Group, IBM.
3. Raouf Y. Halim, CEO, Mindspeed Technologies, Inc.

Sunday, September 5, 2010

New record set for ferroelectric data storage

Scanning Nonlinear Dielectric Microscope: inset left: Shows topography and electric dipole-moment; inset right: Example of a ferroelectric information storage; [Read more...]