Showing posts with label Negative bias temperature instability. Show all posts
Showing posts with label Negative bias temperature instability. Show all posts

Sep 22, 2021

[paper] Abstraction NBTI model

Stephan Adolf and Wolfgang Nebel
Abstraction NBTI model
it - Information Technology, Sep. 2021
DOI: 10.1515/itit-2021-0005

Abstract: Negative Bias Temperature Instability (NBTI) is one of the major transistor aging effects, possibly leading to timing failures during run-time of a system. Thus, one is interested in predicting this effect during design time. In this work, an Abstraction NBTI model is introduced reducing the state space of trap-based NBTI models using two abstraction parameters, applying a state transformation to incorporate variable stress conditions. This transformation is faster than traditional approaches. Currently, the conversion into estimated threshold voltage damages is a very time-consuming process.

Fig: Trap in the gate oxide of a PMOS transistor

Acknowledgement: The author thanks Kim Grüttner for proofreading the manuscript of the paper. This research is funded by the German Research Foundation through the Research Training Group “SCARE: System Correctness under Adverse Conditions” (DFG-GRK 1765/2), https://www.uni-oldenburg.de/en/scare/. The simulations were partly performed on the HPC Cluster CARL at the University of Oldenburg (Germany), funded by the DFG through its Major Research Instrumentation Program (INST 184/157-1 FUGG) and the Ministry of
Science and Culture (MWK) of the Lower Saxony State.


Feb 7, 2017

[paper] Statistical model of the NBTI-induced ΔVth, ΔSS, and Δgm degradations in advanced pFinFETs

Statistical model of the NBTI induced threshold voltage, subthreshold swing, and transconductance degradations in advanced pFinFETs
J. Franco, B. Kaczer, S. Mukhopadhyay, P. Duhan, P. Weckx, Ph.J. Roussel, T. Chiarella, L.-Å. Ragnarsson, L. Trojman, N. Horiguchi, A. Spessot, D. Linten, A. Mocuta
2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2016, pp. 15.3.1-15.3.4.
DOI: 10.1109/IEDM.2016.7838422
Abstract
We study the stochastic NBTI degradation of pFinFETs, in terms of ΔVth, ΔSS, and Δgm. We extend our Defect-Centric model to describe also the SS distribution in a population of devices of any area, at any stage of product aging. A large fraction of nanoscale devices is found to show a peak g m improvement after stress. We explain this effect in terms of the interaction of individual defects with the percolative channel conduction, and we propose a statistical description of g m aging. Our Vth, SS, and gm aging models are pluggable into reliability-enabled compact models to estimate design margins for a wide variety of circuits. Selected nanoscale device characteristics resulting from 3 percolation paths, generated with the EKV model [read more...]