Monday, December 17, 2018

Friday, December 14, 2018

Thursday, December 13, 2018

IEEE Cledo Brunetti Award 2018 presented to Prof.Dr. Siegfried Selberherr

One of the founders of modern Technology Computer Aided Design (TCAD), Siegfried Selberherr has provided modeling and software development tools invaluable to the continued miniaturization of semiconductor devices. TCAD involves the use of computer simulation to develop and optimize semiconductor processing technologies. Selberherr developed MINIMOS for two-dimensional predictive simulation of the electrical characteristics of miniaturized devices to understand and control the short-channel effects and doping profiles encountered as device sizes shrink. MINIMOS was later enhanced for three-dimensional simulation to address energy transport and interface physics. He also created the ZOMBIE and PROMIS simulators, which incorporated mesh generation and programming interfaces. Selberherr then developed the Vienna Integrated System for TCAD Applications (VISTA) to combine both process and device simulation tools in a common framework. An IEEE Fellow, Selberherr is a professor with the Institute for Microelectronics at the Technische Universität Wien, Vienna, Austria.

Wednesday, December 12, 2018

Determination of full S-parameters of a low-loss two-port device from uncalibrated measurements #paper

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December 12, 2018 at 06:20PM

What is #OpenSource & Why Should You Care?

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December 12, 2018 at 10:56AM

Monday, December 10, 2018

[C4P] ESSDERC / ESSCIRC September 23-26, 2019 Kraków, POLAND

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September 23-26, 2019
Kraków, POLAND
ESSDERC/ESSCIRC annual Conference is the most important European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
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ESSCIRC tracks:
Data Converters
RF and mm-Wave
Frequency Generation
Wireless and Wireline Systems
Sensors, Imager and Biomedical
Digital, Security and Memory
Power Management
ESSDERC tracks:
CMOS Devices and Technology
Opto-, Power and Microwave Devices
Physical Modeling of Materials and Devices
Compact Modeling of Devices and Circuits
Memory Devices and Technology
Emerging non-CMOS Devices and Technologies
Sensor Devices and Technology
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Technical Co-Sponsorship

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ESSDERC Financial Sponsor

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ESSCIRC Financial Sponsor

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All submissions must be received by
8th April 2019


Manuscript guidelines as well as instructions on how to submit electronically will be soon available on the Conference website. Papers must not exceed four A4 pages with all illustrations and references included.

Papers submitted for review must clearly state:

    - the purpose of the work
    - how and to what extent it advances the state-of-the art
    - specific results and their impact

After selection of papers, the authors will be informed about the decision of the Technical Program Committee by e-mail by 
31th May 2019.

At the same time, the complete program will be published on the Conference website. An oral presentation will be given at the Conference for each accepted paper. No-shows will result in the exclusion of the papers from any conference related publication.

The submitted final PDF files should be IEEE Xplore compliant.

For each paper independently, at least one co-author is required to register for the Conference (one registration-one paper policy).

 49th European Solid-State Device Research Conference

ESSCIRC 45th European Solid-State Circuits Conference
September 23-26, 2019Kraków, POLAND


Krzysztof Kasinski (AGH UST, PL)
Robert Szczygiel (AGH UST, PL)


Foundation for AGH
University of Science and Technology
Anna Inglot – Conference Manager
phone: +48 504 004 517
Copyright 2018 Foundation for AGH UST in Cracow. All rights reserved.
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Sunday, December 9, 2018

New Czech law makes ICT #neutrality a #right #paper

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December 09, 2018 at 12:40PM

Tuesday, November 27, 2018

Analysis of #DIBL Effect and Negative Resistance Performance for }NCFET Based on a Compact #SPICE #Model

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November 27, 2018 at 06:19PM

Explicit #Model of Channel Charge, Backscattering, and Mobility for #Graphene #FET in Quasi-#Ballistic Regime

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November 27, 2018 at 04:44PM

Sunday, November 25, 2018

An Illustrated Subway Map of Human Anatomy #modeling

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November 25, 2018 at 07:07AM

Friday, November 23, 2018

Compact #Terahertz #SPICE #Model: Effects of Drude Inductance and Leakage

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November 23, 2018 at 09:13PM

Optimization and #Scaling of #Ge-Pocket #TFET (#paper)

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November 23, 2018 at 04:49PM

#Mobility Calculation of Ge Nanowire #Junctionless and Inversion-Mode Nanowire NFETs With Size and Shape Dependence (#paper)

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November 23, 2018 at 04:47PM

High-k Spacer Consideration of Ultrascaled Gate-All-Around #Junctionless Transistor in Ballistic Regime (#paper)

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November 23, 2018 at 03:20PM

Thursday, November 22, 2018

[mos-ak] [Final Program] 11th International MOS-AK Workshop; Silicon Valley, December 5, 2018

11th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 5, 2018

Together with Sivaco team, the MOS-AK workshop host as well as International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) and all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 11th International MOS-AK Workshop is Silicon Valley.

Scheduled, subsequent 11th MOS-AK SPICE/Compact Modeling Workshop organized in the Silicon Valley, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online: <>

2811 Mission College Blvd., 6th Floor
Santa Clara,  California  95054

Online Registration is still open
(any related enquiries can be sent to

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems

W.Grabinski on the behalf of International MOS-AK Committee


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The Experimental Side of #Modeling - Read online

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November 22, 2018 at 06:43PM

Monday, November 19, 2018

A Path to Energy #Efficiency and #Reliability for ICs: Fully Depleted Silicon-on-Insulator (#FDSOI) Devices Offer Many Advantages - in IEEE Solid-State Circuits Magazine, vol. 10, no. 4, pp. 24-33, Fall 2018 #paper

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November 19, 2018 at 12:10AM

Friday, November 9, 2018

7 reasons I love #opensource and you should too

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November 09, 2018 at 05:01PM

Wednesday, November 7, 2018

#Franz is made in Vienna, Austria with lots of by Stefan Malzner & the amazing community. #opensource

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November 07, 2018 at 07:32PM

Friday, November 2, 2018

Device #Modeling of MgO-Barrier Tunneling Magnetoresistors for Hybrid Spintronic-CMOS

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November 02, 2018 at 09:41PM

ISDCS 2019 in Hiroshima

The International Symposium on Devices, Circuits and Systems & Workshop on Nanoelectronics will take place in Hiroshima (Japan), on March 6-8 2019.

The ISDCS is a premium international forum for scholars, scientists, educators, students and engineers to exchange their latest findings and technological advances in the field of devices, circuits and systems. 

One of the topics is Physics, Analysis and Modeling of Devices. 

Other topics;

Photonics and Optoelectronics of Advanced Materials
Digital and Analog Circuits and Their System Applications
Neural Networks & Neuromorphic Circuits and Systems
Circuit Testing and Verifications
IoT Circuits and Systems
AI Circuits for Machine Learning Systems
Beyond CMOS Circuits and Hybrid systems
Intelligent Systems and Robotics
Environment Electronics and
Their Applications
Visual Communications & Multimedia Signal Processing

This symposium is initiated by IIEST Shibpur in collaboration with Hiroshima University, which will be held annually in India and in Japan alternatively. The first event was held at IIEST Shibpur. The 1st ISDCS-2018 conference proceedings are published in IEEE-explore.  

Deadline: November 15 2018.