Wednesday, August 15, 2018

Monday, August 13, 2018

Accurate semi empirical predictive #model for doped and undoped double gate #DG #MOSFET (Solid-State Electronics Available online 4 August 2018) https://t.co/klJRI2hywk https://t.co/Y3PoUrYO58


from Twitter https://twitter.com/wladek60

August 13, 2018 at 10:02AM
via IFTTT

Saturday, August 11, 2018

#FOSDEM 2019 - Call for participation #C4P https://t.co/t7BFGjDvy5 #paper


from Twitter https://twitter.com/wladek60

August 11, 2018 at 03:35PM
via IFTTT

Friday, August 10, 2018

Physical Insights on #Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around #NSFET for #5nm Technology Node - IEEE Journals & Magazine https://t.co/EVcK4twqtW #paper


from Twitter https://twitter.com/wladek60

August 10, 2018 at 01:32PM
via IFTTT

Why Join an #OpenSource Software #Foundation? - SourceForge Community Blog https://t.co/r9AyUXGnwc


from Twitter https://twitter.com/wladek60

August 10, 2018 at 07:43AM
via IFTTT

Wednesday, August 8, 2018

Hybrid Systems-in-Foil: Enabler or Flexible Electronics

Presented by: Joachim N. Burghartz
Date: 22 August 2018
Time: 11 AM – 12 PM EDT 

Hybrid Systems-in-Foil: Enabler or Flexible Electronics - Flexible electronics add mechanical flexibility, shape adaptivity and stretchability as well as large-area place ability to electronic systems, thus allowing for conquering fundamentally new markets in consumer and commercial applications. Hybrid assembly of large-area devices and ultra-thin silicon chips on flexible substrates is viewed as an enabler to high-performance and reliable industrial solutions as well as to high-end consumer applications of flexible electronics. This talk discusses issues in ultra-thin chip fabrication, device modeling and circuit design, as well as assembly and interconnects for thin chips embedded into foil substrates in which flexible large-area components are implemented for an overall optimized Hybrid System-in-Foil (HySiF).

This message is being sent to you on behalf of Tian-Ling Ren, EDS Education Committee Chair. All participants will receive WebEx details prior to the event. We sincerely hope that you can join us for these special events. Register Now!

#Nanostructured gate dielectric boosts stability of #organic thin-film transistors #TFT https://t.co/hL0l9OTlxi #paper


from Twitter https://twitter.com/wladek60

August 07, 2018 at 10:49PM
via IFTTT

Sunday, August 5, 2018

#Memristors On A Chip Solve Partial #Differential #Equations https://t.co/T2E3smdTSl #paper


from Twitter https://twitter.com/wladek60

August 05, 2018 at 10:38AM
via IFTTT

Tuesday, July 31, 2018

Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7 https://t.co/lXfNZLv67t


from Twitter https://twitter.com/wladek60

July 31, 2018 at 09:00AM
via IFTTT

Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7


from Twitter https://twitter.com/wladek60

July 31, 2018 at 09:00AM
via IFTTT

Monday, July 30, 2018

Friday, July 27, 2018

Thursday, July 26, 2018

#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:49PM
via IFTTT

#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:20PM
via IFTTT

#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:49PM
via IFTTT

#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:20PM
via IFTTT

Wednesday, July 25, 2018

Electrical #contact to #molecules in #semiconductor structures established for the first time https://t.co/s4JvZCyvcL #paper


from Twitter https://twitter.com/wladek60

July 24, 2018 at 11:12PM
via IFTTT

Tuesday, July 24, 2018

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1 https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
via IFTTT

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
via IFTTT

Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O


from Twitter https://twitter.com/wladek60

July 24, 2018 at 05:13PM
via IFTTT

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
via IFTTT

Wednesday, July 18, 2018

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

MOS-AK Workshop at ESSDERC/ESSCIRC
Dresden, Sept. 3, 2018

Subsequent MOS-AK modeling workshop organized at ESSDERC/ESSCIRC in Dresden on Sept. 3, 2018, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

Venue:
Technische Universität Dresden
room CHE/0184/U
Dresden (D)

Agenda:
  • MOS-AK Workshop: Sept. 3, 2018
  • ESSDERC Track4 "Compact modeling of devices and circuit" Sept. 5-6, 2018
    • Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
      Chair: Wladek Grabinski, Thierry Poiroux
    • Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
      Chair: Daniel Tomaszewski, Benjamin Iniguez
(any related inquiries can be sent to registration@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems


WG180718

 

--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Wednesday, July 11, 2018

SINANO Modelling Summer School in Tarragona (Spain): Registration Open!

The 8th SINANO Modelling Summer School will take place in Tarragona (Catalonia, Spain) from September 25 to 28 2018, co-organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. It is also partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.

The official website of the SINAMO Modelling Summer School is:

 

REGISTRATION IS ALREADY OPEN.

The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 6th Framework Programme of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy  (2016, 2014, 2012, 2010, 2008, 2006).

The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.

This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices. It includes a total of 23 lectures targeting topics related to the modelling, simulation and characterization of diferent types of semiconductor devices for nanoelectronics, flexible electronics and photonics. Very hot topics, such as devices for quantum computing, neuromorphic computing, THz electronics and printed electronics will also be addressed. The lecturers are internationally well recognized experts in these fields. Our SINANO Summer School is a unique opportunity for young researchers to become familiar with all scales of device modelling and for many types of device structures, as well as to interact with those top researchers.


 
Invited speakers' short biographies are given in:



Apart from the technical programme, we include a social program consisting of a Welcome Reception and a Gala Dinner in a nice place in front of the Mediterranean Sea. And I hope you can find some time to walk down Tarragona streets and see its main landmarks, many of them dating back to the Roman Empire. Besides, September 23 is Tarragona Patron Saint Day (“Santa Tecla”), and around that date there will be many nice celebrations and musical performances in the city.

Therefore, I encourage researchers in semiconductor device technology, modeling and circuit design to attend this 8th SINANO Modelling Summer School,a.

Monday, July 9, 2018

Thursday, July 5, 2018

Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm https://t.co/dH5G1DQJCm


from Twitter https://twitter.com/wladek60

July 05, 2018 at 06:46PM
via IFTTT

Evaluation of #10nm Bulk #FinFET #RF Performance -Conventional vs. NC-FinFET - IEEE Journals & Magazine #paper https://t.co/dH5G1DQJCm


from Twitter https://twitter.com/wladek60

July 05, 2018 at 06:46PM
via IFTTT

Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper https://t.co/VWfQDyeDJy https://t.co/O8mutPeYJc


from Twitter https://twitter.com/wladek60

July 05, 2018 at 06:40PM
via IFTTT

Heterogeneously Integrated Impedance Based Biosensors (technology scaling on low-noise transimpedance amplifiers was studied using the Enz-Krummenacher-Vittoz (#EKV) model) https://t.co/p91Kn839bj #paper https://t.co/VWfQDyeDJy


from Twitter https://twitter.com/wladek60

July 05, 2018 at 06:40PM
via IFTTT

High accuracy large-signal #SPICE model for silicon carbide (#SiC) #MOSFET https://t.co/93yZ8JEbv8 #paper


from Twitter https://twitter.com/wladek60

July 05, 2018 at 04:27PM
via IFTTT

Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper https://t.co/Lu5f4UXm47 https://t.co/G3A9t83dDd


from Twitter https://twitter.com/wladek60

July 05, 2018 at 04:26PM
via IFTTT

Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era https://t.co/vmVDYfMPcH #paper https://t.co/Lu5f4UXm47


from Twitter https://twitter.com/wladek60

July 05, 2018 at 04:26PM
via IFTTT

Toward a sustainable materials system https://t.co/Z5j8ezhTSm #paper https://t.co/MjjavPoXEv


from Twitter https://twitter.com/wladek60

July 05, 2018 at 10:46AM
via IFTTT

A bright future for microelectronics at CERN | EP Department newsletter https://t.co/QoB8YqI8KZ #paper https://t.co/ID31W3qp3Z


from Twitter https://twitter.com/wladek60

July 05, 2018 at 10:30AM
via IFTTT

Saturday, June 30, 2018

CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper https://t.co/2xBWocU81z


from Twitter https://twitter.com/wladek60

June 30, 2018 at 10:22PM
via IFTTT

CMOS-Integrated Low-Noise Junction Field-Effect Transistors #JFET for #Bioelectronic Applications - IEEE Journals & Magazine https://t.co/2xBWocU81z #paper


from Twitter https://twitter.com/wladek60

June 30, 2018 at 10:21PM
via IFTTT

Monday, June 18, 2018

2018 SINANO Modeling Summer School in Tarragona, Spain

The 8th SINANO Modeling Summer School
in Tarragona (Catalonia) 
September 25 to 28 2018

The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 7th FB of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy (2016, 2014, 2012, 2010, 2008, 2006).

The Sinano Modeling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a program consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world's leading device simulation and electrical characterization experts. This year the SINANO Modeling Summer School will target multi-scale modeling of semiconductor devices.

The 7th SINANO Modeling Summer School is partially sponsored by the SINANO Institute and the DOMINO EU H2020 project. It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The Chair of the 8th SINANO Modeling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project.

Registration, with reduced fees for students, will be open soon.

2018 SINANO Modeling Summer School Program:

Tuesday, September 25 2018
8:30
Opening Session
Benjamin Iñiguez (Universitat Rovira i Virgili)
IEEE EDS MINI-COLLOQUIUM
ON SEMICONDUCTOR DEVICE MODELING
8:55
"Characterization Techniques for Ultrathin Materials and Devices".
Sorin Cristoloveanu (MINATEC, France)
10:05
"Compact Modeling of Organic Thin Film Transistors"
Jamal Deen (McMaster University, Canada)
11:15
Coffee Break
11:40
"Multiscale Reliability Modeling"
Tibor Grasser (TU-Wien, Austria)
12:50
"FOSS TCAD/EDA Tools for Compact Modeling"
Wladek Grabinski (GMC, Switzerland)
14:00
Lunch
SINANO MODELING SUMMER SCHOOL
15:15
"Monte Carlo simulation of THz nanodevices based on III-V semiconductors"
Javier Mateos (University of Salamanca, Spain)
16:25
"Monte Carlo simulation of emerging Si devices"
Francisco Gámiz (University of Granada, Spain)
20:00
Welcome Reception
Wednesday September 26 2018
9:00
"Steep-slope devices: prospects and challenges"
Elena Gnani (University of Bologna)
10:10
"Physics of novel devices for quantum information science"
Thierry Ferrus et al. (Hitachi Cambridge Laboratory, UK)
11:20
Coffee break
11:30
"Spiking Neural Circuits and Systems"
François Danneville (IEMN, France)
12:50
"Time Dependent Variability in CMOS devices: characterization and compact modeling"
Montserrat Nafria (Autonomous University of Barcelona, Spain)
14:00
Lunch
15:15
"Atomic-scale modeling of semiconductor technology"
Kurt Stokbro (Synopsis QuantumWise, Denmark)
16:25
"Physics and modeling of organic and hybrid photovoltaic devices"
Lluís F. Marsal (Universitat Rovira i Virgili, Spain)
Thursday, June 27 2018
9:00
"Complex structure deformation simulation in TCAD for flexible electronics"
Ahmed Nejim (Silvaco Europe Ltd., UK)
10:10
"Mathematical and Semi-physical modeling for emerging device tecnologies & needs"
Firas Mohamed. (Infiniscale, France)
11:20
Coffee break
11:30
"Advanced modeling of AlGaN/GaN HEMT transistors: the ASM HEMT model"
Sourabh Khandelwal (Macquarie University, Australia)
12:50
"Electrical characterization of low frequency noise"
Thomas Gneiting (AdMOS GmbH, Germany)
14:00
Lunch
15:15
"TCAD and compact modeling of source-gated transistors"
Radu Sporea (University of Surrey, UK)
16:25
"Compact modeling of memristors"
Rodrigo Picos (Universitat de les Illes Balears, Spain)
20:30
Gala Dinner

Friday, September 28 2018
9:00
"Current status and trends in RF SOI material and devices"
Jean-Pierre Raskin (Université catholique de Louvain, Belgium)
10:10
"Characterization and Modeling of Organic Diodes and TFTs""
Yvan Bonnassieux (Ecole Polytechnique, France)
11:20
Coffee break
11:30
"Mechanical Deformation-Aware Compact Modeling for Flexible Electronics"
Slobodan Mijalkovic (Silvaco Europe Ltd., UK)
12:50
"Physics and operation of sonic devices"
Giuseppe Iannaccone (University of Pisa, Italy)
14:00
Lunch
15:15
"Parameter extraction and modeling of Amorphous Oxide TFTs"
Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)
16:25
Closing Session

I strongly encourage researchers in semiconductor devices, especially Ph D students and postdocs to attend the SINANO Modeling Summer School in Tarragona!!!

Prof. Benjamin Iñiguez
The Chair of the 8th SINANO Modeling Summer School
Coordinator of the DOMINO project

Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.
-->--
You received this message because you are subscribed to the Google Groups "mos-ak" group.
To unsubscribe from this group and stop receiving emails from it, send an email to mos-ak+unsubscribe@googlegroups.com.
To post to this group, send email to mos-ak@googlegroups.com.
Visit this group at https://groups.google.com/group/mos-ak.
For more options, visit https://groups.google.com/d/optout.

Saturday, June 16, 2018

2018 SINANO Modelling Summer School in Tarragona, Spain

The 8th SINANO Modelling Summer School will take place in Tarragona (Catalonia, Spain) from September 25 to 28 2018.

The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 7th FB of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy  (2016, 2014, 2012, 2010, 2008, 2006).

The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices,  with the world’s leading device simulation and electrical characterization experts.

This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices.

The 7th SINANO Modelling Summer School is partially sponsored by the SINANO Institute and  the DOMINO EU H2020 project.

It is organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. The  Chair of the 8th SINANO Modelling Summer School is Prof. Benjamin Iñiguez, who is also the Coordinator of the DOMINO project. 

Registration, with reduced fees for students, will be open soon. 

Here is updated programme:



Tuesday, September 25 2018


8:30
Opening Session
Opening
Benjamin Iñiguez (Universitat Rovira i Virgili)

IEEE EDS MINI-COLLOQUIUM ON SEMICONDUCTOR DEVICE MODELLING

8:55
"Characterization Techniques for Ultrathin Materials and Devices".
Sorin Cristoloveanu (MINATEC, France)

10:05
"Compact Modeling of Organic Thin Film Transistors"
 Jamal Deen (McMaster University, Canada)

11:15
Coffee Break

11:40
"Multiscale Reliability Modeling"
Tibor Grasser (TU-Wien, Austria)


12:50
"FOSS TCAD/EDA Tools for Compact Modelling"
Wladek Grabinski (GMC, Switzerland)

14:00
Lunch

SINANO MODELLING SUMMER SCHOOL




15:15


"Monte Carlo simulation of THz nanodevices based on III-V semiconductors"
Javier Mateos (University of Salamanca, Spain)

 
16:25


20:00
“Monte Carlo simulation of emerging Si devices”
Francisco Gámiz (University of Granada, Spain)

Welcome Reception







Wednesday September 26 2018


9:00
"Steep-slope devices: prospects and challenges"
Elena Gnani (University of Bologna)

10:10
"Physics of novel devices for quantum information science"
Thierry Ferrus et al. (Hitachi Cambridge Laboratory, UK)

11:20
Coffee break

11:30
“Spiking Neural Circuits and Systems”
François Danneville (IEMN, France)

12:50
"Time Dependent Variability in CMOS devices: characterization and compact modelling"
Montserrat Nafria (Autonomous University of Barcelona, Spain)


14:00
Lunch


15:15
Atomic-scale modelling of semiconductor technology"
Kurt Stokbro (Synopsis QuantumWise, Denmark)

16:25
"Physics and modelling of organic and hybrid photovoltaic devices"
Lluís F. Marsal (Universitat Rovira i Virgili, Spain)


Thursday, June 27 2018








9:00


10:10
Complex structure deformation simulation in TCAD for flexible electronics
Ahmed Nejim (Silvaco Europe Ltd., UK)

"Mathematical and Semi-physical modeling for emerging device tecnologies & needs"
Firas Mohamed. (Infiniscale, France)

11:20
Coffee break

11:30
“Advanced modeling of AlGaN/GaN HEMT transistors: the ASM HEMT model”
Sourabh Khandelwal (Macquarie University, Australia)

12:50
"Electrical characterization of low frequency noise"
Thomas Gneiting (AdMOS GmbH, Germany)


14:00
Lunch

15:15
 “TCAD and compact modelling of source-gated transistors”
 Radu Sporea (University of Surrey, UK)

16:25


20:30          
"Compact modeling of memristors”
Rodrigo Picos (Universitat de les Illes Balears, Spain)

Gala Dinner





Friday, September 28 2018




9:00


10:10
Current status and trends in RF SOI material and devices
Jean-Pierre Raskin (Université catholique de Louvain, Belgium)

"Characterization and Modelling of Organic Diodes and TFTs”"
Yvan Bonnassieux. (Ecole Polytechnique, France)

11:20
Coffee break

11:30
“Mechanical Deformation-Aware Compact Modeling for Flexible Electronics”
Slobodan Mijalkovic(Silvaco Europe Ltd., UK)

12:50             "Physics and operation of sonic devices”
                      Giuseppe Iannaccone (University of Pisa, Italy)

14:00             Lunch

15:15            “Parameter extraction and modelling of Amorphous Oxide TFTs”
                      Benjamin Iñiguez (Universitat Rovira i Virgili, Spain)

16:25             Closing Session



 I strongly encourage researchers in semiconductor devices, especially Ph D students and postdocs to attend the SINANO Modelling Summer School in Tarragona!!!


Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most  important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.