Monday, October 8, 2018

Michael Shur winning the 2018 IEEE EDS J.J. Ebers Award


Congratulations to Prof. Michael Shur for winning the 2018 IEEE EDS J.J. Ebers Award "For pioneering the concept of ballistic transport in nanoscale semiconductor devices"

Recent Winners of the J.J. Ebers Award
2017 - Kang L. Wang "For contributions and leadership in strained SiGe and magnetic memory technologies"
2016 - Jaroslav Hynecek "For the pioneering work and advancement of CCD and CMOS image sensor technologies"
2015 - Jack Yuan-Chen Sun "For sustained leadership and technical contributions to energy efficient foundry CMOS technologies"
2014 - Joachim N. Burghartz "For contributions to integrated spiral inductors for wireless communication ICs and ultra-thin silicon devices for emerging flexible electronics"
2013 - Nobukazu Teranishi "For development of the Pinned Photodiode concept widely used in Image Sensors”
2012 - Yuan Taur "For contributions to the advancement of several generations of CMOS process technologies"
2011 - Stuart Ross Wenham “For technical contributions and successful commercialization of high efficiency solar cells”
2010 - Mark E. Law “For contributions to widely used silicon integrated circuit process modeling”

Friday, October 5, 2018

1st Latin American Electron Devices Conference in Colombia

The 1st Latin American Electron Devices Conference (LAEDC 2019) will be held from February 24 to 27 2019 in Armenia, Colombia.

It will take place in parallel with the 2019 Latin American Symposium on Circuits and Systems (2019 LASCAS), also from February 24 to 27 2019 in Armenia, Colombia.


LAEDC is intended to be a top international conference about electron devices. It is thought to become the Latin American equivalent to ESSDERC in Europe. As ESSDERC is held in parallel with a solid state circuits conference, ESSDERC, LAEDC will be organized in combination with LASCAS.

LAEDC will also be the Latin American equivalent to the Electron Devices Technology and Manufacturing Conference (EDTM), organized every year in Asia.

Proceedings will be published by IEEE and will be available on IEEE Xplore.

There is a negotiation to publish a Special Issue in a top journal  containing extended versions of selected papers presented in LAEDC.

One of the topics of LAEDC is Modeling and Simulation. All electron devices can be targeted.

The deadline for paper submission is October 15 2018.

Armenia City is the capital of the department of Quindio. It is located in the Colombian region known as the coffee triangle. Since 2011, this region is recognized by the UNESCO as a world cultural heritage due to its exceptional landscapes that are the mixture of natural beautifulness and cultural traditions around the coffee growing. Different theme parks related to cultural and agricultural traditions are also located in the department of Quindio, which turns out the LAEDC an opportunity not only for academic exchange but also for knowing and enjoying the traditions around the coffee growing.

As Publication Chair, I strongly encourage researchers in device modeling to submit papers to the  1st Latin American Electron Devices Conference!

New offer of a Ph D scholarship about Device modeling in Tarragona (Spain)

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for three years.  The position will start between February and April 2019.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of devices for flexible and printed electronics, including sensing applications, in particular organic and oxide TFTs.
The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices. We are currently coordinating a European Union funded project (DOMINO) about those topics.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible) with passport number
2) Copy of their diploma
3) copy of their passport
4) Academic certificate (translated into English by an official translator) including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.

Candidates are requested to send their documents by e-mail to:
Prof. Benjamin IñiguezDepartment of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26

43007
Tarragona (Spain)

 Email: benjamin.iniguez@gmail.com 

Tel: +34977558521 Fax:+34977559610

Deadline for documents submission: October 20 2018.
 
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information.
Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

Thursday, October 4, 2018

[mos-ak] [2nd Announcement and C4P] 11th International MOS-AK Workshop, Silicon Valley, December 5, 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
11th International MOS-AK Workshop
(co-located with the IEDM and CMC Meetings)
Silicon Valley, December 5, 2018

Together with Silvaco, lead sponsor and local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to consecutive, 11th International MOS-AK Workshop which will be organized at Silvaco HQ on Dev. 5, 2018 (co-located with the IEDM and CMC Meetings)

Planned 11th International MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue
Silvaco
2811 Mission College Blvd., 6th Floor
Santa Clara, California 95054

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
Important Dates: 
  • Call for Papers - Sept. 2018
  • 2nd Announcement - Nov. 2018
  • Final Workshop Program - Oct. 2018
  • MOS-AK Workshop: Dec. 5, 2018
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)

Postworkshop IJHSES Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee

WG041018

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Monday, October 1, 2018

[mos-ak] [2nd Announcement and Call for Papers] 2nd MOS-AK/India Conference, IIT Hyderabad, Feb. 25-27, 2019

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
2nd MOS-AK/India Conference
IIT Hyderabad
Feb. 25-27, 2019 

Together with the MOS-AK/India Steering Committee and executive local organizers at the IIT Hyderabad as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 2nd MOS-AK/India Conference at IIT Hyderabad between Feb. 25-27, 2019 

Venue
Indian Institute of Technology (IIT) Hyderabad
Hyderabad, Kandi
Telangana State, India

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

Compact Modeling Track  
Circuits and Systems Track  
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • FOSS TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT and SOI-based memory cells
  • Organic, Bio/Med devices/technology modeling
  • Microwave, RF device modeling, HV/Power device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D reliability/ageing, DFY, DFT 
  • Foundry/Fabless Interface Strategies
  • Analog Circuits
  • Biomedical and Life-Science Circuits, Systems and Applications
  • Circuits and Systems for Communication
  • Emerging Technologies for Circuits and Systems
  • HP/HV IC Designs
  • Memory Circuits and Systems
  • Mixed Signal Circuits
  • RF/mm-Wave IC Design and Technology
  • Sensory Systems System-on-Chip and CAD
  • Testing Technology
  • VLSI Systems & Applications
  • And any other IC design related topic

Online Abstract Submission (any related enquiries can be sent to secretary.mosak.india@gmail.com)

Original unpublished works in topics related to the following areas (but not limited to) can be submitted for publication. The proceedings of the conference will be submitted to IEEE Explore. Best Paper Award: Gold leaf, Silver leaf and Bronze leaf certificates will be given to best papers.

Highest Ranked papers from regular submission will be invited to extend their paper in the form of a book chapter. All these submission will be published in the form of a book titled "Compact Modeling: Technology, Devices, IC Design" by River Publishers, the technical program promoters of MOS-AK/India 2019 Conference. 
Author Instruction and Registration Details available as a pdf document

Important Dates:
Call for Papers - 1 Sept. 2018
2nd Announcement -  1 Oct. 2018
Paper and Tutorial Submission Deadline - 1 Nov. 2018
Notification of Acceptance - 15 Dec. 2018
Registration and Camera Ready Paper Submission - 10 Jan. 2019
Final Conference Program - 15 Jan. 2019
MOS-AK/India Conference - February 25-27, 2019
Online registration (to be open in Jan. 2019; any related enquiries can be sent secretary.mosak.india@gmail.com)

Extended MOS-AK Committee


WG010118
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Sunday, September 30, 2018

Microsoft #MSDOS #opensource https://t.co/e7Qeg2fMqH


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September 30, 2018 at 06:09PM
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Friday, September 28, 2018

New Charge Pumping Current #Model Assuming Exponential Tails in the Trap Energy Distribution. This modified expression leads to a different method of extracting the trap emission time constant https://t.co/LUtOI11Och


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September 28, 2018 at 12:20PM
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Thursday, September 27, 2018

System76 To Release A "New #opensource #Computer" https://t.co/CglryyCNZU https://t.co/SN8OYHydYb


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September 27, 2018 at 05:14PM
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[paper] Importance of complete characterization setup on onwafer TRL calibration in sub-THz range

Chandan Yadav, Marina Deng, Magali De Matos, Sebastien Fregonese
and  Thomas Zimmer
IMS Laboratory, University of Bordeaux
351 cours de la Libération – 33405 Talence cedex, France

Abstract: In this paper, we present the effect of different sub-mm and mm-wave probe geometry and topology on the measurement results of dedicated test-structures calibrated with on-wafer TRL. These results are compared against 3D EM simulation of the intrinsic test-structures. To analyze difference between the measured and intrinsic EM simulation results, onwafer TRL calibration performed on EM simulation results of a dedicated test-structure is also presented. 

FIG: 3D view of the Open-M1 where metal-1 (M1) does not have connection with ground as shown in the enlarged view.



Wednesday, September 26, 2018

#Modeling of Electron Devices Based on 2-D Materials. Shortly analyze the main open challenges of modeling 2-D-based electron devices. https://t.co/GkhpFYFS3H


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September 26, 2018 at 02:48PM
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Tuesday, September 25, 2018

ST and Leti to make #GaN-on-#Si power #transistors https://t.co/yNCDikxtpE #paper


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September 25, 2018 at 12:15AM
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Saturday, September 22, 2018

Contacting and Gating #2D #Nanomaterials https://t.co/IgqlN6pi1c #paper


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September 22, 2018 at 02:11PM
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Thursday, September 20, 2018

Friday, September 14, 2018

Ph D student scholarship about compact modeling at URV (Tarragona, Spain)

We offer one scholarship for a Ph D student position in the Department of Electronic Engineering in the Universitat Rovira i Virgili (URV), in Tarragona, Spain.

The duration of the grant will be for three years. The monthly salary will be about 1000 Euro/month, which is more than enough to live in Tarragona. The position will start between January and April 2019.
The candidate should have a Bachelor or Master degree in Electrical Engineering, Electronic Engineering, Telecommunication Engineering or Physics. A good background in Semiconductor Physics, Semiconductor Devices, or Integrated Circuit Design will be highly appreciated.

The work to be done by the candidate will be focused on the development of new techniques of characterization and modeling of novel advanced semiconductor devices, in particular nanoscale MOSFETs under cryogenic conditions for Quantum Computing.This work will be carried out in collaboration with a research team in IMEC in Leuven (Belgium).
The NEPHOS group at URV is one of the most powerful teams in Europe in the area of compact modeling of semiconductor devices.

Required documents for applicants

Applicants are required to send to the address specified below the following documents (in English or Spanish):
1) a full Curriculum Vitae (as complete as possible) with passport number
2) Copy of their diploma
3) copy of their passport
4) Academic certificate including their marks (it is important that the number of hours or credits of each subject appears). It is also very important that the document specifies what is the minimum mark for passing a given subject and what is the maximum mark that can be awarded.
Candidates are requested to send their documents by e-mail to:
Prof. Benjamin IñiguezDepartment of Electronic, Electrical and Automatic Control Engineering
Universitat Rovira i Virgili (URV)
Avinguda Països Catalans, 26
43007
Tarragona (Spain)Email: benjamin.iniguez@gmail.comTel: +34977558521 Fax:+34977559610

Deadline for documents submission: October 6 2018
You can contact Prof. Benjamin Iñiguez (Benjamin.Iniguez@gmail.com) for more information
Tarragona is a medium city (100000 inhabitants) with a Mediterranean climate and many recreation opportunities (nice beaches, theme parks, nature preserves, mountain hiking, touristic resorts and facilities). It is located 100 km Southwest of Barcelona, and it is very well connected by train, bus, highways and even low cost flights from its own airport. Additional information about the University and the department can be found at: www.urv.cat

Tuesday, September 11, 2018

[mos-ak] [press note] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

16th MOS-AK Workshop at ESSDERC/ESSCIRC
http://www.mos-ak.org/dresden_2018/
Dresden, Sept. 3, 2018

The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its 16th MOS-AK Workshop in the timeframe of ESSDERC/ESSCIRC. The event was hosted on September 3rd, 2018, by the TU Dresden in Dresden, Germany. The technical program of the event was coordinated by the MOS-AK TPC Committee. The workshop has received technical program promotion provided by ASCENT Network, Europractice, EPFL EDlab, IJHSES as well as NEEDS of nanoHUB.org

The MOS-AK workshop was opened by Wladek Grabinski, who has welcomed all the attendees. A group of 30+ international academic researchers and modeling engineers attended 10 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support.

The workshop was chaired by Larry Nagel, OEC (USA), Suba Subramaniam, XFAB (D) and Matthias Bucher, TUC (GR). In the first morning session Wladek Grabinski gave an overview of the MOS-AK Community. Afterwards, Prof. Muhammad Mustafa Hussain from KAUST (SA) held a talk of "Physically Compliant CMOS Electronics Enabled Interactive Electronic System". It followed a talk by Dr. Sadayuki Yoshitomi from Toshiba Memory Corp. (J) gave some insights of "RF CMOS Compact modeling technologies past and future".
Krishna Pradeep from ST Microelectronics (D) started the second morning session with a talk entitled "Analysis and modeling of wafer level process variability in advanced FD-SOI devices using split C-V and gate current data". Kerim Yilmaz from TH Mittelhessen (D) offered a modeling approach for "Scaling correlation between DG & GAA MOSFETs". Dr. Laurie Calvet from University Paris-Sud (F) held a talk on "Compact Modeling for Neuromorphic Applications". The morning session ended with "Advanced PDK and Technologies accessible through ASCENT" by Dr. Luca Perniola from CEA (F).

The afternoon session continued with four additional talks, where Dr. Farzan Jazaeri from EPFL (CH) gave a talk on "Reliability Modeling in Harsh Radiation for Space Applications". Prof. Benjamin Iniguez from URV (SP) explained the latest results on "Low frequency noise modeling of organic and IGZO TFTs". Dr. Mike Schwarz from NanoP (D) continued with the topic "Schottky Barrier MOSFET Device Physics for Cryogenic Applications". The session was closed by a talk of Dr. Daniel Tomaszewski, ITE (PL), on various methodologies of "Compact Modeling for Process and Device Characterization".

The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and all the presentations are available online for download at http://www.mos-ak.org/dresden_2018/.


Photo: Part of the participants of the 16th MOS-AK Workshop at ESSDERC/ESSCIRC

Afterward all the participants could follow ESSDERC Track4 "Compact modeling of devices and circuit" on Sept. 5-6, 2018
Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
Chair: Wladek Grabinski, Thierry Poiroux
Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
Chair: Daniel Tomaszewski, Benjamin Iniguez

The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA, China and India throughout coming 2018/2019 years, including:
About MOS-AK Association:
MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

   
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Monday, September 10, 2018

Jushan Xie New Vice-Chair of #Si2 #Compact #Model Coalition #CMC https://t.co/5P0iKUCOD3 https://t.co/L8Yv0gq1m3


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September 10, 2018 at 06:34PM
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18 #Python programming books for beginners and veterans https://t.co/DbR7XiA3Sr #opensource


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September 10, 2018 at 09:34AM
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Saturday, September 8, 2018

Design of an ultralow power CNTFET based 9T SRAM with shared BL and half select free techniques #paper IJNM https://t.co/pltPaaF9SI


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September 08, 2018 at 04:32PM
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#FOSSCON 2018: Where #OpenSource and #LEGO Collide | Tux Machines https://t.co/SfKMUbpYVq


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September 08, 2018 at 01:09PM
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Thursday, September 6, 2018

Ultrahigh-Sensitive #CMOS pH #Sensor Developed in the BEOL of Standard 28 nm #UTBB #FDSOI https://t.co/Mdbk2AswjV #paper


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September 06, 2018 at 06:29PM
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#SPICE #Modeling of #Photoelectric Effects in Silicon With Generalized Devices - IEEE Journals & Magazine https://t.co/QecgTxVHhR


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September 06, 2018 at 02:46PM
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Tuesday, August 28, 2018

Fujitsu triples output #power of #GaN #HEMTs https://t.co/mx7SeL9xSD #paper


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August 28, 2018 at 05:16PM
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Thursday, August 23, 2018

C4P: Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Call for Papers for a Special Issue 
of IEEE Transactions on Electron Devices
on “Reliability of CMOS Logic, Memory, Power and Beyond CMOS Devices

Submission deadline: March 31, 2019; Publication date: October 2019

Reliability of electronic devices continues to remain as a serious issue for several technology generations. Bias Temperature Instability (BTI) continues to impact CMOS logic devices for High-K Metal Gate (HKMG) technologies, while Hot Carrier Degradation (HCD) and Self Heating Effect (SHE) have evolved as additional issues for FinFETs. The Time Dependent Dielectric Breakdown (TDDB) is still a concern and needs attention. These topics are also of interest for future devices with different channel materials (such as SiGe, Ge or III-V) and architectures (such as Gate All Around Nano Sheet FETs). The mechanisms governing degradation of program/erase window with cycling, data retention before and after cycling, etc. in conventional Vertical NAND and different emerging memories such as Resistive RAM, Phase Change RAM, Magnetic RAM and Ferroelectric RAM are of interest. Different power devices (Si and SiC FETs, IGBTs, GaN HEMTs) are becoming mainstream now and their reliability needs to be accessed. Finally, very little has been studied on the reliability of futuristic 2D channel devices.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the an in the field of device reliability based on both experimental results and theoretical models. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:

  • Advanced Transistors: Negative and Positive Bias Temperature Instabilities; Hot Carrier Degradation; SelfHeating Effects; De-convolution of BTI-HCI-SHE; Variability; Random Telegraph Noise; Alternative (SiGe, Ge and III-V) channels; Novel device architectures; etc.;
  • Gate Dielectrics: Charge trapping and breakdown including TDDB; Reliability of novel gate dielectrics and materials for logic and memory devices; Evaluation and modeling of progressive breakdown; Gate dielectric reliability on SiGe, Ge and III-V channels; etc.;
  • Reliability of Memory Devices: DRAM and NVM including 2D and 3D NAND; Novel memory devices such as Re-RAM, Phase Change RAM, MRAM; etc.;
  • Power Devices: MOSFET, HEMT, IGBT on different materials (GaN, SiC, Ga203); etc.;
  • RF Devices: High frequency effects; GaN HEMT; RF 801 etc.
  • Novel Devices: Negative Capacitance FETs; Ferroelectric memory FETs; Tunnel FETs; Transistors with 2D semiconductors (graphene, M082); Spintronic devices; Neuromorphic devices, etc.;
  • Process-Related Reliability: Reliability issues related to different fabrication processes and layout for the above devices.
  • Device-Circuit Correlation: Impact of device reliability on circuit operation including any correlation between different effects; development of compact models; circuit simulation; etc.

Submission instructions: Manuscripts should be submitted in a double column format using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/pub1ications/authors/author_templates.html

In your cover letter, please indicate that your submission is for this special issue.

Submission deadline: March 31, 2019 Publication date: October 2019

Guest Editors:

  1. Dr. Andreas Kerber, Globalfoundries, USA
  2. Dr. Chandra Mouli, Micron Technology Inc., USA
  3. Prof. Durga Misra, New Jersey Institute of Technology, USA
  4. Prof. Gaudenzio Meneghesso, University of Padova, USA
  5. Dr. James Stathis, IBM, USA
  6. Prof. Ninoslav D. Stojadinovié, University of Nis, RS
  7. Dr. Randy Koval, Intel, SG
  8. Prof. Souvik Mahapatra, Indian Institute of Technology, Bombay, IN (Guest EIC)
  9. Dr. Stephen Ramey, Intel, USA
  10. Prof Tibor Grasser, TU, Wien, A


Wednesday, August 22, 2018

FOSDEM 2019 Call for Participation

XIX FOSDEM Edition 
Saturday 2nd and Sunday 3rd February 2019 
ULB Campus Solbosch in Brussels.

We now invite proposals for main track presentations, developer rooms, stands and lightning talks. FOSDEM offers open source and free software developers a place to meet, share ideas and collaborate. Renowned for being highly developer oriented, the event brings together some 8000+ geeks from all over the world. We will record and stream all main tracks, devrooms and lightning talks live. The recordings will be published under the same license as all FOSDEM content (CC-BY). If, exceptionally, you believe there is a legitimate reason why your presentation should not be streamed or recorded, you must seek our agreement before submitting it.

Main Tracks
Previous editions have featured main tracks centered around security, operating system development, community building, and many other topics. Presentations are expected to be 50 minutes long (including audience questions) and should cater to a varied technical audience. The conference covers reasonable travel expenses agreed in advance and arranges accommodation for accepted main track speakers if needed.

Proposals for main track presentations should be submitted using Pentabarf: https://fosdem.org/submit. If you already created an account in the system for a previous edition, please reuse it rather than re- registering.

Submissions will be reviewed in two batches, beginning with those received by 13 October. The final deadline is 3 November.

Questions or remarks? Contact us at program@fosdem.org.

Key dates:
13 October: deadline for first batch of main track proposals
3 November: final deadline for main track proposals
1 November onwards: main track talks announced (in batches)

Developer Rooms
Developer rooms are assigned to self-organising groups to work together on open source and free software projects, to discuss topics relevant to a broader subset of the community, etc. Most content should take the form of presentations. Proposals involving collaboration across project or domain boundaries are strongly encouraged.

Developer room proposals should be submitted through the form at
https://fosdem.org/devroom which contains further information.

Questions or remarks? Contact us at devrooms@fosdem.org.

Key dates:
20 September: deadline for developer room proposals
30 September: accepted developer rooms announced
16 October (or earlier): developer rooms issue Calls for Participation
15 December (or earlier): developer rooms publish complete schedules

Stands
FOSDEM offers open source and free software projects the opportunity to display their work during the event. At its stand, a project can share information, demo software, sell merchandise, give away goodies, and so on, and personally interact with the visitors.

What we offer:
- one 180x80cm table, positioned in one of the buildings with developer
  rooms, for the entire duration of the conference. A second table is
  possible in a few cases, but the pressure on space means this is
  becoming increasingly rare and needs strong justification. Joint
  submissions that share a table between related projects will be
  favoured in the selection process.
- two chairs per table
- one power socket type C/E (if you require adapters or additional
  sockets, please bring them yourself)
- fast uplink shared wireless Internet access

To apply, please fill out the form at: https://fosdem.org/stands which
contains further information.

Questions or remarks? Contact us at stands@fosdem.org.

Key dates:
2 November: deadline for stand proposals
11 November: accepted stands announced

Lightning talks
Lighting talks are short — 15 minute long — talks on a wide variety of topics. Anyone who has something interesting to say about an open source or free software topic can apply. We particularly encourage topics that do not fit in any of the developer rooms.

Proposals for lightning talks should be submitted using Pentabarf: https://fosdem.org/submit. Please select "lightning Talks" in the "track" field. If you already created an account in the system for a previous edition, please reuse it rather than re-registering.

Questions or remarks? Contact us at lightningtalks@fosdem.org.

Key dates:
24 November: deadline for lightning talk proposals
15 December: accepted lightning talks announced

All deadlines are at 23.59 UTC.
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Tuesday, August 21, 2018

Cryogenic MOS Transistor Model https://t.co/yuB4LVzdrZ #paper This paper presents a physics-based analytical model for the MOST operating continuously from room temperature down to 4.2K from depletion to strong inversion and in the linear and saturation regimes.


from Twitter https://twitter.com/wladek60

August 21, 2018 at 01:48PM
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A Review of #Silicon #Photonics https://t.co/NW3NKTiUXq #paper


from Twitter https://twitter.com/wladek60

August 20, 2018 at 10:43PM
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Saturday, August 18, 2018

Bluespec, Inc. Releases a New Family of #OpenSource #RISC-V #Processors https://t.co/qtfdmtXjqe


from Twitter https://twitter.com/wladek60

August 18, 2018 at 03:23PM
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Special issue on advanced solution methods for #modeling complex electromagnetic problems - Wang - - International Journal of Numerical Modelling: Electronic Networks, Devices and Fields - Wiley Online Library https://t.co/FbeN2V72B7


from Twitter https://twitter.com/wladek60

August 18, 2018 at 12:14PM
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Wednesday, August 15, 2018

Monday, August 13, 2018

Accurate semi empirical predictive #model for doped and undoped double gate #DG #MOSFET (Solid-State Electronics Available online 4 August 2018) https://t.co/klJRI2hywk https://t.co/Y3PoUrYO58


from Twitter https://twitter.com/wladek60

August 13, 2018 at 10:02AM
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Saturday, August 11, 2018

#FOSDEM 2019 - Call for participation #C4P https://t.co/t7BFGjDvy5 #paper


from Twitter https://twitter.com/wladek60

August 11, 2018 at 03:35PM
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Friday, August 10, 2018

Physical Insights on #Quantum Confinement and Carrier Mobility in Si, Si0.45Ge0.55, Ge Gate-All-Around #NSFET for #5nm Technology Node - IEEE Journals & Magazine https://t.co/EVcK4twqtW #paper


from Twitter https://twitter.com/wladek60

August 10, 2018 at 01:32PM
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Why Join an #OpenSource Software #Foundation? - SourceForge Community Blog https://t.co/r9AyUXGnwc


from Twitter https://twitter.com/wladek60

August 10, 2018 at 07:43AM
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Wednesday, August 8, 2018

Hybrid Systems-in-Foil: Enabler or Flexible Electronics

Presented by: Joachim N. Burghartz
Date: 22 August 2018
Time: 11 AM – 12 PM EDT 

Hybrid Systems-in-Foil: Enabler or Flexible Electronics - Flexible electronics add mechanical flexibility, shape adaptivity and stretchability as well as large-area place ability to electronic systems, thus allowing for conquering fundamentally new markets in consumer and commercial applications. Hybrid assembly of large-area devices and ultra-thin silicon chips on flexible substrates is viewed as an enabler to high-performance and reliable industrial solutions as well as to high-end consumer applications of flexible electronics. This talk discusses issues in ultra-thin chip fabrication, device modeling and circuit design, as well as assembly and interconnects for thin chips embedded into foil substrates in which flexible large-area components are implemented for an overall optimized Hybrid System-in-Foil (HySiF).

This message is being sent to you on behalf of Tian-Ling Ren, EDS Education Committee Chair. All participants will receive WebEx details prior to the event. We sincerely hope that you can join us for these special events. Register Now!

#Nanostructured gate dielectric boosts stability of #organic thin-film transistors #TFT https://t.co/hL0l9OTlxi #paper


from Twitter https://twitter.com/wladek60

August 07, 2018 at 10:49PM
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Sunday, August 5, 2018

#Memristors On A Chip Solve Partial #Differential #Equations https://t.co/T2E3smdTSl #paper


from Twitter https://twitter.com/wladek60

August 05, 2018 at 10:38AM
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Tuesday, July 31, 2018

Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7 https://t.co/lXfNZLv67t


from Twitter https://twitter.com/wladek60

July 31, 2018 at 09:00AM
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Analytical #modeling of channel potential and threshold voltage of triple material gate AlGaN/GaN HEMT including trapped and polarization‐induced charges https://t.co/5pjOzA7eik https://t.co/7ibTrRWoH7


from Twitter https://twitter.com/wladek60

July 31, 2018 at 09:00AM
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Monday, July 30, 2018

Friday, July 27, 2018

Thursday, July 26, 2018

#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:49PM
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#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:20PM
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#RISC-V’s #OpenSource Architecture Shakes Up Chip #Design https://t.co/V1YgHIeH4H #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:49PM
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#RISCV’s #OpenSource Architecture Shakes Up Chip #Design - IEEE Spectrum https://t.co/ben2ocypsI #paper


from Twitter https://twitter.com/wladek60

July 26, 2018 at 09:20PM
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Wednesday, July 25, 2018

Electrical #contact to #molecules in #semiconductor structures established for the first time https://t.co/s4JvZCyvcL #paper


from Twitter https://twitter.com/wladek60

July 24, 2018 at 11:12PM
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Tuesday, July 24, 2018

Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1 https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
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Analysis of the Channel and Contact Regions in Staggered and Drain-Offset ZnO Thin-Film Transistors With #Compact #Modeling - IEEE Journals & Magazine https://t.co/T4cI4ySoH1


from Twitter https://twitter.com/wladek60

July 24, 2018 at 09:18PM
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Characterization and #Modeling of Temperature Effects in #3D #NAND Flash Arrays—Part II: Random Telegraph #Noise https://t.co/gQUJCnoP3O


from Twitter https://twitter.com/wladek60

July 24, 2018 at 05:13PM
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A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8 https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
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A Physics-Based #Compact #Model of #SiC Junction Barrier Schottky Diode for Circuit Simulation - Published in: IEEE Transactions on Electron Devices ( Volume: 65, Issue: 8, Aug. 2018 ) https://t.co/68fIGLy7M8


from Twitter https://twitter.com/wladek60

July 24, 2018 at 10:12AM
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Wednesday, July 18, 2018

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC in Dresden, Sept. 3, 2018

MOS-AK Workshop at ESSDERC/ESSCIRC
Dresden, Sept. 3, 2018

Subsequent MOS-AK modeling workshop organized at ESSDERC/ESSCIRC in Dresden on Sept. 3, 2018, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

Venue:
Technische Universität Dresden
room CHE/0184/U
Dresden (D)

Agenda:
  • MOS-AK Workshop: Sept. 3, 2018
  • ESSDERC Track4 "Compact modeling of devices and circuit" Sept. 5-6, 2018
    • Wednesday 14:20-15:40 B4L-G Compact Modeling (3 papers)
      Chair: Wladek Grabinski, Thierry Poiroux
    • Thursday 10:20-12:0 C2L-F Compact Modeling of Electron Devices (4 papers)
      Chair: Daniel Tomaszewski, Benjamin Iniguez
(any related inquiries can be sent to registration@mos-ak.org)

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems


WG180718

 

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Wednesday, July 11, 2018

SINANO Modelling Summer School in Tarragona (Spain): Registration Open!

The 8th SINANO Modelling Summer School will take place in Tarragona (Catalonia, Spain) from September 25 to 28 2018, co-organized by the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV), in Tarragona. It is also partially sponsored by the SINANO Institute and the DOMINO EU H2020 project.

The official website of the SINAMO Modelling Summer School is:


REGISTRATION IS ALREADY OPEN. The SINANO Modeling Summer School extended deadline for the reduced fee registration is now: September 12.

The SINANO summer school was established in 2005, in the from of the SINANO Network of Excellence (funded by the 6th Framework Programme of the EU). The previous editions were held in Glasgow (2005) and in Bertinoro, Italy  (2016, 2014, 2012, 2010, 2008, 2006).

The Sinano Modelling Summer School is a bi-annual comprehensive set of classes aimed at doctoral or postdoctoral level researchers from both industry and academia. Via a programme consisting of lectures, tutorials, advanced discussion groups, students will expand and refine their knowledge of the design, optimization, simulation and characterization of cutting edge semiconductor devices, with the world’s leading device simulation and electrical characterization experts.

This year the SINANO Modelling Summer School will target multi-scale modelling of semiconductor devices. It includes a total of 23 lectures targeting topics related to the modelling, simulation and characterization of diferent types of semiconductor devices for nanoelectronics, flexible electronics and photonics. Very hot topics, such as devices for quantum computing, neuromorphic computing, THz electronics and printed electronics will also be addressed. The lecturers are internationally well recognized experts in these fields. Our SINANO Summer School is a unique opportunity for young researchers to become familiar with all scales of device modelling and for many types of device structures, as well as to interact with those top researchers.


Invited speakers' short biographies are given in:



Apart from the technical programme, we include a social program consisting of a Welcome Reception and a Gala Dinner in a nice place in front of the Mediterranean Sea. And I hope you can find some time to walk down Tarragona streets and see its main landmarks, many of them dating back to the Roman Empire. Besides, September 23 is Tarragona Patron Saint Day (“Santa Tecla”), and around that date there will be many nice celebrations and musical performances in the city.

Therefore, I encourage researchers in semiconductor device technology, modeling and circuit design to attend this 8th SINANO Modelling Summer School,a.