Thursday, April 19, 2018

EDS DL MQ Gdynia Maritime University, June 20, 2018, Gdynia, Poland

EDS Distinguished Lecturer Mini-Colloquium
SiC: technology, devices, modeling
Gdynia Maritime University, June 20, 2018, Gdynia, Poland


9:00-9:05
Introduction
Dr. Daniel Tomaszewski, ITE Warsaw, IEEE EDS Member 

9:05-9:50
Lecturer: Dr. Muhammad Nawaz, ABB Corporate Research, Sweden
Title: SiC technology offerings; challenges and opportunities
Abstract: A wide bandgap SiC technology has now entered in transitional phase on various power electronics front; thanks to its superior physical properties such as wide bandgap, larger breakdown field strength, higher carrier saturation velocity, and larger thermal conductivity than that of Si counterpart. Low voltage SiC MOSFET discrete devices and power modules within voltage range of 1.2-1.7 kV are commercially available. On the other side, medium voltage MOSFET devices of 3.3-6.5 kV and high voltage MOSFET devices of 10-15 kV are also visible in the scientific literature with excellent static and dynamic performance, illustrating the potential benefit for high power applications in energy transmission and distribution networks. This talk will focus on the requirement and issues using SiC MOSFETs facing high power applications while addressing simultaneously the potential benefits for high power converters. Reliability concerns from the end user’s perspective will be addressed as well.

10:00-10:45
Lecturer: Prof. Simon Deleonibus, IEEE Fellow, Fellow Electrochemical Society, CEA Research Director
Title: On the way to the Energy and Variability Efficient (E.V.E.) Era
Abstract: Major power consumption reduction will drive future design of technologies and architectures that will request less greedy devices and interconnect systems. The electronic market will be able to face an exponential growth thanks to the availability and feasibility of autonomous and mobile systems necessary to societal needs. The increasing complexity of high volume fabricated systems will be possible if we aim at zero intrinsic variability, and generalize 3-dimensional integration of hybrid, heterogeneous technologies at the device, functional and system levels. Weighing on the world energy saving balance will be possible and realistic by maximizing the energy efficiency of co integrated Low Power and High Performance Logic and Memory devices.The future of Nanoelectronics will face the major concerns of being Energy and Variability Efficient (E.V.E.).

10:55-11:15 Coffee break

11:15-12:00
Lecturer: Prof. Victor Veliadis, IEEE Fellow, Deputy Executive Director and CTO, PowerAmerica; Professor of Electrical and Computer Engineering, North Carolina State University
Title: SiC power device fabrication and path to commercialization
Abstract: The presentation will discuss major SiC power device application areas and touch on foundry models, cost reduction strategies, and path to commercialization. The advantages of SiC over other power electronic materials will be outlined, and SiC devices currently developed for power electronic applications will be introduced. Emphasis will be placed on SiC MOSFETs, which are currently being inserted in the majority of SiC based power electronic systems. Aspects of device fabrication will be given, with stress on processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Finally, the presentation will highlight common SiC Edge Termination techniques, which allow devices to reach their full high-voltage potential.


12:10-12:55
Lecturer: Prof. Henryk M. Przewłocki, IEEE Member, ITE, Warsaw;
Title: The importance of the diffusion currents in the photoelectric investigations of the MIS system
Abstract: The fundamental property of any nanoelectronic material or system is its energy band diagram, which allows to predict its physical properties, potential applications and/or limitations. The most effective methods of band diagram determination are the photoelectric methods, which deserve therefore detailed theoretical analysis, as well as precisely controlled experimental procedures. It is shown in this paper that the commonly accepted and currently applied theory (further called classical theory) of internal photoemission in the metal-insulator-semiconductor (MIS) system, which very well represents its experimental characteristics taken at high enough electric fields E, in the insulator, fails at low electric fields (usually for E<(104-105) V/cm), i.e. in the vicinity of the point where the photocurrent changes sign (I=0). This failure of the classical theory will be demonstrated by comparing the characteristics calculated using the classical theory with the experimental characteristics taken in the range of low electric fields in the insulator. It was already shown some time ago, by the present author that this discrepancy results from the neglect of the diffusion currents, which become important at low electric fields in the insulator. In this paper the origin, the magnitude and the role of diffusion current in determination of the MIS system photoelectric characteristics at low electric fields in the insulator will be quantitatively analyzed. The theory of the photocurrent vs. gate voltage characteristics, at different wavelengths of light illuminating the structure under test, with diffusion currents taken into account will be presented. It will be shown that characteristics calculated using this theory remain in good agreement with the relevant experimental characteristics. The ability to accurately predict these characteristics in the range of low electric fields opens the possibilities of developing new measurement methods of the MIS system crucial parameters. Examples of such methods will be demonstrated.

13:05-14:05 Lunch Break

14:05-14:50
Lecturer: Prof. Mike Brinson, Centre for Communications Technology, London Metropolitan University
Title: Verilog-A compact modelling of SiC devices with Qucs-S, QucsStudio and MAPP/Octave FOSS tools
Abstract: The purpose of this presentation is provide an overview of the fundamentals of the Verilog-A hardware description language and its use in compact modelling of established and emerging semiconductor technology devices. With the adoption of Verilog-A as the standardised model interchange language by CMC, a knowledge of this subject is of increasing importance to the modelling community. Similarly, access to freely available Verilog-A modelling tools and circuit simulators is essential if Verilog-A modelling techniques are to be widely adopted. For this reason, in an attempt to encouraging all who attend to experiment with Verilog-A. the presentation is based on the Qucs-S, QucsStudio and the MAPP/Octave FOSS software. Throughout the talk a series of modelling case studies outline the stages in the development of Verilog-A models for established and SiC semiconductor devices. In the later stages of the presentation participants are also introduced to using the Berkeley MAPP tools with Qucs-S/Xyce.

15:00-15:45
Lecturer: Dr. Wladek Grabinski, IEEE EDS Senior Member, MOS-AK (EU);
Title: FOSS TCAD/EDA Tools for Advanced Compact Modeling
Abstract: Compact/SPICE models of circuit elements (passive, active, MEMS, RF) are essential to enable advanced IC design using nanoscaled semiconductor technologies. Compact/SPICE models are also a communication means between the semiconductor foundries and the IC design teams to share and exchange all engineering and design information. To explore all related interactions, we are discussing selected FOSS CAD tools along complete technology/design tool chain from nanascaled technology processes; thru the MOSFET, FDSOI, FinFET and TFET compact modeling; to advanced IC transistor level design support. New technology and device development will be illustrated by application examples of the FOSS TCAD tools: Cogenda TCAD and DEVSIM. Compact modeling will be highlighted by review topics related to its parameter extraction and standardization of the experimental and measurement data exchange formats. Finally, we will present two FOSS CAD simulation and design tools: ngspice and Qucs. Application and use of these tools for advanced IC design (e.g. analog/RF IC applications) directly depends the quality of the compact models implementations in these tools as well as reliability of extracted models and generated libraries/PDKs. Discussing new model implementation into the FOSS CAD tools (Gnucap, Xyce, ngspice and Qucs as well as others) we will also address an open question of the compact/SPICE model Verilog-A standardization. We hope that this presentation will be useful to all the researchers and engineers actively involved in the developing compact/SPICE models as well as designing the integrated circuits in particular at the transistor level and then trigger further discussion on the compact/SPICE model Verilog-A standardization and development supporting FOSS CAD tools.

15:55 End of MQ

Wednesday, April 18, 2018

Semianalytical #modeling of the depletion layers and their effects on the #threshold #voltage of a #junctionless double‐gate MOSFET including trapped charges - Beigi - - IJNM - Wiley Online Library https://t.co/P6T6PSop2t https://t.co/P6T6PSop2t


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April 17, 2018 at 11:16PM
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Tuesday, April 17, 2018

A scalable and multibias #parameter #extraction method for a small‐signal GaN HEMT #model - Chen - - International Journal of Numerical Modelling: Electronic Networks, Devices and Fields - Wiley Online Library https://t.co/qStCsViVKt https://t.co/qStCsViVKt


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April 17, 2018 at 10:20PM
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#Graphene is Grown With the Same Band Gap as #Silicon - IEEE Spectrum #paper https://t.co/Cxv8s8DKef


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April 16, 2018 at 10:36PM
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Saturday, April 14, 2018

A new approach to the extraction of single exponential diode #model parameters https://t.co/qc5i9xwEwK


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April 14, 2018 at 03:33PM
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Friday, April 13, 2018

Using #opensource Designs to Create More Specialized #IC. RISC-V wants to do for chips what Linux did for software. https://t.co/M9iVOgdb7k https://t.co/JyDdsDs7Pb https://t.co/VrKNjBxkmt


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April 13, 2018 at 04:30PM
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Tuesday, April 3, 2018

[mos-ak] [2nd Announcement and Call for Papers] 3rd Sino MOS-AK Workshop Peking, June 14-16 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
3rd Sino MOS-AK Workshop
Peking, June 14-16 2018

Together with the Honorary Committee Chair, Yan Wang, Tsinghua Universitylocal organization team and International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 3rd Sino MOS-AK Compact/SPICE Modeling Workshop which will be organized at Tsinghua University between June 14-16, 2018.

Planned 3rd Sino MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue
会议场所:清华大学FIT-楼,在紫光国际国际交流中心旁
Tsinghua University FIT building, close to Tsinghua Unisplendour International Center

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:
  • Compact Modeling (CM) of the electron devices
  • Advances in semiconductor technologies and processing
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, TFT, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and reliability/ageing IC Designs
  • Foundry/Fabless Interface Strategies
SpeakersInvited talks tentative listing (alphabetic order)
  • Prof. Mansun Chan; Compact Models for Giga-Scale Memory System
  • Dr. Axel Huelsmann; mHEMT based MMICs, Modules, and Systems for mmWave Applications
  • Dr.-Ing. Franz Sischka; Successful and Verified RF Measurements for Device Modeling
  • Dr. Lifeng Wu; A Full Design Flow Solution for OLED Flat Panel Display
  • Dr. Pete Zampardi; Understanding Gaps in III-V HBT Modeling and Simulation
Important Dates: 
  • Call for Papers - March 2018
  • 2nd Announcement - April 2018
  • Final Workshop Program - May 2018
  • MOS-AK Workshop - June 14-16 2018
    • Day 1: MOS-AK Tutorial Day
    • Day 2: MOS-AK SPICE/Verilog-A Modeling Workshop
    • Day 3: MOS-AK SPICE/Verilog-A Modeling Workshop
Online Abstract Submission is open 
(any related enquiries can be sent to abstract@mos-ak.org)
Manuscript submission deadline: 28th May 2018 (Monday)
Notification of Acceptance: 4th June 2018 (Monday)
Submission of final manuscript: 11th June 2018 (Monday)

Online Workshop Registration is open 
(any related enquiries can be sent to registration@mos-ak.org)

Postworkshop IJHSES Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

International MOS-AK Committee:
  • Honorary Committee Chair
    • Yan Wang, Tsinghua University
  • Advisory Committee
    • George Ponchak, T-MTT Editor
    • Yuhua Cheng, PKU
  • Organizing Committee General Co-Chairs:
    • Min Zhang, XMOD Technologies
    • Wladek Grabinski, MOS-AK (EU)
  • Finance Chair:
    • Li Zhang, Tsinghua University
  • Publication Chair: 
    • Wladek Grabinski, MOS-AK (EU)
  • Awards Committee Chair:
    • Zhiping Yu, Stanford University
  • Sponsorship Chair:
    • Li Zhang, Tsinghua University
    • Min Zhang, XMOD Technologies
  • Exhibition Chair:
    • Jin Chen, SIMIT
    • Kai Lv, NUS
  • Local Arrangements Chair:
    • Wenfei Hu, Tsinghua University
  • Publicity:
    • Sen Yin, Tsinghua  University
  • Workshop Secretary:
    • Li Zhang
    • Office: +86 010 62771733; 
    • Mobile: +86 138 01302877
    • Email: zhangli95@tsinghua.edu.cn
Extended MOS-AK Committee
WG03043018

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(NEW DEADLINE: 10 APRIL) ESSDERC Call for Papers

Call for Papers 
(NEW DEADLINE: 10 APRIL

PAPER SUBMISSION: Manuscript guidelines as well as instructions on how to submit electronically ARE AVAILABLE HERE. Papers must not exceed four A4 pages with all illustrations and references included. All submissions must be received by (NEW DEADLINE): 10 APRIL

Papers submitted for review must clearly state:

  • The purpose of the work
  • How and to what extent it advances the state-of-the-art
  • Specific results and their impact

Only work that has not been previously published or submitted elsewhere will be considered. Submission of a paper for review and subsequent acceptance is considered as a commitment that the work will not be publicly available prior to the conference [read more...]

Wednesday, March 28, 2018

Monday, March 26, 2018

Tissue #paper #sensors show promise for health care, entertainment, robotics https://t.co/PssD62ihrx https://t.co/vY0eG5ik5N


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March 26, 2018 at 11:31AM
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Compact #Modeling of Proximity Effect in High- ${Q}$ Tapered Spiral Inductors - IEEE Journals & Magazine https://t.co/dsVW3ux2UJ https://t.co/dsVW3ux2UJ


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March 25, 2018 at 11:40PM
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Saturday, March 24, 2018

Modeling Nanowire and Double-Gate Junctionless Field-Effect Transistors by F. Jazaeri and J.-M. Sallese https://t.co/YYHqopRbzX #paper https://t.co/L7D2Zlrhg6 https://t.co/glgZxWJ6qC


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March 24, 2018 at 04:06PM
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#paper: " #Circuit #aging has become a real reliability concern, because it leads to an increase in transistor threshold voltage that may cause timing errors as a result of higher delays in critical paths” https://t.co/CSbMZ94Yrg https://t.co/CSbMZ94Yrg


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March 24, 2018 at 02:21PM
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#AR2 6 axis #robot is an #opensource platform https://t.co/Xf4WRoy8cx https://t.co/jb0c3bzxIf


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March 24, 2018 at 01:31PM
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Anomalous #CV Inversion in #TSVs: The Problem and Its #Cure #paper https://t.co/meiOoj9ulj


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March 24, 2018 at 11:25AM
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Thursday, March 22, 2018

[mos-ak] [press note] Spring'18 MOS-AK Workshop in Munich on March 13, 2018

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
Spring'18 MOS-AK Workshop
Munich, March 13, 2018


The MOS-AK Compact Modeling Association, a global compact/SPICE modeling and Verilog-A standardization forum, held its Spring compact/SPICE workshop in Munich. The event was hosted on March 13, 2018, by Infineon Technologies AG in Neubiberg. The technical program of the event was coordination by Klaus-Willi Pieper, Infineon, and the MOS-AK TPC Committee. The workshop has received full industrial sponsorship by Infineon Technologies AG (lead sponsor) with technical program promotion provided by ASCENT NetworkKeysight TechnologiesIJHSES as well as NEEDS of nanoHUB.org

The MOS-AK workshop was opened by Klaus-Willi Pieper, Principal Compact Modeling Smart Power Devices at Infineon, who has welcomed all the attendees and shared Infineon view on the compact modeling and its importance in the TCAD/EDA modeling/design ecosystem. 

A group of 40+ international academic researchers and modeling engineers attended 10 technical compact modeling presentations covering full development chain from the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. The event featured advanced technical presentations covering compact model development, implementation, deployment and standardization covering full engineering R&D chain: TCAD/processing, device modeling, transistor level IC design support. These contributions were delivered by leading academic and industrial experts, including: [1] Klaus-Willi Pieper, Overview of the Compact Modeling at Infineon; [2] James Ma et al, Advanced Fast on-wafer Low-frequency Noise Measurement with High Resolution, Wide Bandwidth and Large Biasing Current Range; [3] Volker Gloeckel, Advances in Statistical Compact Modeling; [4] Markus Becherer, et al, Compact Modeling of Nanomagnetic Logic Devices and Circuits; [5] Gražvydas Žiemys, Devices for Nanomagnetic Logic; [6] Paul Roseingrave, Modelling Emerging Devices through EU ASCENT Network; [7] Jushan Xie, How Is CMC Standard Model Implemented and Verified In Simulator?; [8] Maria Cotorogea et al, Virtual Prototyping for Power Diode and IGBT Development; [9] Franz Sischka, et al, Modeling of Device Aging - Example: Diode; [10] Katja Puschkarsky, Device Aging Simulations Enabling Circuit Optimizations; [11] Fabio A. Velarde Gonzalez, Integration of Aging Models Across Different EDA Environments A case study implementing HCI and NBTI models for X-FAB XU035 CMOS technology; During complementary MOS-AK Panel Discussion on Compact Model Licensing Peter Lee, CMC Chair highlighted current status of the CMC compact model licensing status, stating that final discussions are converging to establish official licensing in the next few months. All the presentations are available online for download at <http://www.mos-ak.org/munich_2018/>. Selected best presentation will be recommended for further publication in the IJHSES.

The MOS-AK, international compact modeling association, has various deliverables and initiatives including a book entitled "Open Source TCAD/EDA Tools for Compact Modeling" and open Verilog-A model directory with supporting FOSS TCAD/EDA tools. The MOS-AK Association plans to continue its standardization efforts by organizing future compact modeling meetings, workshops and courses in Europe, USA, China and India throughout coming 2018/2019 years, including:

About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common information exchange system among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools including FOSS for the compact/SPICE models development, validation/implementation and distribution. For more information please visit: mos-ak.org

About  Infineon Technologies AG:
Infineon designs, develops, manufactures and markets a broad range of semiconductors and system solutions. The focus of its activities is on automotive electronics, industrial electronics, RF applications, mobile devices and hardware-based security. Combining entrepreneurial success with responsible action, at Infineon we make the world easier, safer and greener. Barely visible, semiconductors have become an indispensable part of our daily lives. Infineon's components play an essential role wherever electric energy is generated, transmitted and used efficiently. Furthermore, they safeguard data communication, improve safety on roads and reduce automotive emissions. Product range includes:
  • Automotive: 32-bit automotive microcontrollers for powertrain, safety and driver assistance systems, discrete power semiconductors, IGBT modules, industrial microcontrollers, magnetic and pressure sensors, power ICs, radar sensor ICs (77 GHz), transceivers (CAN, LIN, Ethernet, FlexRay), voltage regulators
  • Industrial Power Control: bare die business, discrete IGBTs, driver ICs, IGBT modules (low-power, medium-power, high-power), IGBT module solutions incl. IGBT stacks, silicon carbide modules
  • Power Management & Multimarket: control ICs, customized chips (ASICs), discrete low-voltage and high-voltage power MOSFETs, gallium nitride (GaN) transistors, GPS low-noise amplifiers, low-voltage and high-voltage driver ICs, MEMS and ASICs for silicon microphones, pressure sensors, radar sensor ICs (24 GHz, 60 GHz), RF antenna switches, TVS (transient voltage suppressor) diodes
  • Chip Card & Security: contact-based security controllers, contactless security controllers, dual-interface security controllers (contact-based and contactless), embedded security controllers
Presence: 36 research and development locations, 18 manufacturing locations and about 44 sales offices worldwide

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Capacitive #RF #MEMS switch design and simulation https://t.co/z6KeAsfzac #Modeling https://t.co/GeegWnsUDG


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March 22, 2018 at 10:48AM
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Thursday, March 15, 2018

#GNU #Octave 4.2.2 #Released https://t.co/rVdmPblrKc #opensource


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March 15, 2018 at 10:16PM
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#Intel #opensource Sound Firmware, Pushing For More Open Firmware - Phoronix https://t.co/xKeyG4ZptG


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March 15, 2018 at 10:14PM
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Si2 Approves IC Design Simulation Standards for Gallium Nitride Devices https://t.co/Paz8lLEngY #Modeling https://t.co/XfGGQtef4f


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March 15, 2018 at 08:44AM
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Tuesday, March 13, 2018

Time for '#OpenInnovation,' Not Just #OpenSource https://t.co/zUuvSHl2EE


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March 13, 2018 at 07:46PM
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Monday, March 12, 2018

Friday, March 9, 2018

[1889 reeds] Open-source circuit simulation tools for RF compact semiconductor device #modeling https://t.co/OeqgG1ChLD


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March 09, 2018 at 10:30AM
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Tuesday, March 6, 2018

Experimental Observation and Simulation #Model for Transient Characteristics of Negative-Capacitance in... https://t.co/Q73Mvkixlp


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March 06, 2018 at 02:31PM
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Experimental Observation and Simulation #Model for Transient Characteristics of Negative-Capacitance in Ferroelectric HfZrO2 Capacitor https://t.co/ijwoKP4zCM


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March 06, 2018 at 02:31PM
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ENBIOS-2D Lab

Aldi Hoxha1, Paolo Scarbolo1, Andrea Cossettini2, Federico Pittino3, Luca Selmi4
1. DPIA, Università degli Studi di Udine 2. University of Udine 3. Università di Udine 4
DPIA, Università degli Studi di Udine, Italy

Abstract: ENBIOS-2D Lab is a tool to illustrate and to study simple Ion Sensitive Field Effect Transistor structures in two dimensions. Together with its companion tool ENBIOS-1D Lab, it is meant for use as a teaching tool in support of undergraduate or graduate courses on the basic physics of transduction in ion and particle sensors, and to assist early stage researchers getting familiar with some basic concepts in the field. At the present stage, ENBIOS-2D Lab supports simulation and visualization of DC I-V characteristics, impedance/admittance spectra as well as DC and AC potential/carrier/ion distributions in simple two-dimensional ISFET structures. A broader set of case studies will become available with future releases of the tool. The companion ENBIOS-1D Lab tool offers the possibility to simulate simple Electrolyte/Insulator/Semiconductor systems in one-dimension. The physical system is modelled with the Poisson/Boltzmann (DC) and Poisson/Nernst/Planck - Poisson/Drift/Diffusion (AC small signal) equations coupled to the site-binding charge model equations at the Electrolyte/Insulator interfaces. Dedicated models are implemented for the frequency and salinity dependence of the electrolyte electrical permittivity and the temperature dependence of the ions' mobility (in water solvent). ENBIOS-2D Lab is powered by ENBIOS, (Electronic Nano-BIOsensor Simulator), a general purpose three-dimensional Control Volume Finite Element Method (CVFEM) simulator developed in-house at the University of Udine - Italy. ENBIOS simulates in three dimensions (3D) the DC and AC small signal impedance response to ions and micro/nanoparticles of three-dimensional devices made of semiconductor, insulator and electrolyte materials.
References:

[1] P. Scarbolo, E. Accastelli, F. Pittino, T. Ernst, C. Guiducci, L. Selmi, “Characterization and modelling of differential sensitivity of nanoribbon-based pH-sensors”, Proceedings of the 2015 Transducers - 18th International Conference on Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), 21-25 June 2015, pp. 2188-2191

[2] Paolo Scarbolo, Enrico Accastelli, Thomas Ernst, Carlotta Guiducci and Luca Selmi, "Analysis of Dielectric Microbead Detection by Impedance Spectroscopy with Nanoribbons", IEEE Nano Conference, August 2016.

[3] Federico Pittino and Luca Selmi, "Use and comparative assessment of the CVFEM method for Poisson–Boltzmann and Poisson–Nernst–Planck three dimensional simulations of impedimetric nano-biosensors operated in the DC and AC small signal regimes", Comput. Methods Appl. Mech. Engrg., v.278, (2014), pp.902–923.


Sunday, March 4, 2018

A New Analytical Pinned Photodiode Capacitance #Model - IEEE Journals & Magazine https://t.co/3IiJn8I4MH https://t.co/1Hea8LzBUn


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March 04, 2018 at 12:45PM
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A New Analytical Pinned Photodiode Capacitance #Model - IEEE Journals & Magazine https://t.co/3IiJn8I4MH


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March 04, 2018 at 12:45PM
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Friday, March 2, 2018

[paper] Compact modeling of SiC Schottky barrier diode and its extension to junction barrier Schottky diode

Dondee Navarro1, Fernando Herrera1, Hiroshi Zenitani2, Mitiko Miura-Mattausch1, Naoto Yorino2, Hans Jürgen Mattausch1,2, Mamoru Takusagawa3, Jun Kobayashi3 and Masafumi Hara3

Published 19 February 2018 • © 2018 The Japan Society of Applied Physics
Japanese Journal of Applied Physics, Volume 57, Number 4S

1 HiSIM Research Center, Hiroshima University, Hiroshima 739-8530, Japan
2 Graduate School of Engineering, Hiroshima University, Hiroshima 739-8530, Japan
3 Toyota Motor Corporation, Toyota, Aichi 470-0309, Japan

Abstract: A compact model applicable for both Schottky barrier diode (SBD) and junction barrier Schottky diode (JBS) structures is developed. The SBD model considers the current due to thermionic emission in the metal/semiconductor junction together with the resistance of the lightly doped drift layer. Extension of the SBD model to JBS is accomplished by modeling the distributed resistance induced by the p+ implant developed for minimizing the leakage current at reverse bias. Only the geometrical features of the p+ implant are necessary to model the distributed resistance. Reproduction of 4H-SiC SBD and JBS current–voltage characteristics with the developed compact model are validated against two-dimensional (2D) device-simulation results as well as measurements at different temperatures [read more: https://doi.org/10.7567/JJAP.57.04FR03]

Fig.: Electron current density in a JBS cross-section. JBS has a peak density at the n− region adjacent to the p+ implant.



Wednesday, February 28, 2018

[paper] Compact electro-thermal modeling of a SiC MOSFET power module under short-circuit conditions

Proceedings of 43rd Annual Conference of the IEEE Industrial Electronics Society
IECON 2017
Lorenzo Ceccarelli, Paula Diaz Reigosa, Amir Sajjad Bahman, Francesco Iannuzzo,
Frede Blaabjerg
Center of Reliable Power Electronics, Department of Energy Technology Aalborg University,
Pontoppidanstræde 101
9220 Aalborg, Denmark 

ABSTRACT: A novel physics-based, electro-thermal model which is capable of estimating accurately the short-circuit behavior and thermal instabilities of silicon carbide MOSFET multi-chip power modules is proposed in this paper. The model has been implemented in PSpice and describes the internal structure of the module, including stray elements in the multi-chip layout, self-heating effect, drain leakage current and threshold voltage mismatch. A lumped-parameter thermal network is extracted in order to estimate the internal temperature of the chips. The case study is a half-bridge power module from CREE with 1.2 kV breakdown voltage and about 300 A rated current. The short-circuit behavior of the module is investigated experimentally through a non-destructive test setup and the model is validated. The estimation of overcurrent and temperature distribution among the chips can provide useful information for the reliability assessment and fault-mode analysis of a new-generation SiC high-power modules [read more...]

Fig.: SiC MOSFET model structure. 

Sunday, February 25, 2018

Call for papers for a Special Issue of IEEE Transactions on Electron Devices on Compact #Modeling for Circuit... https://t.co/N6U0dXHmu1


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February 25, 2018 at 10:48AM
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Call for papers for a Special Issue of IEEE Transactions on Electron Devices on Compact #Modeling for Circuit Design - IEEE Journals & Magazine https://t.co/MNRwd2XitA


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February 25, 2018 at 10:48AM
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Compact #Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition - IEEE Journals &... https://t.co/xp2Ff5Tlcp


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February 25, 2018 at 12:17AM
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Compact #Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition - IEEE Journals & Magazine https://t.co/yTSpsNriwQ


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February 25, 2018 at 12:17AM
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Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the... https://t.co/RBNC96OpbO


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February 25, 2018 at 12:10AM
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Large-Signal Static Compact Circuit #Model of SiGe Heterojunction Bipolar Phototransistors: Effect of the Distributed Nature of Currents - IEEE Journals & Magazine https://t.co/wNNqfPzf0P


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February 25, 2018 at 12:10AM
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Saturday, February 24, 2018

Extraction of Process Variation Parameters in FinFET Technology Based on Compact #Modeling and Characterization https://t.co/1RTYdSlig5


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February 24, 2018 at 12:38PM
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Friday, February 23, 2018

#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin... https://t.co/xKqgbSKTJs


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February 23, 2018 at 04:08PM
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#paper : On the Formulation of Self-heating Models for Circuit Simulation Lining Zhang, Member, IEEE, Debin Song, Ying Xiao, Xinnan Lin, Mansun Chan, Fellow, IEEE https://t.co/yNcMnQarbw


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February 23, 2018 at 04:08PM
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[Short Course] RFSOI: from basics to practical use of wireless technology

RFSOI: from basics to practical use of wireless technology

18th of March, Granada, Spain
LLN
  
Incize organizes a one-day short course at EuroSOI-ULIS about Silicon-on-Insulator (SOI) technology for RF applications. The tutorial is given by globally recognized experts in the field. It aims to provide its participants with the knowledge about SOI materials, devices, circuits and performance.

  
The Silicon-on-Insulator (SOI) technology is gaining more grounds in the domains of RF applications. Nearly 100% of RF antenna switches in wireless system Front-End Modules (FEM) are based on SOI. A FEM entirely built on SOI can be implemented in the observable future as both academia and industry are working in this direction.

  
This tutorial will be of interest for engineers and graduate students willing to prepare themselves for the future RF applications.

Program:Sunday, March 18
08:00 – 08:50RF SOI, fabrication, materials and eco-system
(Abstract)
Ionut Radu
Director of Advanced R&D
Soitec, France
Ionut Radu
08:50 – 09:40Fundamentals of RF SOI technology(Abstract)Jean-Pierre Raskin
Professor
UCL, Belgium
Jean-Pierre
09:40 – 10:10Break
10:10 – 11:0022nm FDSOI Technology optimized 
for RF/mmWave Applications
 (Abstract)
David L. Harame
RF CTO Development and Enablement
GlobalFoundries, Germany
David L. Harame
11:00 – 11:50RF SOI technology and components for 5G connectivityChristine Raynaud
Program Manager (Business Development – Technology to Design)
CEA-Leti, France
Christine Raynaud
11:50 – 13:30Lunch
13:30 – 14:20Analog and RF design on SOI (Abstract)Barend van Liempd
Senior Researcher
imec, Belgium
Barend van Liempd
14:20 – 15:10Techniques and tricks for RF measurements on SOI Andrej Rumiantsev
Director RF Technologies
MPI Corporation, Germany
Andrej Rumiantsev
15:10 – 15:40Break
15:40 – 16:30FOSS TCAD/EDA tools for advanced 
SOI-device modeling
 (Abstract)
Wladek Grabinski
R&D CM Manager
MOS-AK, Switzerland
Wladek Grabinski
16:30 – 17:20RF design flow for SOIIan Dennison
Design Systems Senior Group Director
Cadence, UK
Ian Dennison


To register, please use the EuroSOI-ULIS registration website

More information about the EuroSOI-ULIS conference and the technical Program


For any inquiries please email us at info@incize.com
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