Sunday, May 31, 2020

#DISLIN Graphics Library to plot S- and Y-parameters on Smith Charts, and to create arbitrary Cartesian plots of S-parameter data along with Polar plots of radiation patterns. #paper

from Twitter

May 31, 2020 at 09:55PM

[paper] ReRAM: History, Status, and Future

ReRAM: History, Status, and Future
Y. Chen, Member, IEEE
Western Digital Corporation, Milpitas, CA
in IEEE TED, vol. 67, no. 4, pp. 1420-1433, April 2020
doi: 10.1109/TED.2019.2961505.

Abstract: This article reviews the resistive random-access memory (ReRAM) technology initialization back in the 1960s and its heavily focused research and development from the early 2000s. This review goes through various oxygen/oxygen vacancy and metal-ion-based ReRAM devices and their operation mechanisms. This review also benchmarks the performance of various oxygen/oxygen vacancy and metal-ion-based ReRAM devices with general trend drawn. Being a semiconductor memory and storage technology, the commercialization attempts for both stand-alone mass storage/storage-class memory and embedded nonvolatile memory are also reviewed. Looking toward the coming era, the potential of using ReRAM technology to improve machine learning efficiency is discussed. 
Fig: General category of resistive switching memory technologies
with ReRAM highlighted as the review focus

Acknowledgment: Sincere acknowledgment to people who ever contribute to ReRAM technology development and understanding.


Friday, May 29, 2020

What Rhymes With #SPICE And Simulates Huge Circuits? #paper

from Twitter

May 29, 2020 at 03:58PM

Open PhD and Post-Doc positions at BIU

Dr. Adam Teman is a tenure track Senior Lecturer at Bar-Ilan University in Ramat Gan, Israel and a leading member of the Emerging Nanoscaled Circuits and Systems (EnICS) Labs at BIU. Dr.Temen is also among  the Woolf Foundation's 2020 Krill Award winners for young Israeli researchers. Dr.Teman is looking now for candidates for PhD and Post-Doc positions. Please contact him at 

Dr. Adam Teman Research IC Tapeouts
  • 2019 - SoC2 System-on-Chip (TSMC 16FFC)
  • 2018 - Kwak Gain Cell eDRAM T(Samsung 28nm FD-SOI)
  • 2017 - Martini Gain Cell eDRAM (ST 28nm FD-SOI)
  • 2016 - BEER Gain Cell eDRAM (ST 28nm FD-SOI)
  • 2016 - DAFNA Gain Cell eDRAM (TSMC 28nm)

Wednesday, May 27, 2020

Tuesday, May 26, 2020

#EU and #Japan step up cooperation in #science, #technology and innovation #Paper

from Twitter

May 26, 2020 at 05:32PM

[paper] InAs-OI-Si MOSFET Compact Model

S. K. Maity, A. Haque and S. Pandit
Charge-Based Compact Drain Current Modeling of InAs-OI-Si MOSFET 
Including Subband Energies and Band Nonparabolicity
in IEEE TED, vol. 67, no. 6, pp. 2282-2289, June 2020
doi: 10.1109/TED.2020.2984578

Abstract: In this article, we report a physics-based compact model of drain current for InAs-on-insulator MOSFETs. The quantum confinement effect has been incorporated in the proposed model by solving the 1-D Schrödinger–Poisson equations without using any empirical model parameter. The model accurately captures the variation of surface potential, charge density in the inversion layer, and subband energy levels with gate bias inside the quantum well. The conduction-band nonparabolicity effect on modification in eigen energy, effective mass, and density of states is derived and incorporated into the proposed model. The velocity overshoot effect that originates from the quasi-ballistic nature of carrier transport is also considered in the model. The proposed drain current model has been implemented in Verilog-A to use in the SPICE environment. The model predicted results are in good agreement with the commercial device simulator results and experimental data. 
Fig: Energy band profile of InAs-OI-Si MOSFET in the direction perpendicular to the oxide interface at flat-band condition. E0 and E1 denote the first and the second subband energy levels, respectively, and ΔEc and Vox represent the conduction-band offset between buffer-channel and oxide-channel regions, respectively.

Acknowledgment: The author S. Pandit would like to thank the Department of Electronics and Information Technology, Government of India for utilizing the resources obtained under the SMDP-C2SD Project at the University of Calcutta.


Open PhD Positions In The Eu-Funded Project "GREAT". Currently, there are still vacancies in Germany and France. You can find more information at: AMO GmbH | #paper

from Twitter

May 26, 2020 at 09:19AM

Monday, May 25, 2020

[paper] Organic Transistor Memory Based on Black Phosphorus Quantum Dots

P. Kumari, J. Ko, V. R. Rao, S. Mhaisalkar and W. L. Leong
Non-Volatile Organic Transistor Memory Based on Black Phosphorus Quantum Dots as Charge Trapping Layer,
in IEEE Electron Device Letters, vol. 41, no. 6, pp. 852-855, June 2020
doi: 10.1109/LED.2020.2991157

Abstract: High performance organic nano-floating gate transistor memory (NFGTM) has important prerequisites of low processing temperature, solution–processable layers and charge trapping medium with high storage capacity. We demonstrate organic NFGTM using black phosphorus quantum dots (BPQDs) as a charge trapping medium by simple spin-coating and low processing temperature ( 120 °C). The BPQDs with diameter of 12.6 ± 1.5 nm and large quantum confined bandgap of ~2.9 eV possess good charge trapping ability. The organic memory device exhibits excellent memory performance with a large memory window of 61.3 V, write-read-erase-read cycling endurance of 10 3 for more than 180 cycles and reliable retention over 10,000 sec. In addition, we successfully improved the memory retention to ON/OFF current ratio 10E4 over 10,000 sec by introducing PMMA as the tunneling layer.
FIG: a.) Schematic of bottom gate top contact NFGTM device; b.) Band diagram explaining memory mechanism under positive gate bias 

Acknowledgement: W.L. Leong would like to acknowledge funding support from her NTU start-up grant (M4081866), Ministry of Education (MOE) under AcRF Tier 1 grant (2016-T1-002- 097), Tier 2 grant (2018-T2-1-075), ASTAR AME IAF-ICP Grant (No.I1801E0030) and A*STAR AME Young Individual Research Grant (Project No. A1784c019).

[paper] IoT Vision empowered by EH-MEMS and RF-MEMS

Internet of things (IoT); internet of everything (IoE); tactile internet; 5G
A (not so evanescent) unifying vision empowered 
by EH-MEMS (energy harvesting MEMS) and RF-MEMS (radio frequency MEMS)
 Jacopo Iannacci
Fondazione Bruno Kessler (FBK) in Trento (IT)
Sensors and Actuators A: Physical 272 (2018): 187-198

Abstract: This work aims to build inclusive vision of the Internet of Things (IoT), Internet of Everything (IoE), Tactile Internet and 5G, leveraging on MEMS technology, with focus on Energy Harvesters (EH-MEMS) and Radio Frequency passives (RF-MEMS). The IoT is described, stressing the pervasivity of sensing/actuating functions. High-level performances 5G will have to score are reported. Unifying vision of the mentioned paradigms is then built. The IoT evolves into the IoE by overtaking the concept of thing. Further step to Tactile Internet requires significant reduction in latency, it being enabled by 5G.

The discussion then moves closer to the hardware components level. Sets of specifications driven by IoT and 5G applications are derived. Concerning the former, the attention is concentrated on typical power requirements imposed by remote wireless sensing nodes. Regarding the latter, a set of reference specifications RF passives will have to meet in order to enable 5G is developed. Once quantitative targets are set, a brief state of the art of EH-MEMS and RF-MEMS solutions is developed, targeting the IoT and 5G, respectively. In both scenarios, it will be demonstrated that MEMS are able to address the requirements previously listed, concerning EH from various sources and RF passive components.
FIG: Scheme of the pillar drivers supporting evolution of the IoT into IoE andTactile Internet.
Some relevant IoT technology enablers are indicated.
In conclusion, the frame of reference depicted in this work outlines a relevant potential borne by EH-MEMS and RF-MEMS solutions within the unified scenario of IoT, IoE, Tactile Internet and 5G, making the forecast of future relentless growth of MEMS-based devices, more plausible and likely to take place.

[paper] SPICE PCM Model

A SPICE Model of Phase Change Memory for Neuromorphic Circuits
Xuhui Chen1, Huifang Hu1, Xiaoqing Huang1, Weiran Cai2, Ming Liu3 (Fellow, Ieee), Chung Lam4,  Xinnan Lin1 (Member, IEEE), Lining Zhang5 (Senior Member, IEEE)
and Mansun Chan6 (Fellow, IEEE)
1The Shenzhen Key Lab of Advanced Electron Device and Integration, ECE, Peking University Shenzhen Graduate School, Shenzhen 518055 CN
2Institute of Microscale Optoelectronics, Shenzhen University, Shenzhen 518061 CN
3Key Laboratory of Microelectronics Devices and Integration Technology, Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, and the University of Chinese Academy of Sciences, Beijing 100049 CN
4Jiangsu Advanced Memory Technology Co., Ltd, Huaian 223302 CN
5School of Electronic and Computer Engineering, Peking University, Shenzhen 518055, CN
6HKUST Shenzhen Research Institute, Shenzhen 518057, China, and Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, HK

doi: 10.1109/ACCESS.2020.2995907

Abstract: A phase change memory (PCM) model suitable for neuromorphic circuit simulations is developed. A crystallization ratio module is used to track the memory state in the SET process, and an active region radius module is developed to track the continuously varying amorphous region in the RESET process. To converge the simulations with bi-stable memory states, a predictive filament module is proposed using a previous state in iterations of nonlinear circuit matrix under a voltage-driven mode. Both DC and transient analysis are successfully converged in circuits with voltage sources. The spiking-timedependent- plasticity (STDP) characteristics essential for synaptic PCM are successfully reproduced with SPICE simulations verifying the model’s promising applications in neuromorphic circuit designs. Further on, the developed PCM model is applied to propose a neuron circuit topology with lateral inhibitions which is more bionic and capable of distinguishing fuzzy memories. Finally, unsupervised learning of handwritten digits on neuromorphic circuits is simulated to verify the integrity of models in a large-scale-integration circuits. For the first time in literature an emerging memory model is developed and applied successfully in neuromorphic circuit designs, and the model is applicable to flexible designs of neuron circuits for further performance improvements. 
FIG: Schematic diagram of commonly used PCM mushroom structure

[paper] Graphene/4H-SiC/Graphene MSM UV-photodetector

An optimized Graphene/4H-SiC/Graphene MSM UV-photodetector operating
in a wide range of temperature 
H. Bencherif 1, L. Dehimi1 2, G. Messina 3, P. Vincent 4, F. Pezzimenti 3, F. G. Della Corte 3 1Laboratory of Metallic and Semiconductor Materials, University of Biskra, Biskra, DZ
2Faculty of Science, University of Batna 1, DZ
3DIIES, Mediterranea University of Reggio Calabria, Reggio Calabria, IT
4School of Electronics Engineering, KNU, 80 Daehakro, Buk-gu, Daegu, 702-701, KP

Abstract: In this paper, .an accurate analytical model has been developed to optimize the performance of an Interdigitated Graphene Electrode/p-silicon carbide (IGE/p-4H-SiC) Metal semiconductor Metal (MSM) photodetector operating in a wide range of temperatures. The proposed model considers different carrier loss mechanisms and can reproduce the experimental results well. An overall assessment of the electrodes geometrical parameters’ influence on the device sensitivity and speed performances was executed. Our results confirm the excellent ability of the suggested Graphene electrode system to decrease the unwanted shadowing effect. A responsivity of 238 μA/W was obtained under 325-nm illumination compared to the 16.7 μA/W for the conventional Cr-Pd/p-SiC PD. A photocurrent to- dark-current ratio (PDCR) of 5.75 × 105 at 300K and 270 at 500K was distinguished. The response time was found to be around 14 μs at 300K and 54.5 μs at 500K. Furthermore, the developed model serves as a fitness function for the multi objective optimization (MOGA) approach. The optimized IGE/p-4H-SiC MSM-PD design not only exhibits higher performance in terms of PDCR (7.2×105), responsivity (430A/cm2) and detectivity (1.3×1014 Jones) but also balances the compromise between ultrasensitive and high-speed figures of merit with a response time of 4.7 μs. Therefore, the proposed methodology permits to realize ultra-sensitive, high-speed SiC optoelectronic devices for extremely high temperature applications. 
FIG: a) Energy band diagram of Graphene/p-SiC/Graphene structure, b) Cross-sectional view of the suggested IGE/4H-SiC MSM UV-PD with interdigitated electrodes

Acknowledgments: This work was supported by DGRSDT Of Ministry of Higher education of Algeria. The work was done in the unit of research of materials and renewable energies (URMER).

Open Science Idea

Open Science Idea
2020 TEDxSkoltech Moscow
[full pdf:]

Talk  by Александра Элбакян, the Sci-Hub creator, at the TEDx conference at Uni Skoltech. The text transcript is given with  slides. All the video recording of that performance has been removed from TED website as the organizers referred to the fact that it violated some TED rules.

Saturday, May 23, 2020

[PhD] Printed Inorganic Materials Electronics

Circuit Design and Compact Modeling in Printed Electronics Based on Inorganic Materials
PhD Dissertation
Gabriel Cadilha Marques
Veröffentlicht am 30.04.2020
DOI: 10.5445/IR/1000118801

Abstract - The goal of this thesis is therefore to develop an inorganic printed electronics technology with corresponding modeling methodologies to capture device behavior for industry standard circuit simulators as well as circuit designs as building blocks for future applications. To reduce the high supply voltage requirements (~5V) in PE, alternative gating approaches for FETs are considered. One approach is to replace the dielectric with an electrolyte. Due to the formation of a Helmholtz double layer (HDL), a FET with a high gate-capacitance (~5 μFcm-2) is expected, reducing the voltage requirements to ~1V. By combining the indium oxide channel with the electrolyte-gating approach, high performance devices with low voltage requirements are available in PE.

Tuesday, May 19, 2020

[paper] Polymer Electrodes in Clinical EEG and MEG

Laura M. Ferrari, Usein Ismailov, Jean-Michel Badier, Francesco Greco and Esma Ismailova 
Conducting polymer tattoo electrodes in clinical electro- and magneto-encephalography
npj Flex Electron 4, 4 (2020)
Received: 17 October 2019; Accepted: 20 February 2020;
DOI: 10.1038/s41528-020-0067-z

Abstract - Temporary tattoo electrodes are the most recent development in the field of cutaneous sensors. They have successfully demonstrated their performances in the monitoring of various electrophysiological signals on the skin. These epidermal electronic devices offer a conformal and imperceptible contact with the wearer while enabling good quality recordings over time. Evaluations of brain activity in clinical practice face multiple limitations, where such electrodes can provide realistic technological solutions and increase diagnostics efficiency. Here we present the performance of inkjet-printed conducting polymer tattoo electrodes in clinical electroencephalography and their compatibility with magnetoencephalography. The working mechanism of these dry sensors is investigated through the modeling of the skin/electrode impedance for better understanding of the biosignals transduction at this interface. Furthermore, a custom-made skin phantom platform demonstrates the feasibility of high-density recordings, which are essential in localizing neuropathological activities. These evaluations provide valuable input for the successful application of these ultrathin electronic tattoos sensors in multimodal brain monitoring and diagnosis.

Fig: Temporary tattoo electrodes (TTEs) for EEG: a The layered structure of the temporary tattoo paper permits the release of the top film on which electrodes are fabricated. b Expanded view of an all-polymer printed TTE. c A TTE released on the scalp, in Oz position. d Close-in view of a TTE released on the scalp after 12 h from application. e Impedance recordings on the forearm using TTE and Ag/AgCl electrodes. 
Experiments involving human participants -Two able-bodied participants (one male and one female aged 33.5 ± 3.5 years old) free of any motor and neural disorders gave their informed consent and participated in this study. One participant performed the impedance recordings with the three diverse TTEs sets while another participant volunteered in the EEG/MEG evaluations with TTEs and Ag/AgCl electrodes. All experiments are performed following Timone hospital’s regulations regarding personal data protection. The experiment was conducted under conditions provided by French regulations.

Data Availability - The experimental data referenced in this text is available from the authors upon reasonable request.

#EU Parliament Strongly Recommends Developing and Using #opensource Software

from Twitter

May 19, 2020 at 10:00AM

Monday, May 18, 2020

[paper] Novel Design and Optimization and the gm/ID Ratio

A Novel Design and Optimization Approach for Low Noise Amplifiers (LNA) Based on MOST Scattering Parameters and the gm/ID Ratio
1Facultad de Ingeniería, Universidad Católica de Córdoba, Córdoba 5017 (AN)
2Service d’Électronique et Microélectronique, Université de Mons (UMONS), 7000 Mons (BE)
3Departamento de Electrónica, Instituto de Astrofísica de Canarias (IAC), 38200 La Laguna (SP)
* Author to whom correspondence should be addressed.
Electronics 2020, 9(5), 785;
Received: 31 March 2020 / Revised: 30 April 2020 
Accepted: 9 May 2020 / Published: 11 May 2020

AbstractThis work presents a new design methodology for radio frequency (RF) integrated circuits based on a unified analysis of the scattering parameters of the circuit and the gm/ID ratio of the involved transistors. Since the scattering parameters of the circuits are parameterized by means of the physical characteristics of transistors, designers can optimize transistor size and biasing to comply with the circuit specifications given in terms of S-parameters. A complete design of a cascode low noise amplifier (LNA) in 65nm CMOS technology is taken as a case study in order to validate the approach. In addition, this methodology permits the identification of the best trade-off between the minimum noise figure and the maximum gain for the LNA in a very simple way.
Figure: gm/ID versus iD

Acknowledgement - This research was funded by Universidad Católica de Córdoba (Argentina), the Walloon Region DGO6 BEWARE Fellowships Academia Programme (1410164-POHAR, cofunded by the European Marie Curie Actions), the Belgian FNRS (Fond National pour la Recherche Scientifique) and the Argentinean MINCyT (Ministerio de Ciencia y Tecnología).

Friday, May 15, 2020

[paper] Electrical characterization of advanced MOSFETs

Valeriya Kilchytska, Sergej Makovejev, Babak Kazemi Esfeh, Lucas Nyssens, Arka Halder,
Jean-Pierre Raskin and Denis Flandre
Electrical characterization of advanced MOSFETs towards analog and RF applications
IEEE LAEDC, San Jose, Costa Rica, 2020, 
doi: 10.1109/LAEDC49063.2020.9073536

Abstract - This invited paper reviews main approaches in the electrical characterization of advanced MOSFETs towards their target analog and RF applications. Advantages and necessity of those techniques will be demonstrated on different study cases of various advanced MOSFETs, such as FDSOI, FinFET, NW in a wide temperature range, based on our original research over the last years. 


Acknowledgements - This work was partially funded by Eniac “Places2Be”, Ecsel “Waytogofast”, FNRS - FRFC “Towards Highly-efficient 10 nm MOSFETs”, FP7 “Nanosil” and “Nanofunction” projects. The authors thank our colleagues from CEA-Leti, ST and Imec, and particularly, F. Andrieu, O. Faynot, T. Poiroux, S. Barraud, M. Haond, N. Planes, N. Collaert, C. Claeys, M. Jurczak, B. Parvais, R. Rooyackers, for providing UTBB FD SOI, NW and FinFET devices and valuable discussions.

Thursday, May 14, 2020

Wednesday, May 13, 2020

#OpenRAMAN: #OpenSource Raman Spectrometer Is Cheaper, But Not Cheap

from Twitter

May 13, 2020 at 10:22AM

Tuesday, May 12, 2020

[paper] Computing-in-Memory

Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryption
Dayane Reis, Student Member, IEEE, Jonathan Takeshita, Taeho Jung, Member, IEEE, Michael Niemier, Senior Member, IEEE and Xiaobo Sharon Hu, Fellow, IEEE
preprint arXiv:2005.03002 (2020).

Abstract - Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) — paradigms where computation is done within the memory boundaries — represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation.When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-toend tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPUbased HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally,our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGAbased accelerator.
Fig: Log shifter implemented in CiM-HE.
This work was supported in part by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Corresponding author: Xiaobo Sharon Hu, Department of Computer Science and Engineering, University of Notre Dame, Notre Dame, IN, 46556, USA. e-mail: .

Monday, May 11, 2020

Conference Paper Reached 300 Reads

Grabinski, Wladek, Daniel Tomaszewski, Farzan Jazaeri, Anurag Mangla, Jean-Michel Sallese, Maria-Anna Chalkiadaki, Antonios Bazigos, and Matthias Bucher
FOSS EKV 2.6 Parameter Extractor
In 2015 22nd International MIXDES Conference , pp. 181-186. (2015)

Abstract—The design of advanced integrated circuits (IC) in particular for low power analog and radio-frequency (RF) application becomes more complex as the device level modeling confronting challenges in micro- and nano-meter CMOS processes. As present CMOS technologies continue geometry scaling the designers can benefit using dedicated SPICE MOSFET models and apply specific analog design methodologies. The EKV was developed especially to meet altogether the analog/RF design requirements. This paper describes a basic set of the DC parameter extraction steps for the EKV 2.6 model. The free open source software (FOSS) Profile2D tool was used to illustrate accurate EKV 2.6 DC extraction strategy. 

[paper] BSIM-HV: High-Voltage MOSFET Model

H. Agarwal , Member, IEEE, C. Gupta , Graduate Student Member, IEEE, R. Goel , Graduate Student Member, IEEE, P. Kushwaha , Member, IEEE, Y.-K. Lin , Graduate Student Member, IEEE, M.-Y. Kao , Graduate Student Member, IEEE, J.-P. Duarte , Graduate Student Member, IEEE, H.-L. Chang , Member, IEEE, Y. S. Chauhan , Senior Member, IEEE, S. Salahuddin, Fellow, IEEE, and C. Hu, Life Fellow, IEEE
BSIM-HV: High-Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect
IEEE TED, vol. 66, no. 10, pp. 4258-4263, Oct. 2019
doi: 10.1109/TED.2019.2933611

Abstract - A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90V LDMOS and 40V VDMOS transistors, and shows excellent agreement.
FIG: Schematic of the LDMOS. Lightly doped n-region constitutes the drain. Majority of the applied drain voltage drops across this region, which protects the intrinsic transistor region from breakdown.
Manuscript received March 3, 2019; revised May 23, 2019 and July 24, 2019; accepted July 31, 2019. Date of publication August 26, 2019; date of current version September 20, 2019. This work was supported in part by the members of the Berkeley Center for Negative Capacitance Technology and the members of the Berkeley Device Modeling Center. The review of this article was arranged by Editor B. Iñiguez.

[paper] Compact Device Models for FinFET and Beyond

D. D. Lu, M. V. Dunga, A. M. Niknejad, C.Bing Hu, F.-X. Liang, W.-C. Hung, J. Lee, C.-H. Hsu
and M.-H. Chiang,
Compact device models for FinFET and beyond
ArXiv, vol. abs/2005.02580, 2020

Abstract - Compact device models play a significant role in connecting device technology and circuit design. BSIM-CMG and BSIM-IMG are industry standard compact models suited for the FinFET and UTBB technologies, respectively. Its surface potential based modeling framework and symmetry preserving properties make them suitable for both analog/RF and digital design. In the era of artificial intelligence / deep learning, compact models further enhanced our ability to explore RRAM and other NVM-based neuromorphic circuits. We have demonstrated simulation of RRAM neuromorphic circuits with Verilog-A based compact model at NCKU. Further abstraction with macromodels is performed to enable larger scale machine learning simulation.
Fig: Simulation of a novel floating - gate synaptic transistor. (a) Device structure with separate negative feedback gate (nfb) for programming and synaptic gate (sg) readout. (b) Equivalent circuit diagram for compact modeling 
Acknowledgements - The authors would like to express sincere gratitude to Chip Implementation Center (CIC), Hsinchu, Taiwan for providing SPICE simulation environment for RRAM simulations.

Thursday, May 7, 2020

[PhD] Compact DC Modeling of Tunnel-FETs

Compact DC Modeling of Tunnel-FETs
November 2019
PhD Thesis of Fabian Horst 
Doctor Advisor: Profs. Benjamin Iniguez and Alexander Kloes

Abstract - In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator. 

Fig: 2D sketch of the n-type DG TFET device geometry, showing the channel thickness t ch , the channel length l ch , the gate oxide thickness tox and the length of the S/D region l sd . Source (S) and drain (D) region are highly p/n-doped with a doping concentration N s/d 


Wednesday, May 6, 2020

IEEE EDS DL Series by the EDS Delhi Chapter
IEEE Electronc Devices Society
IEEE Electron Device Society (EDS) Delhi Chapter – India
Department of Electronic Science
University of Delhi South Campus, New Delhi, India
Delhi University - Colleges, Cut off 2020, Courses, Fees, Admissions
Jointly Organizes
EDS Distinguished Lecture
(Live Session under EDS Distinguished Lecturer Program - Virtual Lectures)
Online Live Webinar Lecture Schedule (via Google Meet)
April 30, 2020 at 10:30 am (past event)
High-k Dielectric and Interface Engineering for High Performance Si/Ge MOS and FinFETs
Kuei-Shu Chang-Liao
Department of Engineering and System Science
National Tsing Hua University, Hsinchu, Taiwan
May 01, 2020 at 10:30 am  (past event)
Two-dimensional Layered Materials for Nanoelectronics Chai
Associate Professor, Department of Applied Physics
The Hong Kong Polytechnic University
May 05, 2020 at 01:30 pm (past event)
Introducing two-dimensional layered dielectrics in solid-state micro-electronic devices
Mario LanzaMario Lanza
Institute of Functional Nano & Soft Materials, Soochow University, Collaborative Innovation Center of Suzhou Nano Science & Technology, China
May 06, 2020 at 06:30 pm (past event)
Field Effect Transistors: From MOSFET to Tunnel-FET
Joao Antonio Martino
Professor at University of Sao Paulo, Brazil
May 08,2020 at 06:30 pm IST
Junctionless Nanowire Transistors: Electrical Characteristics and Compact Modeling
Marcelo Antonio Pavanello Centro Universitario FEI, Department of Electrical Engineering Av. Humberto de Alencar Castelo Branco, Sao Bernardo do Campo,  Brazil
May 11, 2020 at 01:30 pm IST
From CMOS to Neuromorphic Computing - A peek into the future
EEE Staff Photo Prof M De SouzaMaria Merlyne De Souza
Department of Electronic and Electrical Engineering
The University of Sheffield, United Kingdom 
May 12, 2020 at 10:30 am IST
Phase change electro-optical devices for space applications
Mina Rais-Zadeh  portraitMina Rais-Zadeh
Group Supervisor, Advanced Optical and Electromechanical Microsystems Group, Micro Device Laboratory, NASA JPL, Pasadena, CA
May 15, 2020 at 08:30 pm IST
State-of-the-Art Silicon Very Large Scale Integrated Circuits: Industrial Face of Nanotechnology S. Shur 
Electrical, Computer and Systems Engineering and Physics, Applied Physics, and Astronomy
Rensselaer Polytechnic Institute 
May 16, 2020 at 02:00 pm IST
Transparent and Flexible Large Area Electronics
Arokia  Nathan portraitArokia Nathan 
Cambridge Touch Technologies, 
University of Cambridge, United Kingdom (UK)
May 20, 2020 at 02:30 pm IST
Trends and challenges in Nanoelectronics for the next decade
Elena  Gnani portraitElena Gnani 
Department of Electrical, Electronic and Information Engineering, University of Bologna, Italy 
May 22, 2020 at 07:30 pm IST
Accelerating commercialization of SiC power electronics
Victor VeliadisVictor Veliadis
Executive Director and CTO, Power America
Professor of Electrical and Computer Engineering, 
North Carolina State University
May 27, 2020 at 07:30 pm IST
Advanced III-N Devices for 5G and Beyond
Patrick Fay
Department of Electrical Engineering, 
University of Notre Dame
More talks will be added so if you wish to attend any of these then then kindly register on:

Coordinated by:
Dr. Manoj Saxena, SMIEEE, FIETE, MNASc (India)
EDS BoG Member (2018-2020) & EDS DL
Regional Editor for South Asia, IEEE EDS Newsletter
Associate Professor, Department of Electronics 
Deen Dayal Upadhyaya College, University of Delhi 
Dwarka Sector-3, New Delhi, India; Email: 
Professor Mridula Gupta, SMIEEE, FIETE
Chairperson-IEEE EDS Delhi Chapter
Head, Department of Electronic Science
University of Delhi South Campus
New Delhi 110021, India