Die shots of the Raspberry Pi #RP2040 #chip #Teardown #Dieshot #ReverseEngineering #PiDay #semi @johndmcmaster @Raspberry_Pi https://t.co/3B7OuJRpBH https://t.co/ghjLWICnno

Die shots of the Raspberry Pi #RP2040 #chip #Teardown #Dieshot #ReverseEngineering #PiDay #semi @johndmcmaster @Raspberry_Pi https://t.co/3B7OuJRpBH pic.twitter.com/ghjLWICnno

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[mos-ak] 1st Asia/South Pacific MOS-AK Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion

Modeling of Systems and Parameter Extraction Working Group

1st Asia/South Pacific MOS-AK Workshop

(virtual/online) FEB. 25-26, 2021

Together with  local organization team, International MOS-AK Board of R&D Advisers as well as all the Extended MOS-AK TPC Committee, we have the pleasure to invite to 1st Asia/South Pacific MOS-AK Workshop which will be organized as the virtual/online event on FEB. 25-26, 2021

Planned virtual 1st Asia/South Pacific MOS-AK Workshop aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring academic and industrial experts in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue: Virtual/Online

Online Workshop Registration to be open FEB.15 2021 

(any related enquiries can be sent to register@mos-ak.org)

Topics to be covered include the following among other related to the compact/SPICE modeling and its Verilog-A standardization:

• Compact Modeling (CM) of the electron devices
• Advances in semiconductor technologies and processing
• Verilog-A language for CM standardization
• New CM techniques and extraction software
• Open Source (FOSS) TCAD/EDA modeling and simulation
• CM of passive, active, sensors and actuators
• Emerging Devices, TFT, CMOS and SOI-based memory cells
• Microwave, RF device modeling, high voltage device modeling
• Nanoscale CMOS, BiCMOS, SiGe, GaN, InP devices and circuits
• Technology R&D, DFY, DFT and reliability/ageing IC designs
• Foundry/Fabless Interface Strategies

Important Dates: 

• 2nd Announcement: Jan. 2021
  
• Final Workshop Program: Feb. 2020
  
• Virtual MOS-AK Workshop:  FEB. 25-26, 2021
  

Online Abstract Submission to be open FEB.1 2021

(any related enquiries can be sent to abstracts@mos-ak.org)

Extended MOS-AK Committee

WG250121

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The big question: Will #Intel become Outtel? https://t.co/Nt0fkMv8K2 #semi https://t.co/hxtbZEyRai

The big question: Will #Intel become Outtel? https://t.co/Nt0fkMv8K2 #semi pic.twitter.com/hxtbZEyRai

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The Knowledge Transfer Network (#KTN) and UK Space Agency (#UKSA) have mapped out a Space Sector Landscape for the UK. https://t.co/hq1sLEd5e6 #semi https://t.co/xKBmW0cxBG

The Knowledge Transfer Network (#KTN) and UK Space Agency (#UKSA) have mapped out a Space Sector Landscape for the UK. https://t.co/hq1sLEd5e6 #semi pic.twitter.com/xKBmW0cxBG

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Joint Spring MOS-AK, SB-MOS and IEEE EDS MQ

Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) Devices

with IEEE EDS Mini-Colloquium on “Non-Conventional Devices and Technologies”

September 29 to October 1, 2020

THM Giessen (Germany)

—by Mike Schwarz— The Joint Spring MOS-AK Workshop and Symposium on Schottky Barrier MOS (SB-MOS) devices with IEEE EDS Mini-Colloquium on “Non-conventional Devices and Technologies” was held from September 29 to October 1, 2020. While it was initially planned for spring at THM—University of Applied Sciences in Giessen (Germany), it was shifted to the early autumn due to the COVID-19 pandemic. However, finally the local organizers of NanoP Competence Center for Nanotechnology and Photonics of THM decided to move it to Zoom and perform it virtually. It was sponsored by THM, the EDS Germany Chapter, the IEEE Young Professionals Germany Affinity Group, and the AdMOS company. The event was attended by 69 IEEE members and 115 non IEEE members (guests) from 25 countries during the three days [read more...]

#Samsung Foundry Certifies Analog #FastSPICE Platform from #Siemens

#Samsung Foundry Certifies Analog #FastSPICE Platform from #Siemens for Early Design Starts on #3nm #GAA #Semi Technology

https://t.co/WhRlX9Xts1 pic.twitter.com/ZLl20ROru7

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#GaN based #MEMS resonator operates stably at high temperature https://t.co/5qKtiUn6q3 #semi https://t.co/mhajQde4EQ

#GaN based #MEMS resonator operates stably at high temperature https://t.co/5qKtiUn6q3 #semi pic.twitter.com/mhajQde4EQ

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[paper] Publish or be ethical?

Mariola Paruzel-Czachura, Lidia Baran, Zbigniew Spendel 

Publish or be ethical? Publishing pressure and scientific misconduct in research 

First Published CC BY-NC 4.0 Dec. 18, 2020 

SAGE Journals: Research Ethics (2020) 

DOI: 10.1177/1747016120980562 

* Institute of Psychology, University of Silesia in Katowice, Poland

Abstract: The paper reports two studies exploring the relationship between scholars’ self-reported publication pressure and their self-reported scientific misconduct in research. In Study 1 the participants (N = 423) were scholars representing various disciplines from one big university in Poland. In Study 2 the participants (N = 31) were exclusively members of the management, such as dean, director, etc. from the same university. In Study 1 the most common reported form of scientific misconduct was honorary authorship. The majority of researchers (71%) reported that they had not violated ethical standards in the past; 3% admitted to scientific misconduct; 51% reported being were aware of colleagues’ scientific misconduct. A small positive correlation between perceived publication pressure and intention to engage in scientific misconduct in the future was found. In Study 2 more than half of the management (52%) reported being aware of researchers’ dishonest practices, the most frequent one of these being honorary authorship. As many as 71% of the participants report observing publication pressure in their subordinates. The primary conclusions are: (1) most scholars are convinced of their morality and predict that they will behave morally in the future; (2) scientific misconduct, particularly minor offenses such as honorary authorship, is frequently observed both by researchers (particularly in their colleagues) and by their managers; (3) researchers experiencing publication pressure report a willingness to engage in scientific misconduct in the future.

Fig: Ways in which respondents have infringed ethical principles

Founding: The current research was supported by Miniatura1 2017/01/X/HS6/01332 from the National Science Centre (NCN, Poland) to Mariola Paruzel-Czachura. Any opinions, findings, and conclusions or recommendations expressed in this material are those of them authors and do not necessarily reflect the views of the National Science Center. The funders had no role in study design, data collection and analysis, decision to publish, or preparation of the manuscript.

Tracking a variety of #semi, which are affected by COVID-19. (Image source: Yole) https://t.co/oeNFCdXZTj https://t.co/8wV4D8PQR3

Tracking a variety of #semi, which are affected by COVID-19

(Image source: Yole) https://t.co/oeNFCdXZTj pic.twitter.com/8wV4D8PQR3

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[paper] CNTFET Technology for RF Applications

Martin Hartmann^1,2, Sascha Hermann^1,2,3, Phil F. Marsh⁴, Christopher Rutherglen⁴, 

Dawei Wang⁵, Li Ding⁶, Lian-Mao Peng⁶, Martin Claus⁷, 

and Michael Schröter⁷ (Senior Member, IEEE)

CNTFET Technology for RF Applications:

Review and Future Perspective

(Invited Paper)

IEEE Journal of Microwaves, vol. 1, no. 1, pp. 275-287, 2021

DOI: 10.1109/JMW.2020.3033781

¹Center for Microtechnology, Chemnitz University of Technology, Chemnitz, Germany
²Center for Advancing Electronics Dresden, Germany
³Fraunhofer Institute for Electronic Nanosystems, Chemnitz, Germany
⁴Carbonics Inc., Culver City, USA
⁵Carbon Technology Inc., Irvine, USA
⁶Key Laboratory for the Physics and Chemistry of Nanodevices 

and Center for Carbon-based Electronics,  Peking University, China
⁷Chair for Electron Devices and Integrated Circuits, Technical University Dresden, Germany

Abstract: RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Fig: (a) sketch of a T-shape top gate on 4" wafer and (b) corresponding SEM image,

(c) SEM image in false colors depicting a multifinger buried gate CNTFET on an 8" wafer.

Acknowledgement: This work was supported in part by the German Research Foundation (DFG) through the Cluster of Excellence “Center for Advancing Electronics Dresden” (EXC1056/1); in part by the Federal Ministry of Education and Research under the project reference numbers 16FMD01K, 16FMD02 and 16FMD03, under the individual DFG Grant SCR695/6%25; in part by the National Key Research & Development Program under Grant 2016YFA0201901; in part by the National Science Foundation of China under Grants 61888102 and 61671020; in part by the Beijing Municipal Science and Technology Commission under Grant Z181100004418011; in part by the King Abdulaziz City for Science and Technology (KACST); in part by the The Saudi Technology Development and Investment Company (TAQNIA); in part by the U.S. Army STTR Contract W911NF19P002; and in part by the SBIR programs from the U.S. National Science Foundation and the U.S. Air Force Research Laboratory.

Von Neumann Is Struggling https://t.co/CQZ9RSnUNx #semi https://t.co/fbpB7K9TFw

Von Neumann Is Struggling https://t.co/CQZ9RSnUNx #semi pic.twitter.com/fbpB7K9TFw

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Virtual Si Museum /2103/ Electron Devices Scaling

Other look at the electron device scaling: Trinitron CRT vs iPhone6 Retina HD LED display. Both were extracted for broken units:) Trinitron CRT (Sony's brand name for its line of aperture-grille-based CRTs) were introduced in 1968. Its standard TV resolution was 720x576-pixel for PAL. iPhone6 available since 2014 has the HD LED display 1334x750-pixel. Just estimate volume, resolution and power consumption scaling in both cases.

REF:

• Sony Trinitron A13JZVOOX
  5-inch (diagonal) CRT 720x576-pixel resolution for PAL at 192 ppi
• iPhone6 Retina HD display
  4.7-inch (diagonal) LED 1334x750-pixel resolution at 326 ppi

[paper] MEMS thermal actuators

Longchang Ni, Ryan M. Pocratsky and Maarten P. de Boer 

Demonstration of tantalum as a structural material for MEMS thermal actuators 

Microsyst Nanoeng 7, 6 (2021) 

DOI: 10.1038/s41378-020-00232-z 

CMU Mechanical Engineering Dept., Pittsburgh, PA, USA

Abstract: This work demonstrates the processing, modeling, and characterization of nanocrystalline refractory metal tantalum (Ta) as a new structural material for microelectromechanical system (MEMS) thermal actuators (TAs). Nanocrystalline Ta films have a coefficient of thermal expansion (CTE) and Young’s modulus comparable to bulk Ta but an approximately ten times greater yield strength. The mechanical properties and grain size remain stable after annealing at temperatures as high as 1000 °C. Ta has a high melting temperature (Tm = 3017 °C) and a low resistivity (ρ = 20 µΩ cm). Compared to TAs made from the dominant MEMS material, polycrystalline silicon (polysilicon, Tm = 1414 °C, ρ = 2000 µΩ cm), Ta TAs theoretically require less than half the power input for the same force and displacement, and their temperature change is half that of polysilicon. Ta TAs operate at a voltage 16 times lower than that of other TAs, making them compatible with complementary metal oxide semiconductors (CMOS). We select α-phase Ta and etch 2.5-μm-thick sputter-deposited films with a 1 μm width while maintaining a vertical sidewall profile to ensure in-plane movement of TA legs. This is 25 times thicker than the thickest reactive-ion-etched α-Ta reported in the technical literature. Residual stress sensitivities to sputter parameters and to hydrogen incorporation are investigated and controlled. Subsequently, a V-shaped TA is fabricated and tested in air. Both conventional actuation by Joule heating and passive self-actuation are as predicted by models.

Fig: Top view of freestanding Ta thermal actuator. In-plane deflection δ ≈ 5µm after hydrogen degas step

Acknowledgements: This work was partially supported by the US National Science Foundation (NSF) grant number CMMI-1635332. We also acknowledge the Kavcic-Moura Endowment Fund for the support. We would like to thank the executive manager, Matthew Moneck, and all the staff members of the CMU Eden Hall Foundation Cleanroom for their guidance and advice on equipment usage and process development. We also acknowledge the use of the Materials Characterization Facility at Carnegie Mellon University under grant # MCF-677785

[paper] Subtractive photonics

Reza Fatemi, Craig Ives, Aroutin Khachaturian, and Ali Hajimiri

Subtractive photonics

Optics Express Vol. 29, Issue 2, pp. 877-893 (2021)

DIO: 10.1364/OE.410139

California Institute of Technology, 1200 E. California Blvd., Pasadena, CA 91125, USA

Abstract: Realization of a multilayer photonic process, as well as co-integration of a large number of photonic and electronic components on a single substrate, presents many advantages over conventional solutions and opens a pathway for various novel architectures and applications. Despite the many potential advantages, realization of a complex multilayer photonic process compatible with low-cost CMOS platforms remains challenging. In this paper, a photonic platform is investigated that uses subtractively manufactured structures to fabricate such systems. These structures are created solely using simple post-processing methods, with no modification to the foundry process. This method uses the well-controlled metal layers of advanced integrated electronics as sacrificial layers to define dielectric shapes as optical components. Metal patterns are removed using an etching process, leaving behind a complex multilayer photonic system, while keeping the electronics'metal wiring intact. This approach can be applied to any integrated chip with well-defined metallization, including those produced in pure electronics processes, pure photonics processes, heterogeneously integrated processes, monolithic electronic-photonic processes, etc. This paper provides a proof-of-concept example of monolithic electronic-photonic integration in a 65 nm bulk CMOS process and demonstrates proof-of-concept photonic structures. The fabrication results, characterization, and measurement data are presented.

Fig: The fabricated chip with various photonic structures in a measurement setup.

[paper] Fabrication EM AlGaN/GaN MIS HEMT

Flavien Cozette¹, Bilal Hassan¹, Christophe Rodriguez¹, Eric Frayssinet², Rémi Comyn², François Lecourt³, Nicolas Defrance⁴, Nathalie Labat⁵, François Boone¹, Ali Soltani¹, Abdelatif Jaouad¹, Yvon Cordier² and Hassan Maher¹

New barrier layer design for the fabrication of gallium nitride-metal-insulator-semiconductor-high electron mobility transistor normally-off transistor

2021 Semicond. Sci. Technol. 36 034002

DOI: 10.1088/1361-6641/abd489

¹LN2, CNRS-UMI-3463, 3IT, Université de Sherbrooke, Canada

²Université Côte d'Azur, CNRS, CRHEA, Valbonne, France

³OMMIC, 94450 Limeil-Brévannes, France

⁴IEMN, CNRS-UMR-8520, University of Lille, France

⁵IMS, CNRS-UMR-5218, University of Bordeaux, France

Abstract: This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (Vth) of +0.4 V and +0.9 V respectively with ΔVth about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an ION/IOFF about 108 and a breakdown voltage of VBR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface.

Fig: SEM image of an E-mode device.

Acknowledgments: This work was supported by Fonds de Recherches du Québec—Nature, Technologies (FRQNT), the Natural Sciences and Engineering Research Council of Canada (NSERC), French technology facility network RENATECH and the French National Research Agency (ANR) through the projects ED-GaN (ANR-16-CE24-0026-02) and the 'Investissements d'Avenir' program GaNeX (ANR-11-LABX-0014).

Imec’s Plan For Continued Scaling: “Towards Atomic Channels and Deconstructed Chips” https://t.co/rUAJ5qPJOO #semi https://t.co/CiRNgqPsHG

Imec’s Plan For Continued Scaling: “Towards Atomic Channels and Deconstructed Chips” https://t.co/rUAJ5qPJOO #semi 

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More #Data, More #Memory-#Scaling Issues https://t.co/Zqnozg3YIe #semi https://t.co/vnI48eyGFL

More #Data, More #Memory-#Scaling Issues https://t.co/Zqnozg3YIe #semi pic.twitter.com/vnI48eyGFL

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IEEE-EDS SCV/SF Chapter January Seminar (Webex only)

Title: Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and Prospects

Speaker: Prof. Shimeng Yu, Georgia Institute of Technology

Friday, January 15, 2020 at noon – 1PM PDT

Please note that this seminar is now WEBEX participation only:

Webex Link 

Organizer contact: Hiu Yung Wong <hiuyung.wong@ieee.org>

Abstract: Compute-in-memory (CIM) is a new computing paradigm that addresses the memory-wall problem in the deep learning accelerator. In this presentation, first I will present our DNN+NeuroSim benchmark framework that is interfaced with Tensorflow/PyTorch to evaluate different device technologies for state-of-the-art DNN models. We will discuss about the pros and cons of various non-volatile memory candidates and the most important device specifications for inference/training, respectively. Second, I will present our RRAM-CIM prototype chips that are integrated with CMOS peripheral circuitry and its performance. Furthermore, we will show our experimental characterizations of the multilevel RRAM's variability and reliability and their impact on DNN inference accuracy. To overcome the challenges of the RRAM-CIM prototypes we identified, we propose monolithic 3D integration with back-end-of-line (BEOL) transistors as a potential solution.

Speaker Bio: Shimeng Yu is an associate professor of electrical and computer engineering at the Georgia Institute of Technology. He received the B.S. degree in microelectronics from Peking University in 2009, and the M.S. degree and Ph.D. degree in electrical engineering from Stanford University in 2011 and 2013, respectively. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu's research interests are nanoelectronic devices and circuits for energy-efficient computing systems. His expertise is on the emerging non-volatile memories (e.g., RRAM, ferroelectrics) for different applications such as deep learning accelerator, neuromorphic computing, monolithic 3D integration, and hardware security. Among Prof. Yu's honors, he was a recipient of the NSF Faculty Early CAREER Award in 2016, the IEEE Electron Devices Society (EDS) Early Career Award in 2017, the ACM Special Interests Group on Design Automation (SIGDA) Outstanding New Faculty Award in 2018, the Semiconductor Research Corporation (SRC) Young Faculty Award in 2019, and the ACM/IEEE Design Automation Conference (DAC) Under-40 Innovators Award in 2020, etc. Prof. Yu is active in professional services. He served or is serving many premier conferences as technical program committee, including IEEE International Electron Devices Meeting (IEDM), IEEE Symposium on VLSI Technology, etc. He is a senior member of the IEEE.

More information at
the IEEE EDS Santa Clara Valley-San Francisco Chapter Home Page

Creating #Silicon #Valley 2.0 #SV2.0 [IEEE Spectrum] https://t.co/RAqZp75pGL) #semi https://t.co/4LGbgFCjMd

Creating #Silicon #Valley 2.0 #SV2.0 [IEEE Spectrum] https://t.co/RAqZp75pGL) #semi pic.twitter.com/4LGbgFCjMd

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[paper] Modeling Power GaN-HEMTs in SPICE

Utkarsh Jadli, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande*, Mayank Chaturvedi and Sima Dimitrijev

Modeling Power GaN-HEMTs Using Standard MOSFET Equations and Parameters in SPICE

Electronics 2021, 10, 130

DOI: 10.3390/electronics10020130

Queensland Micro- and Nanotechnology Centre, Griffith University, Brisbane, QLD 4111, Australia;

*Electronics Department, Graphic Era (Deemed to Be University), Dehradun, Uttarakhand 248002, India;

Abstract: The device library in the standard circuit simulator (SPICE) lacks a gallium nitride based high-electron-mobility-transistor (GaN-HEMT) model, required for the design and verification of power-electronic circuits. This paper shows that GaN-HEMTs can be modeled by selected equations from the standard MOSFET LEVEL3 model in SPICE. A method is proposed for the extraction of SPICE parameters in these equations. The selected equations and the proposed parameter-extraction method are verified with measured static and dynamic characteristics of commercial GaN-HEMTs. Furthermore, a double pulse test is performed in LTSpice and compared to its manufacturer model to demonstrate the effectiveness of the MOSFET LEVEL3 model. The advantage of the proposed approach to use the MOSFET LEVEL3 model, in comparison to the alternative behavioral-based model provided by some manufacturers, is that users can apply the proposed method to adjust the parameters of the MOSFET LEVEL3 model for the case of manufacturers who do not provide SPICE models for their HEMTs.

Fig: Internal cross-sectional structure of GaN-HEMT

Acknowledgments: The authors would like to acknowledge the Innovative Manufacturing Co- operative Research Centre (IMCRC) for providing a PhD scholarship to the first author. We also acknowledge the School of Engineering and Built Environments (EBE) of Griffith University for funding this project. This work was performed in part at the Queensland node of the Australian National Fabrication Facility, a company established under the National Collaborative Research Infrastructure Strategy to provide nano- and micro-fabrication facilities for Australia’s researchers.

[paper] Stretchable transistors

Yahao Dai, Huawei Hu, Maritha Wang, Jie Xu* and Sihong Wang

Stretchable transistors and functional circuits for human-integrated electronics

Nat Electron (2021) 

DOI:10.1038/s41928-020-00513-5

Pritzker School of Molecular Engineering, The University of Chicago, Chicago, IL, USA
*Nanotechnology and Science Division, Argonne National Laboratory, Lemont, IL, USA

Abstract: Electronics with skin- or tissue-like mechanical properties, including low stiffness and high stretchability, can be used to create intelligent technologies for application in areas such as health monitoring and human–machine interactions. Stretchable transistors that provide signal-processing and computational functions will be central to the development of this technology. Here, we review the development of stretchable transistors and functional circuits, examining progress in terms of materials and device engineering. We consider the three established approaches for creating stretchable transistors: buckling engineering, stiffness engineering and intrinsic-stretchability engineering. We also explore the current capabilities of stretchable transistors and circuits in human-integrated electronics and consider the challenges involved in delivering advanced applications.

Fig: Stretchable sensor–amplifier system for pulse measurements [Nature 555] 

Acknowledgements: This work is supported by the start-up fund from the University of Chicago. J.X. acknowledges support from the Center for Nanoscale Materials, a US Department of Energy Office of Science User Facility, and the US Department of Energy, Office of Science, under contract no. DE-AC02-06CH11357.

REF:

[Nature 555] Wang, S. et al. Skin electronics from scalable fabrication of an intrinsically stretchable transistor array. Nature 555, 83–88 (2018).

The #Top50 Most Valuable Global Brands https://t.co/6pkHadVcJ4 #semi https://t.co/vtZiOE5DL7

The #Top50 Most Valuable Global Brands https://t.co/6pkHadVcJ4 #semi pic.twitter.com/vtZiOE5DL7

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[Technical Paper] Shunsuke Abe et al. ;Photonic integration based on a ferroelectric thin-film platform; Advantest Laboratories, Ltd. https://t.co/463lP5jlAi #semi https://t.co/d6jWVypZBA

[Technical Paper] Shunsuke Abe et al. ;Photonic integration based on a ferroelectric thin-film platform; Advantest Laboratories, Ltd. https://t.co/463lP5jlAi #semi pic.twitter.com/d6jWVypZBA

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[paper] Neuromuscular Junction‐on‐a‐Chip

Rianne de Jongh¹, Xandor M. Spijkers^1,2, Svetlana Pasteuning‐Vuhman¹, 

Paul Vulto² R. Jeroen Pasterkamp¹

Neuromuscular Junction‐on‐a‐Chip: 

ALS disease modeling and read‐out development in microfluidic devices

Journal of Neurochemistry 

Open Access 31 December 2020

DOI: 10.1111/jnc.15289 

1 Department of Translational Neuroscience, University Medical Center Utrecht Brain Center, Utrecht University, Utrecht, The Netherlands.
2 Mimetas B.V., Organ-on-a-chip Company, Leiden, The Netherlands

Abstract: Amyotrophic lateral sclerosis (ALS) is a fatal and progressive neurodegenerative disease affecting upper and lower motor neurons with no cure available. Clinical and animal studies reveal that the neuromuscular junction (NMJ), a synaptic connection between motor neurons and skeletal muscle fibers, is highly vulnerable in ALS and suggest that NMJ defects may occur at early stages of the disease. However, mechanistic insight into how NMJ dysfunction relates to the onset and progression of ALS is incomplete, which hampers therapy development. This is, in part, caused by a lack of robust in vitro models. The ability to combine microfluidic and induced pluripotent stem cell (iPSC) technologies has opened up new avenues for studying molecular and cellular ALS phenotypes in vitro. Microfluidic devices offer several advantages over traditional culture approaches when modeling the NMJ, such as the spatial separation of different cell types and increased control over the cellular microenvironment. Moreover, they are compatible with 3D cell culture, which enhances NMJ functionality and maturity. Here, we review how microfluidic technology is currently being employed to develop more reliable in vitro NMJ models. To validate and phenotype such models, various morphological and functional read‐outs have been developed. We describe and discuss the relevance of these read‐outs and specifically illustrate how these read‐outs have enhanced our understanding of NMJ pathology in ALS. Finally, we share our view on potential future directions and challenges.

FIG: Overview of some of the morphological and functional read-outs that can be used

in NMJ-on-a-chip models for studying ALS disease mechanisms. 

Acknowledgements: We thank Dr. Ewout Groen and Prof. Eran Perlson for carefully reading the manuscript, and Frederik Schavemaker for help with preparing the Figures. Work in the laboratory of R.J.P. is supported by the ALS Stichting Nederland (TOTALS, ALS-on-a-Chip) and by the MAXOMOD and INTEGRALS consortia under the frame of E-Rare-3, the ERANet for Research on Rare Diseases.

#Intel Talks With #TSMC, #Samsung to Outsource Some Chip #semi Production https://t.co/nMJIjXsben https://t.co/u8mpOgXf6R

#Intel Talks With #TSMC, #Samsung to Outsource Some Chip #semi Production https://t.co/nMJIjXsben pic.twitter.com/u8mpOgXf6R

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Technology Optimization for #Magnetoresistive RAM (#STT-#MRAM) - Semiwiki https://t.co/f3LCsyUfDq #TCAD #semi https://t.co/emMfRnGxQp

Technology Optimization for #Magnetoresistive RAM (#STT-#MRAM) - Semiwiki https://t.co/f3LCsyUfDq #TCAD #semi pic.twitter.com/emMfRnGxQp

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Low-power #MEMS #microphone https://t.co/A6tcnAt4km #semi https://t.co/CSEfyDEsgm

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[C4P] Spintronics-Devices and Circuits

Call for Papers for a Special Issue of 

IEEE Transactions on Electron Devices on

“Spintronics-Devices and Circuits”

Submission deadline: 30 September, 2021 

Publication date: April 2022

Spintronics is one of the emerging fields for the next-generation nanoscale devices offering better memory and processing capabilities with improved performance levels. It demonstrates great potential in the post-Moore era. Ever since the discovery of Giant Magneto-Resistance (GMR) effect in 1988, spintronics has shown rapid progress. Recent advances have expanded this technology to the entire electronics industry of sensors, memories, oscillators, quantum information processors, computer architecture, brain inspired computing and various other fields. Spintronics is now one of the most researched areas and is on the verge of becoming a mainstream technology. A hard disk drive (HDD) invented by IBM in 1956, now has a global market revenue of approximately $12bn. Other emerging field of application for this technology is magnetic field sensors that showcased a market revenue of ~$19b in 2018. The magnetic memory production at major foundries such as Samsung, Globalfoundries, Western Digital and TSMC marks the adoption of spintronics technology. However, in order to meet the ever-increasing demands of the industry, innovation in terms of modeling, design, materials, processes, circuits and applications are required. This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state-of-the-art in the field of spintronic devices, circuits and new architectures for high performance.

Topics of interest include, but are not limited to:

Materials:

Ferromagnets, Antiferromagnets, 2D material for better spin manipulation and spin logic devices, Heusler alloys, dilute magnetic semiconductors (DMS), half-metallic ferromagnet (HMF)

Transport mechanism:

Spin accumulation, injection and detection in spin devices, spin pumping techniques, angular momentum transportation by spin polarized currents, spin waves, magnons, spin hall effect, spin transfer torque, enhancement in spin diffusion length and coherence time

Spintronics devices:

STT-MRAM, SOT-MRAM, VCMA-MRAM, domain-wall, skyrmions, nano-oscillators, sensors etc. Low power and high-speed switching schemes for spintronic devices.

Optoelectronics and Spintronics:

All-optical switching of magnetization, inverse magnetooptical effects, single shot optical switching, modeling circuit and architecture level design for ultra-fast laser excitation

Memories:

High storage density MRAM, enhancement in power efficiency and speed

In-memory computing:

Spintronics based in-memory computing/ processing circuits/architectures and applications

Quantum Computing:

Quantum information processing, protocol for communication, computation and sensing, algorithms, spin qubit, systems and applications, spintronics-based quantum memories

Neuromorphic computing:

Hardware implementation of neural networks, analog and digital, architectures and applications

Fabrication:

Fabrication and characterization of novel materials and devices, hybrid spintronics integration and fabrication

Spintronics based circuits:

Reconfigurable and programmable spintronics based circuits, Security applications including RNG and PUF, ADC/DAC, reliability and power performance analysis of spintronics based devices and circuits

Submission instructions: Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/publications/authors/author_templates.html
In your cover letter, please indicate that your submission is for this special issue.
Submission site: https://mc.manuscriptcentral.com/ted

The papers must present original material that has not been copyrighted, published or accepted

for publications in any other archival publications, that is not currently being considered for

publications elsewhere, and that will not be submitted elsewhere while under considerations

by the Transactions on Electron Devices.

Guest Editors:

1. Prof. Brajesh Kumar Kaushik, Department of Electronics and Communication Engineering, Indian Institute of Technology Roorkee, INDIA (Lead Guest Editor)

2. Dr. Sanjeev Aggarwal, Everspin Technologies Inc., USA

3. Prof. Supriyo Bandyopadhyay, Department of Electrical and Computer Engineering, VCU College of Engineering, USA

4. Prof. Debanjan Bhowmik, Department of Electrical Engineering, Indian Institute of Technology Delhi, INDIA

5. Dr. Vivek De, Circuits Research Lab, Intel, USA

6. Dr. Bernard Dieny, SPINTEC, IRIG/CEA Grenoble, FRANCE

7. Prof. Wang Kang, School of Microelectronics, Beihang University, CHINA

8. Prof. S.N. Piramanayagam, School of Physical & Mathematical Sciences - Division of Physics & Applied Physics, Nanyang Technological University, SINGAPORE

9. Prof. Kaushik Roy, School of Electrical and Computer Engineering, Purdue

University, USA

10. Prof. Ashwin A. Tulapukur, Department of Electrical Engineering, Indian Institute of Technology Bombay, INDIA

[C4P] New simulation methodologies for next-generation TCAD

Call for Papers for a Special Issue of

IEEE Transactions on Electron Devices on

"New simulation methodologies for next-generation TCAD" 

Submission deadline: February 28, 2021 

Publication date: November 2021

Technology Computer Aided Design is used to simulate semiconductor processes and devices,a field which has become increasingly complex and heterogeneous. Processing of integrated circuits requires nowadays over 400 process steps, and the resultant devices often have a complicated 3D structure and contain various materials. The full device behavior can only be understood by considering effects on all length scales from atomistic (interfaces, defects etc.) over nanometric (quantum confinement, non-bulk properties etc.) to full chip dimensions (strain, heat transport etc.), and time scales from femtoseconds to seconds. Voltages, currents and charges have been scaled to such low levels that electronic noise, statistical effects and process variations have a strong impact. Devices based on new materials (e.g. 2D crystals) and physical principles (ferroelectrics, magnetic materials, qubits etc.) challenge standard TCAD approaches. While the simulation methods developed by the physics community can describe the basic device behavior, they often lack important simulation capabilities like, for example, transient simulations or integration with other TCAD tools and are too slow for daily use. Due to the complexity of semiconductor technology, it becomes more and more difficult to assess the impact of a change in processing or device structure on circuit performance by looking at a single aspect of an isolated device under idealized conditions. Instead a TCAD tool chain is required that can handle realistic device structures embedded in a chip environment. New methodologies are required for all aspects of TCAD to ensure an efficient tool chain covering from atomistic effects to circuit behavior based on flexible simulation models that can handle new materials, device principles and the ensuing large-scale simulations.

This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of TCAD for processing and for device behavior with a focus on new methodologies that improve the tool chain. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices.

Topics of interest include, but are not limited to:
• Artificial Intelligence applied to TCAD

• TCAD device models for
• new materials (2D materials, oxides, organic semiconductors, oxide semiconductors,
nanowire devices etc.)
• new device types (magnetic devices, memristors, spintronics, qubits, sensors etc.)
• physical effects (ferroelectric dielectrics, thermal transport at nanoscale, atomistic
simulation etc.)
• simulation conditions that push the limits of standard TCAD: ballistic transport, THz
frequencies, cryogenic conditions, device degradation, electromagnetic and plasma
waves in active devices, transient simulations, noise and fluctuations, microscopic 
simulation of large power devices

• Process simulation

• Atomistic process simulation to generate structures for atomistic device simulations
(including both interconnects and transistors)
• Gate stack modeling including dipole diffusion
• Stress simulation for nanosheet and forksheet devices and stress simulations
including layout effects
• Topological simulation
• Equipment simulation

• New methods for the TCAD tool chain

• Self-consistent integration of simulation models into the hierarchy
• Device-circuit interaction
• Multi-physics and multi-scale integration
• Efficient use of the data produced along the chain
• Workflow improvements
• Methods that improve the turn-around-time for TCAD simulations

Submission instructions: Manuscripts should be submitted in a double column format
using an IEEE style file. Please visit the following link to download the templates:
http://www.ieee.org/publications_standards/publications/authors/author_templates.html
In your cover letter, please indicate that your submission is for this special issue.

Guest Editors:

1. Prof. Fabrizio Bonani, Politecnico di Torino, Italy
2. Dr. Stephen Cea, Intel Corp., USA
3. Prof. Elena Gnani, University of Bologna, Italy
4. Prof. Sung-Min Hong, GIST, Republic of Korea
5. Dr. Seonghoon Jin, Samsung, USA
6. Prof. Christoph Jungemann, RWTH Aachen, Germany
7. Prof. Xiaoyan Liu, Peking University, China
8. Dr. Victor Moroz, Synopsys, USA
9. Dr. Anne Verhulst, imec, Belgium

[paper] Generalized EKV Charge-based MOSFET Model

A Generalized EKV Charge-based MOSFET Model Including Oxide and Interface Traps

Chun-Min Zhang^a,  Farzan Jazaeri^a,  Giulio Borghello^b,  Serena Mattiazzo^c,  Andrea Baschirotto^d

and Christian Enz^a

Solid-State Electronics

Available online 7 January 2021, 107951

Open Access under a Creative Commons License

DOI: 10.1016/j.sse.2020.107951

a Integrated Circuits Laboratory (ICLAB), École Polytechnique Fédérale de Lausanne (EPFL), Neuchâtel 2000, Switzerland

b Department of Experimental Physics, CERN, Geneva 1211, Switzerland

c Department of Information Engineering, INFN Padova and University of Padova, Padova 35131, Italy

d Microelectronic Group, INFN Milano-Bicocca and University of Milano-Bicocca, Milano 20126, Italy

Abstract: This paper presents a generalized charge-based EKV MOSFET model that includes the effects of trapped charges in the bulk oxide and at the silicon/oxide interface. It is shown that in the presence of oxide- and interface-trapped charges, the mobile charge density can still be linearized but with respect to both the surface potential and the channel voltage. This enables us to derive closed-form expressions for the mobile charge density and the drain current. These simple formulations demonstrate the effects of charge trapping on MOSFET characteristics and crucial device parameters. The proposed charge-based analytical model, including the effect of velocity saturation, is successfully validated through measurements performed on devices from a 28nm bulk CMOS technology. Ultrahigh total ionizing doses up to 1 Grad (SiO2) are applied to generate oxide-trapped charges and activate the passivated interface traps. Despite a small number of parameters, the model is capable of accurately capturing the measurement results over a wide range of device operation from weak to strong inversion. Explicit expressions of device parameters also allow for the extraction of the oxide- and interface-trapped charge density.

Fig: Energy band diagrams illustrating interface charge trapping in bulk n- (a) and pMOSFETs (b) in inversion. The quasi-Fermi level of the minority carriers, 𝐸𝐹𝑛 or 𝐸𝐹𝑝, is split from that of the majority carriers 𝐸𝐹 by the channel voltage 𝑉𝑐ℎ

Acknowledgements: The authors would like to thank the EP-ESE group at CERN, especially Dr. Federico Faccio, for the continuous support in radiation measurements and the interesting discussions about data analysis. This work was supported in part by the Swiss National Science Foundation (SNSF) through the GigaradMOST project under grant number 200021_160185 and in part by the Istituto Nazionale di Fisica Nucleare (INFN) through the ScalTech28 Project.

15 Biggest #semi Companies in the World https://t.co/hWRDbS6Mjw https://t.co/LgUQaDw0Mg

15 Biggest #semi Companies in the World https://t.co/hWRDbS6Mjw pic.twitter.com/LgUQaDw0Mg

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Junior Scientist (PhD candidate) Positions

♦ Ferroelectric Vertical Nanowire Field Effect Transistors Development
at NaMLab, Dresden (Germany) and at University of Bordeaux (France)

Contact:

Dr.-Ing. Jens Trommer, NaMLab gGmbH 

Dr. Marina Deng, University of Bordeaux 

♦ Millimetre-wave (mmWave) Device; Silicon Waveguide Technologies for future > 100 GHz Applications
at School of Engineering, UC Louvain 
Contact:

Prof. Dimitri Lederer, UC Louvain 

♦ Modeling of Single Photon Avalanche Photodiode Temporal Response
at Institut d'Optique Graduate School, Univ. Saint-Etienne and STM (Crolles)
Contact:

Prof. Raphael Clerc, Univ. Saint-Etienne

Dr. Ing. Denis Rideau, STM

Virtual Si Museum /2101/ Electron Devices Time Line

my own view on the electron devices time line. The electron devices scaling: from a single vacuum tube, a BJT, TTL digital ICs to 68719476736 devices in a NAND flash memory card. If you have something else to add, just let me know:

REF:

1. Vacuum Tube GE 9-22 188-5
2. 2N2905A BJT - PNP, -60 V, -600 mA, 600 mW, TO-39
3. TTL 74F00 IC - 5V, quad 2-input NAND gate; series F (=fast) introduced in 1978
4. 64Gb NAND flash memory card

[Opinion] Money's not the problem for Europe's #semi rebuild https://t.co/5zyzOORFMi https://t.co/UYXWPxzXac

[Opinion] Money's not the problem for Europe's #semi rebuild https://t.co/5zyzOORFMi pic.twitter.com/UYXWPxzXac

— Wladek Grabinski (@wladek60) January 6, 2021

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January 06, 2021 at 02:13PM
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[paper] Perspective of Ultra-Scaled CMOS

Ab initio perspective of ultra-scaled CMOS

from 2D-material fundamentals to dynamically doped transistors

Aryan Afzalian 

Open Access; npj 2D Mater Appl 5, 5 (2021) 

DOI: 10.1038/s41699-020-00181-1 

Abstract: Using accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

Fig: Switching energy vs delay (EDP) of high-performance MOSFET and D2-FET inverters. EDP of 1ML-HfS2 high-performance inverter cells, at various VDD (0.4 V to 0.7 V), made of L = 5 nm and L = 3 nm stacked DG MOSFETs (5 ribbons/device) and L = 0 nm and L = nm stacked SG-D2-FETs (nine ribbons/device). The EDP performance of Si HP inverter cells made of L = 12 nm stacked Si-GAA MOSFETs (tS = 5 nm, 8 wires/device) and L = 5 nm stacked Si SG-D2-FETs (tS = 3 nm, 7 ribbons/device) are also shown for comparison. The inverters are loaded with a 50 contacted-gate-pitch-long metal line (https://irds.ieee.org/editions/2018). The extrinsic capacitances of the cell layout are also included in the load capacitance. IOFF = 10 nA/μm. ΔL = 4 nm for the D2-FETs.

Acknowledgements: Part of the computing resources and services used in this work were provided by the VSC (Flemish Supercomputer Center), funded by the Research Foundation–Flanders (FWO) and the Flemish Government. The author acknowledges the support of Dr. G. Gaddemane for the DFTP e-ph coupling calculations.

Open Access: This article is licensed under a Creative Commons Attribution 4.0 International License

[paper] NESS Open-Source TCAD Environment

Cristina Medina-Bailon, Tapas Dutta, Fikru Adamu-Lema, Ali Rezaei, Daniel Nagy,

Vihar P. Georgiev, and Asen Asenov

Nano-Electronic Simulation Software (NESS): 

A Novel Open-Source TCAD Simulation Environment

Journal of Microelectronic Manufacturing

Vol 3 (4) : 20030407 2020

DOI:  10.33079/jomm.20030407

Abstract: This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software (NESS) which is currently under development at the Device Modeling Group of the University of Glasgow. NESS is designed with the main aim to provide an open, flexible, and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models. Currently, NESS is organized into two main components: the structure generator and a collection of different numerical solvers; which are linked to supporting components such as an effective mass extractor and materials database. This paper gives a brief overview of each of the components by describing their main capabilities, structure, and theory behind each one of them. Moreover, to illustrate the capabilities of each component, here we have given examples considering various device structures, architectures, materials, etc. at multiple simulation conditions. We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.

Fig: Randomly generated atomistic device considering random discrete dopants (RDD) and metal gate granularity (MGG) in the NESS simulation domain

Acknowledgments: This project was initiated by the European Union Horizon 2020 research and innovation programme under grant agreement No. 688101 SUPERAID7 and has received further funding from EPSRC UKRI Innovation Fellowship scheme under grant agreement No. EP/S001131/1 (QSEE), No. EP/P009972/1 (QUANTDEVMOD) and No. EP/S000259/1 (Variability PDK for design based research on FPGA/neuro computing); and from H2020-FETOPEN-2019 scheme under grant agreement No.862539-Electromed-FET OPEN. The coauthors would like to thank Dr. Carrillo-Nuñez, Dr. Lee, Dr. Berrada, Dr. Badami, and Dr. Duan for their former contribution to NESS; as well as Dr. Donetti for the possibility of using the 1DMC tool. 

[paper] Analysis of 2D Transistors

Guoli Li, Zizheng Fan, Nicolas André, Member, IEEE, Yongye Xu, Ying Xia, Benjamín Iñíguez, Fellow, IEEE, Lei Liao, Senior Member, IEEE, and Denis Flandre, Senior Member, IEEE

Non-Linear Output-Conductance Function for Robust Analysis of Two-Dimensional Transistors

IEEE Electron Device Letters, 42(1), pp.94-97

DOI: 10.1109/LED.2020.3042212

Abstract: In this work, we explore the outputconductance function (G-function) to interpret the device characteristics of two-dimensional (2D) semiconductor transistors. Based on analysis of the device output conductance, the carrier mobility, and the channel as well as contact resistance are extracted. Thereafter the currentvoltage (IV) characteristics of black phosphorous (BP) and MoS2 transistors from room to low temperature are modeled and compared to experiments. The G-function model proves its reliability and accuracy in parameter extraction and IV modeling of 2D transistors, regardless of the n- or p- type, the short- or long-channel and the Schottky or Ohmic contact. Moreover, this works shows its high potential in the device modeling and further circuit design of the 2D transistors, requiring only few parameters and simulating precise IV characteristics.

G-Function Model (for Linear and Non-Linear Cases), the Rch and Rc can be calculated for both the Ohmic and Schottky contacts in the 2D transistors: 

Aknowlegement: This work was supported in part by the National Key Research and Development Program of China under Grant 2018YFA0703700; in part by the National Natural Science Foundation of China under Grant 61925403, Grant 61851403, and Grant 62004065; in part by the Hunan Natural Science Foundation under Grant 2020JJ5087; and in part by the Technology Program (Major Project) of Changsha under Grant kq1902042.

[paper] Aged MOSFET and Its Compact Modeling

F. A. Herrera, M. Miura-Mattausch, T. Iizuka, H. Kikuchihara, H. J. Mattausch and H. Takatsuka, Universal Feature of Trap-Density Increase in Aged MOSFET and Its Compact Modeling

SISPAD, Kobe, Japan, 2020, pp. 109-112

DOI: 10.23919/SISPAD49475.2020.9241674

Abstract: Our investigation focuses on accurate circuit aging prediction for bulk MOSFETs. A self-consistent aging modeling is proposed, which considers the trap-density Ntrap increase as the aging origin. This Ntrap is considered in the Poisson equation together with other charges induced within MOSFET. It is demonstrated that a universal relationship of the Ntrap increase as a function of integrated substrate current, caused by device stress, can describe the MOSFET aging in a simple way for any device-operating conditions. An exponential increase with constant and unitary slope of the Ntrap is found to successfully predict the aging phenomena, reaching a saturation for high stress degradation. The model universality is verified additionally for any device size. Comparison with existing conventional aging modeling for circuit simulation is discussed for demonstrating the simplifications due to the developed modeling approach

Fig: Schematic of the density-of-state (DOS) model as a function of the state-energy difference from the conduction-band edge, with two parameters gc and Es introduced as new model features.

[paper] Compact Modeling of Carbon Nanotube FETs

A Compact and Robust Technique for the Modeling and Parameter Extraction 

of Carbon Nanotube Field Effect Transistors

Laura Falaschetti¹, Davide Mencarelli¹, Nicola Pelagalli¹, Paolo Crippa¹, Giorgio Biagetti¹,

Claudio Turchetti¹,George Deligeorgis², and Luca Pierantoni¹

Electronics 2020, 9(12), 2199; 

DOI: 10.3390/electronics9122199

1 Department of Information Engineering, Marche Polytechnic University, 60131 Ancona, Italy
2 Microelectronics Research Group (MRG/IESL), FORTH, Greece

Abstract: Carbon nanotubes field-effect transistors (CNTFETs) have been recently studied with great interest due to the intriguing properties of the material that, in turn, lead to remarkable properties of the charge transport of the device channel. Downstream of the full-wave simulations, the construction of equivalent device models becomes the basic step for the advanced design of high-performance CNTFET-based nanoelectronics circuits and systems. In this contribution, we introduce a strategy for deriving a compact model for a CNTFET that is based on the full-wave simulation of the 3D geometry by using the finite element method, followed by the derivation of a compact circuit model and extraction of equivalent parameters. We show examples of CNTFET simulations and extract from them the fitting parameters of the model. The aim is to achieve a fully functional description in Verilog-A language and create a model library for the SPICE-like simulator environment, in order to be used by IC designers.

Figure 2. 3D structure of CNTFET. Reprinted, with permission, from [I and II]

Aknowlwgement: This research was supported by the European Project “NANO components for electronic SMART wireless circuits and systems (NANOSMART)”, H2020—ICT-07-2018-RIA, n. 825430.

References:

[I] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part I: Model of the Intrinsic Channel Region. IEEE Trans. Electron Devices 2007, 54, 3186–3194

[II] Deng, J.; Wong, H.P. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including non-idealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking. IEEE Trans. Electron Devices 2007, 54, 3195–3205