Wednesday, July 8, 2020

[paper] compact nanowire JAM-MOSFET model

Kamalaksha Baral, Prince Kr Singh, Sanjay Kumar, Manas Ranjan Tripathy,
Ashish Kr Singh, Sweta Chander and S JitA
2-D compact DC model for engineered nanowire JAM-MOSFETs 
valid for all operating regimes
Semiconductor Science and Technology, Vol. 35, No. 8

Abstract: This manuscript reports a 2-D compact analytical model for DC characteristics under all possible regimes of operations of a cylindrical gate (CG) nanowire junctionless accumulation mode (JAM) MOSFET including the effects of various device engineering techniques. Superposition technique with appropriate boundary conditions has been used to solve 2-D Poisson’s equation considering both free/accumulation and depletion charges. The minimum potential concept has been used to conceive the threshold voltage formulation considering the effects of structural and electrical quantum confinements. An optimized device model has been formulated incorporating various device engineering. The potential model could also be used for potential modeling of doped inversion mode MOSFETs. Complete drain current including gate induced drain leakage (GIDL) has been derived from the potential model. Drain current has been derived individually for different regions. Further the effects of temperature and trapped interface charges have been included in the model. A 3-D commercial TCAD has been used to validate the model results of our proposed device. 
Fig: A 2-D cross-sectional view of cylindrical gate nanowire
junctionless accumulation mode MOSFET 

Tuesday, July 7, 2020

[mos-ak] [Final Program] MOS-AK Workshop at ESSDERC/ESSCIRC,Grenoble, Sept.14, 2020

Arbeitskreis Modellierung von Systemen und Parameterextraktion
Modeling of Systems and Parameter Extraction Working Group
MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event
Grenoble, September 14, 2020

Together with local ESSDERC/ESSCIRC Organization Team as well as International MOS-AK Board of R&D Advisers and all the Extended MOS-AK TPC Committee, we have the pleasure to invite to consecutive, 18th MOS-AK Workshop as ESSDERC/ESSCIRC Virtual Educational Event

Scheduled, subsequent 18th MOS-AK Workshop organized as an integral part of the ESSDERC/ESSCIRC Confernces, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA FOSS and commercial tool developers and vendors. 

MOS-AK Workshop Program
includes 8 webinars by the internationally recognized compact modeling experts: 
W_1 Qucs-S and QucsStudio for compact device modelling.
Mike Brinson
London Metropolitan University (UK)
W_2 Memory Modeling for Neuromorphic Computing
Mansun Chan
Hong Kong University of Science & Technology (HK)
W_3 Compact Modeling of Oxide and Organic Thin Film Transistors
Benjamin Iniguez
Universitat Rovira i Virgili, Tarragona (SP)
W_4 Latest developments of L-UTSOI: 
A compact model dedicated to low-power analog and digital applications in FDSOI technologies
Sébastien Martinie
CEA-Leti, Grenobel (F)
W_5 Overview of the ASM-HEMT Model
Yogesh Chauhan
IIT Kanpur (IN)
W_6 ngspice - current status and developments
Holger Vogt
Fraunhofer IMS, Duisburg (D)
W_7 LDMOS compact modeling and the PSPHV model
Kejun Xia
W_8 Nanowire Junctionless ISFETs
Ashkhen Yesayan
Institute of Radiophysics and Electronics National Academy of Sciences (AM)

The MOS-AK program is available online: <>

Virtual Educational Event at ESSDERC/ESSCIRC  
(any related enquiries can be sent to

W.Grabinski on the behalf of International MOS-AK Committee

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Monday, July 6, 2020

[paper] TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions

Yu He, Wei-Choon Ng and Lee Smith
TCAD modeling of neuromorphic systems based on ferroelectric tunnel junctions
J Comput Electron (2020)
DOI: 10.1007/s10825-020-01544-z

Abstract: A new compact model for HfO2-based ferroelectric tunnel junction (FTJ) memristors is constructed based on detailed physical modeling using calibrated TCAD simulations. A multi-domain configuration of the ferroelectric material is demonstrated to produce quasi-continuous conductance of the FTJ. This behavior is demonstrated to enable a robust spike-timing-dependent plasticity-type learning capability, making FTJs suitable for use as synaptic memristors in a spiking neural network. Using both TCAD–SPICE mixed-mode and pure SPICE compact model approaches, we apply the newly developed model to a crossbar array configuration in a handwritten digit recognition neuromorphic system and demonstrate an 80% successful recognition rate. The applied methodology demonstrates the use of TCAD to help develop and calibrate SPICE models in the study of neuromorphic systems.
Fig: Electric field–polarization relationship. Solid line: multi-domain simulation; dashed line: single-domain simulation; dot: measurement 

[paper] Real-Time Monitoring of Cell Cultures with Nickel Comb Capacitors

Kociubiński, Andrzej, Dawid Zarzeczny, Maciej Szypulski, Aleksandra Wilczyńska, Dominika Pigoń, Teresa Małecka-Massalska, and Monika Prendecka
Real-Time Monitoring of Cell Cultures with Nickel Comb Capacitors
Informatyka, Automatyka, Pomiary w Gospodarce i Ochronie Środowiska 
10, no. 2 (2020): 32-35
DOI: 10.35784/iapgos.1564

Abstract: The  aim  of  the  study  was  to  present  a  method  for  assessing  the condition of  cell  culture  by  measuring  the  impedance  of  cells  cultured  in  the presence of nickel. For this purpose, an impedance measurement technique using nickel comb capacitors was used. The capacitor electrodes were made using a thin film magnetron sputtering. In the experimental part, the culture of cells of mouse fibroblasts on the prepared substrate was performed. The cell culture lasted 43 hours and showed that the presented technique allows it to be used to analyze the effect of nickel on cells.
Fig: The final nickel electrode array with 8 wells

IEEE Events Reveal #Future #Memory And #Storage #paper

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With #128 #Core #Chip, Ampere Seeks to Deliver Reliable Advances [@EETimes] #paper

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July 06, 2020 at 11:45AM

@ETH integrates #photonics and #electronics on one #chip #paper

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July 06, 2020 at 11:42AM