[mos-ak] [Announcement and Call for Papers] Spring 2015 MOS-AK Workshop at DATE

 Spring 2015 MOS-AK Workshop at DATE

  Grenoble March 12, 2015

  Announcement and Call for Papers 

 

 Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, local workshop chairs Patrick Martin, CEA (F) and Benjamin Iniguez, URV (SP) as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the Spring MOS-AK Workshop which will be held in Grenoble (F) at the DATE Conference. The event is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Venue:

ALPEXPO-ALPES Congres

Parc Événementiel de Grenoble

Avenue d'Innsbruck - CS 52408

38034 Grenoble cedex 2; France

Important Dates:

Call for Papers - December 2014

2nd Announcement - January 2015

Final Workshop Program - February. 2015

MOS-AK Workshop - Friday, March 12, 2015

08:30 - 09:00 - On-site Registration 

09:00 - 11:00 - Morning MOS-AK Session

11:00 - 12:00 - CM Standardization Panel

12:00 - 13:00 - Lunch

13:00 - 16:00 - Afternoon MOS-AK Session 

Topics to be covered include the following:

• Advances in semiconductor technologies and processing
  
• Compact Modeling (CM) of the electron devices
  
• Verilog-A language for CM standardization
  
• New CM techniques and extraction software
  
• Open Source TCAD/EDA modeling and simulation
  
• CM of passive, active, sensors and actuators
  
• Emerging Devices, CMOS and SOI-based memory cells
  
• Microwave, RF device modeling, high voltage device modeling
  
• Nanoscale CMOS devices and circuits
  
• Technology R&D, DFY, DFT and IC Designs
  
• Foundry/Fabless Interface Strategies

Online Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form 

(any related inquiries can be sent to wladek@grabinski.ch)
http://www.mos-ak.org/grenoble_2015/abstracts.php

Free online workshop registration:

(any related inquiries can be sent to wladek@grabinski.ch)

http://www.mos-ak.org/grenoble_2015/registration.php

Postworkshop publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK/GSA Committee

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IEEE Magazine Pays Special Tribute to Professor Yannis Tsividis

  To Electrical Engineering Professor Yannis Tsividis’ long roster of distinguished achievements, add one more: the latest issue of IEEE Solid-State Circuits Magazine is devoted to his remarkable career and strong influence in advancing analog and mixed-signal integrated circuits.

  Tsividis, recently named the Edwin Howard Armstrong Professor of Electrical Engineering at Columbia, created the first fully integrated mixed-signal metal-oxide-semiconductor (MOS) operational amplifier, which became key to pulse-code modulation (PCM) voice codecs for telephony and helped spur the industry toward mixed analog-digital MOS integrated circuits for communications. The work of Tsividis and his students has resulted in multiple patents around the world and extensive applications at the device, circuit, and system levels as well as in enhanced computer simulation.

  Of the honor, Tsividis said, “I was moved by the kind words of my colleagues and former students, and delighted at the opportunity to tell my story.”

[read more...]

postdoctoral positions in Compact Modeling in Tarragona (Spain)

As Professor in the Universitat Rovira i Virgili (Tarragona, Catalonia, Spain), I am going to apply for two or three postdoctoral position (funded by the Spanish Ministry and the Catalan Government) related to our research projects about Compact Modeling of semiconductor devices: in particular, the European Union -funded "DOMINO" project (of which I am the coordinator, and which targets modeling of organic and oxide TFTs), and our national projects addressing the modeling of GaN HEMTs and nanowire MOSFETs.

The candidate should be a person who holds a PhD as awarded within the five years prior to the date when the period for presentation of application forms closes. If the candidate does not hold a PhD yet, the deadline to be awarded a PhD is the date of publication of the Awarding Resolution  web site.

The candidate should have enough research experience in the field of semiconductor devices, and must have a very good knowledge of the physics of electron devices. The research project to be carried out can be adapted to the candidate's profile. In any case, it will be related to the research projects in which we participate. Our contribution in these projects is the physics and modeling (in particular compact modeling) of the novel devices addressed by our projects: organic and oxide Thin Film Transistors (TFTs), GaN HEMTs, nanowire FETs, multi-gate MOSFETs (FinFETs, DG MOSFETs,...), ...

The postdoc positions, which will be a contract, will have a duration of 2-3 years. The net salary will be around 1900 Euro/months.

The postdoctoral researcher will work in the compact device team, led by Prof Benjamin Iñiguez, belonging to the Nanoelectronics and Photonics Systems Group (NEPHOS) in the Department of Electronic, Electrical and Automatic Control Engineering of the Universitat Rovira i Virgili (URV). This team is a worldwide well recognized pioneering group in the development of compact models for advanced and emerging semiconductor devices. The team has participated in a number of European Union funded projects aout this topic and has led some of them.

Interested applicants should send me their CV by e-mail.
DEADLINE TO RECEIVE APPLICATIONS: January 25 2015

MY E-MAIL ADDRESS IS: benjamin.iniguez@gmail.com

Address:
Benjamin Iñiguez
Nanoelectronics and Photonics Systrems Group (NEPHOS)
Department of Electronic Engineering
Universitat Rovira i Virgili (URV)
Avinguda dels Paisos Catalans 26
43007 Tarragona
SPAIN.

About Tarragona:

Tarragona is located on the Mediterranean, in the heart of the Costa Daurada, in the south of Catalonia, about 100 Km south from Barcelona. Tarragona is well connected to Barcelona by highway, and frequent trains and buses. It has also a direct bus connection with Barcelona Airport. Besides, it has high-speed rail connection with Madrid and Barcelona.

Tarraco (the Roman name for Tarragona) was one of the most important cities in the Roman Empire. F On 30 November 2000, the UNESCO committee officially declared the Roman archaeological complex of Tàrraco a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public. Among the citizens of Tarragona, it has moreover fomented knowledge of, pride in and respect for the city.

Speaking about Tarraco’s climate, the famous Roman poet Virgil wrote: “The climate blends and confuses the seasons singularly, so that all the year seems an eternal spring.” Thanks to its temperate climate, with an average yearly temperature of 23ºC, its clean beaches with fine and gloden sand, and its singular artistic and architectural heritage, Tarragona is one of the most important tourism hubs in Europe. The city has a population of 120,202 inhabitants

Call for Papers PRIME 2015

 The PRIME 2015 Call for Papers is available at: 

 http://web.eng.gla.ac.uk/prime2015/static/images/PRIME2015CFPv2.pdf 

The purpose of the PRIME Conference is to grow Ph.D students' experience in the early stage of their career by creating a connection between academic world and companies.

A Workshop is organized for all conference participants on June 29th. Moreover, a Company Fair is organized for all conference participants, to create a connection between major companies in Electronics/Microelectronics and Ph. D students.

PRIME 2015 topics of interest include, but are not limited, to:

• Micro/nanoelectronics
• Semiconductors
• Analog and Digital Signal Processing
• Computer Aided Design
• Analog, Digital, Mixed-Signal and RF IC Design
• Integrated Power ICs
• RF, Microwave and Millimeterwave Circuits
• VLSI and SoC Applications
• Visual Signal Processing
• Sensor Systems and MEMS
• Energy Scavenging
• Technical trends and challenges
• Electronic Skin

[read more...]

Meet with Silvaco at IEDM 2014

Silvaco will showcase at IEDM products for applications such as displays, power devices, optical devices, advanced CMOS process development, radiation & soft error reliability, analog and memory design.

• Victory Process, Device and Stress for 1D, 2D and 3D TCAD simulation for applications such as TFT displays, IGBT power devices, lasers, image sensors, advanced CMOS devices such as FDSOI and FinFETs, radiation and soft error reliability simulation
• Clever for 3D parasitic RC extraction with the highest accuracy capacitance extraction for application such as TFT design, FinFET SRAM analysis
• Utmost IV for creating SPICE models for any device type including TFT, UOTFT, BSIM-CMG for FinFETs, HSIM-HV2 for high voltage devices
• Affordable and complete custom design flow including schematic entry, layout, simulation, analysis and verification ideally suited to analog, power management applications and for process nodes such as 65nm/40nm that are key targets for Internet of Thing (IoT) designs
• SmartSpice for simulation of circuits such as analog/mixed-signal, HSIO, RF, SRAM, standard cells, TFT panels, power ICs and for which recent performance enhancement benchmark data will be shared
• SmartSpice for library, memory and critical path characterization with built-in optimizers and circuit rubber-banding capability, having achieved 16nm FinFET model certification and includes PODE and ETMI reliability model support
• SmartSpice Soft Error Reliability capability that is used to analyze the impact of Single Event Effects (SEE) on circuit performance, an increasingly important challenge at 20nm and below technology nodes 

More information at their website.

[mos-ak] FOSDEM 2015 Electronic Design Automation Devroom Call for Participation

 This is the call for participation in the FOSDEM 2015 devroom on Free/Open Source Software (FOSS) Electronic Design Automation (EDA) tools, to be held on Sunday 1 February 2015 in Brussels, Belgium. We are looking for contributions under the form of talks covering the following main topics:

• Printed Circuit Board (PCB) design tools (e.g. KiCad and gEDA)
  
• High-level modelling tools for PCB and Hardware Description Language (HDL) design (e.g. Libre-FDATool)
  
• Analogue and digital simulators (e.g. ngspice, Qucs, Gnucap, Xyce, GHDL, Icarus and Verilator)
  
• Inter-project opportunities for collaboration

We hope to provide an opportunity for attendees to bring themselves up to date on the latest FOSS EDA developments, share knowledge and identify opportunities to collaborate on development tasks.

The submission process

Please submit your proposals at https://penta.fosdem.org/submission/FOSDEM15 before 1 December 2014.

If you already have a Pentabarf account (for example as a result of having submitted a proposal in the past), make sure you use it to log in and submit your proposal. Do not create a new account if you already have one. Please provide a bit of information about yourself in Person -> Biography. When you submit your proposal (creating an "Event" in Pentabarf), make sure you choose the "Electronic design automation devroom" in the track drop-down menu. Otherwise your proposal might go unnoticed. Fill in at least a title and abstract for the proposed talk and a suggested duration. Bear in mind that a lot of the value in these meetings comes from the discussions, so please be reasonable regarding the duration of the talk.

Important dates

• 1 December 2014: deadline for submission of proposals
  
• 15 December 2014: speakers notified
  
• 30 December 2014: schedule published at https://fosdem.org/
  
• 1 February 2015: devroom day
  

Recordings

The FOSDEM organisers hope to be able to live-stream and record all the talks. The recordings will be published under the same licence as all FOSDEM content (CC-BY). Only presentations will be recorded, not informal discussions and whatever happens during the lunch break. By agreeing to present at FOSDEM, you automatically give permission to be recorded. The organisers will agree to make exceptions but only for exceptional and well-reasoned cases.
Mailing list

Feel free to subscribe to the mailing list of the EDA devroom to submit ideas, ask questions and generally discuss about the event.

Spread the word!
This is the first EDA devroom at FOSDEM. Let's make sure as many projects and developers as possible are present. Thanks!

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[mos-ak] [Final Program] 7th International MOS-AK Workshop; December 12, 2014 at Berkeley

 7th International MOS-AK Workshop

 Berkeley Friday, Dec. 12, 2014 

 Final Program  

 

 Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the 7th consecutive International MOS-AK Workshop which will be held at Berkeley, California, USA. The event is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/Spice modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool vendors. 

Venue:

Room 540 in Cory Hall

EECS Department

University of California, Berkeley

Final MOS-AK Workshop Program  
http://www.mos-ak.org/berkeley_2014/

Free on-line workshop registration:
http://www.mos-ak.org/berkeley_2014/registration.php

Postworkshop publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK/GSA Committee

WG181114

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