Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF

semiconductor device measurement and modeling 

Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:

• Small scale silicon industry
• Power silicon industry and RF Power

Common topics to both Tracks:

• Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.

CMOS Track:

• Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
• DC characterization for emerging nano-technologies
• Flicker Noise and Random Telegraph Noise
• Spice model libraries optimization for dedicated application

Power & RF Power Track:

• High Power Devices measurement
• III-V devices spice model (DynaFET)
• Nonlinear Component characterization
• Non-50ohm Load Pull solution – Maury

Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.

Country	City	Date	More Information
FR	Grenoble	18 September 2014	Register here
FI	Helsinki	23 September 2014	Register here
DE	Munich	30 September 2014	Register here
DE	Dresden	2 October 2014	Register here
CH	Lausanne	14 October 2014	Register here
BE	Leuven	16 October 2014	Register here
NL	Eindhoven	17 October 2014	Register here
SW	Goteborg	28 October 2014	Register here
UK	Cambridge	30 October 2014	Register here
FR	Les Ulis	6 November 2014	Register here

 

 

i-MOS version 201407 release

 The i-MOS team has announced new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201407. Through the Developer module launched in April, the UMEM model for organic thin film transistors has been integrated with i-MOS for users' evaluations and applications. Another model implemented is the BSIM4 (version 4.0.0), together with model collections from the Predictive Technology Models.  

Any comments and other equerries can be addressed to
Lining Zhang,
PhD i-MOS Project Manager
The Hong Kong University of Science & Technology

[SISPAD] Compact Modeling Worksops - Enabling Better Insight of Device Features - Monday, September 8, 2014

 SISPAD Compact Modeling Workshop
 Enabling Better Insight of Device Features 

 Monday, September 8, 2014

 Workshop Program

09:15 - 09:20: Opening 

09:20 - 10:00: J. Takeya (University of Tokyo, Japan): invited Physics of Charge Transport in Organic Field-Effect Transistors
10:00 - 10:40: C. Jungemann (RWTH Aachen University, Germany): invited Validity of Macroscopic Noise Models in the Case of High-Frequency Bipolar Transistors

10:40 - 11:00: break

11:00 - 11:40: N. Goldsman (University of Maryland, USA): invited Key Issues in the Modeling of SiC Electronic Devices
11:40 - 12:10: C. Ma (Hiroshima University, Japan): invited Universal Model of the Negative Bias Temperature Instability (NBTI) Effect for Circuit Aging Simulation

12:10 - 12:30: poster presentations

• P. X. Tran (International University, Vietnam) A Comprehensive Model for the Changing I-V Characteristics of raphene Transistors 
• M. Ghittorelli, F. Torricelli, Z. M. Kovacs-Vajna, and L. Calalongo (University of Brescia, Italy) Accurate Modeling of Amorphous Indium-Gallium-Zinc-Oxide TFTs Deposited on Plastic Foil 
• S. Sato, Y. Omura, and A. Mallik (Kansai University, Japan) Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-Wire Tunnel FET 
• H. Miyamoto, H. Zenitani, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, and T. Nakagawa (HU & AIST, Japan) Consistent Compact Modeling of MOSFETs from Bulk to Double-Gate Structures

12:30 - 13:50: lunch

13:50 - 14:30: D. Warning (Creative Chips GmbH, Germany): invited NGSPICE – an Open Platform for Modeling and Simulation
14:30 - 15:00: A. Schaldenbrand (Cadence Design Systems, Japan): invited Benefits of Verilog-A for Behavioral Modeling and Compact Modeling
15:00 - 15:30: P. Lee (Micron Memory Japan, Inc.): invited Compact Model Coalition: World-Wide Model Standardization for an Expanding Industry

15:30 - 15:40: break

15:40 - 16:00: F. Torricelli, M. Ghittorelli, M. Rapisarda, L. Mariucci, S. Jacob, R. Coppard, E. Cantatore, Z. M. Kovacs-Vajna, and L. Colalongo (Unviersity of Brescia, Italy) Analytical Drain Current Model of Both p- and n-Channel OTFTs for Circuit Simulation
16:00 - 16:20: T. Nakagawa, T. Sekigawa, M. Hioki, Y. Ogasahara, H. Koike, H. Zenitani, H. Miyamoto, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, H. Oda, and N. Sugii (AIST, HU, LEAP, Japan) Parameter-Extraction Strategy of Ultra-Thin Silicon and BOX Layer MOSFETs for Low Voltage Applications
16:20 - 16:40: T. Mizoguchi, T. Naito, Y. Kawaguchi, and W. Hatano (Toshiba, Japan) Compact Modeling of GaN-MISFET for Power Applications
16:40 - 17:00: T. Yamamoto and H. Kato (Denso, Japan) Analysis and Modeling of Injection Enhanced Insulated Gate Bipolar Transistor

17:00: Closing

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical program, tutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.

The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society

We hope to see you in Venice

Best Regards  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC 2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come

ESSCIRC PLENARY TALKS
Hooman Darabi, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers

Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios

ESSDERC PLENARY TALKS
Umesh Mishra, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 

Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS

Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers (Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland

ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era (Full Day) Organizer: Maud Vinet, CEA LETI, France

RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications (Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

[mos-ak] 12th MOS-AK Workshop at the ESSDERC/ESSCIRC Conference in Venice

 Autumn MOS-AK Workshop in Venice 

 

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the 12th consecutive MOS-AK at the ESSDERC/ESSCIRC Conference.

Venue:

Palazzo del Casinò

Lungomare Marconi, 30

30126 Venice Lido, Italy

Important Dates:

Call for Papers - May 2013
2nd Announcement - June 2014
Final Workshop Program - Aug. 2014
MOS-AK Workshop - Friday, Sept. 26, 2014

 8:30 -  9:00 - On Site Registration

 9:00 - 12:00 - Morning MOS-AK Session

12:00 - 13:00 - Buffet Lunch  

13:00 - 16:00 - Afternoon MOS-AK Session

Topics to be covered include the following:

Advances in semiconductor technologies and processing

Compact Modeling (CM) of the electron devices

Verilog-A language for CM standardization

New CM techniques and extraction software

Open Source TCAD/EDA modeling and simulation

CM of passive, active, sensors and actuators

Emerging Devices, CMOS and SOI-based memory cells

Microwave, RF device modeling, high voltage device modeling

Nanoscale CMOS devices and circuits

Technology R&D, DFY, DFT and IC Designs

Foundry/Fabless Interface Strategies

Abstract Submission:

Authors should submit an abstract using on-line MOS-AK submission form (any related enquiries can be sent to abstracts@mos-ak.org)

Postworkshop publications:

selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK/GSA Committee

[WG 052014]

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IJNM Call for Papers

Advances in simulation-driven modeling and optimization of microwave/RF circuits

IJNM Call for Papers

Computer-aided modeling and design of microwave/radio frequency (RF) devices and circuits have undergone tremendous developments in the past decade. The complexity of today's devices and circuits renders electromagnetic (EM) simulation a sine qua non in the microwave design process. That said, EM-driven design poses significant challenges, mostly due to the high computational cost of accurate, high-fidelity simulation. The availability of massive computational resources does not always translate into design speedup because of the need to account for interactions between devices and their surroundings as well as multi-physics (e.g., EM-thermal) effects. Not surprisingly, traditional design optimization procedures that directly utilize EM-simulated responses typically fail or are impractical. As a consequence, there is growing interest in alternative optimization and modeling methodologies, especially ones that exploit computationally cheap surrogate models.

This Special Issue focuses on the current state of the art and future directions in microwave and RF design. Papers on software engineering and practical applications aspects are also encouraged. Suitable topics for this Special Issue therefore include but are not limited to

• surrogate-based modeling and optimization methods including space mapping;
• knowledge-based and tuning methodologies;
• global optimization, evolutionary algorithms, particle swarm optimization, and so on;
• multi-objective optimization;
• adjoint-sensitivities for efficient gradient-based optimizers;
• optimization techniques for nonlinear circuits;
• software architectures for optimization-oriented design;
• automated design optimization using EM simulators;
• optimization for inverse EM problems;
• neural network approaches; and
• optimization for discrete problems.

Manuscripts for this Special Issue should adhere to the requirements for regular papers of the IJNM as specified in the Author Guidelines at http://onlinelibrary.wiley.com/journal/10.1002/(ISSN)1099-1204/homepage/ForAuthors.html

Potential contributors may contact the guest editor to determine the suitability of their contribution to the Special Issue. All manuscripts should be submitted via the IJNM's manuscript website http://mc.manuscriptcentral.com/ijnm, with a statement that they are intended for this Special Issue.

Manuscript submission deadline: January 31, 2015

Prof. Slawomir Koziel
Engineering Optimization and Modeling Center, 
School of Science and Engineering, 
Reykjavik University, Reykjavik, Iceland

1. 
   

[mos-ak] [Summary] Spring MOS-AK Workshop in London

 MOS-AK Compact Modeling Workshop

 London Metropolitan University

 March 28-29, 2014 London

 

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual spring compact modeling workshop on March 28-29, 2014 at London Metropolitan University. The event received full sponsorship from leading industrial partners including Agilent Technologies, MOSIS Services and Tanner EDA. The technical MOS-AK program promoters included Eurotraining, IET, IEEE UKRI Section as well as EDA Solutions. More than 40 registered academic researchers and modeling engineers attended two sessions to hear 9 technical compact modeling presentations including the QUCS Tutorial by Prof. Mike Brinson.

 

The workshop summary has been posted thru the semiwiki.com blog and all the MOS-AK presentations are available for downloads here.

 

The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events to focus on the Verilog-A compact model standardization as well as open source circuit simulation tool developments: 

• 3rd Training Course on Compact Modelling, TCCM, Lublin (PL), June 18, 2014
  
• a special compact modeling session at the MIXDES'14 Conference in Lublin (PL), June 19-21, 2014
  
• an autumn MOS-AK/ESSDERC/ESSCIRC workshop in Venice (I), Sept. 26, 2014
  
• MOS-AK Q4 Workshop San Francisco (US), Dec. 2014

In the meantime, please also visit www.mos-ak.org where we will continue the discussions of all compact/SPICE modeling topics and its Verilog-A standardization.

--WG--V2014

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