Monday, 16 March 2015

[MOS-AK/DATE 2015 Workshop] CEA-Leti's predictive model takes FDSOI further

 CEA-Leti's predictive model takes FDSOI further 

During DATE 2015’s MOS-AK Workshop, CEA-Leti presented the newest version of its advanced compact model for ultra-thin body and buried oxide fully depleted SOI (UTBB-FDSOI) technology.

Fully Depleted Silicon On Insulator (FDSOI) is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon.

Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no need to dope the channel, thus making the transistor fully depleted. The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted SOI” or UTBB-FDSOI.

Back in 2013, CEA-Leti had deployed a first compact model, but working in close cooperation with STMicroelectronics, the research lab understood that more subtle back gate channelling effects had to be addressed to fully exploit the benefits of UTBB-FDSOI and to explore the transistors’ behaviour in more details.

New analytical equations were written from scratch for the Leti-UTSOI2.1 compact model, improving on the predictability and accuracy capabilities of the previous version, Leti-UTSOI2.

To date, other models from the University of Hiroshima, and from the University of Berkeley fail to account for inversion effects at the back interface, when a strong forward back bias (FBB) is applied, told us Thierry Poiroux, Leti research engineer and model co-developer.

More specifically, the French lab used a unique analytical resolution scheme for the calculation of surface potentials at both interfaces of the transistor body, offering a refined description of narrow-channel effects, with an improved accuracy of moderate inversion regime and gate tunnelling current modelling.

Because the model is analytical, it is much faster than any numerical simulation. It is now available in all major SPICE and Fast SPICE simulators through licences with EDA vendors and will allow fabless companies and IC designers to virtually explore different UTBB-FDSOI parameters within a given foundry process node. The new model can also be used by foundries and fabless companies to perform a predictive analysis of future nodes to come, in order to orient their ongoing process optimization.

for more information visit CEA-Leti at

Sunday, 8 March 2015

[BOOK] FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard

 FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard
 Yogesh Singh Chauhan, Darsen Lu, Sriramkumar Venugopalan, Sourabh Khandelwal, Juan Pablo Duarte, Navid Paydavosi, Ai Niknejad, Chenming Hu

DESCRIPTIONThis book is the first to explain FinFET modeling for IC simulation and the industry standard – BSIM-CMG - describing the rush in demand for advancing the technology from planar to 3D architecture, as now enabled by the approved industry standard. The book gives a strong foundation on the physics and operation of FinFET, details aspects of the BSIM-CMG model such as surface potential, charge and current calculations, and includes a dedicated chapter on parameter extraction procedures, providing a step-by-step approach for the efficient extraction of model parameters.

  • Learn how to do FinFET modeling using the BSIM-CMG standard from the experts
  • Authored by the lead inventor and developer of FinFET, and developers of the BSIM-CMG standard model, providing an experts’ insight into the specifications of the standard
  • The first book on the industry-standard FinFET model - BSIM-CMG
With this book you will learn:
  • Why you should use FinFET
  • The physics and operation of FinFET
  • Details of the FinFET standard model (BSIM-CMG)
  • Parameter extraction in BSIM-CMG
  • FinFET circuit design and simulation

Tuesday, 17 February 2015

MIXDES 2015, June 25-27, 2015; Torun, Poland

 22nd International Conference "Mixed Design of Integrated Circuits and Systems"
 MIXDES 2015, June 25-27, 2015; Torun, Poland

The deadline for regular paper submission is approaching (March 2nd, 2015). If you are going to contribute, I encourage you to register your papers as soon as possible. You will be able to update the paper details and the document file at any time till the final paper version deadline (May 15th, 2015). The early submission will allow us to take care of your paper just now, especially start the reviewer assignments and begin the formatting verification process.

[read more...]

Monday, 16 February 2015

Call for Papers [dvconeurope] DVCon-Europe 2015

The Design and Verification Conference & Exhibition Europe (DVCon Europe) is the premier conference for system architects, concept engineers, software developers, design and verification engineers, and IP integrators to share the latest methodologies and technologies on the practical use of EDA and IP languages and standards used in electronic design.

The focus of this highly technical conference is on the industrial application of specialized design and verification languages such as SystemC, SystemVerilog, VHDL, UVM or e; assertions in SVA or PSL; the use of AMS languages; design automation using IP-XACT; and the use of general purpose languages C and C++.

This call for papers solicits presentations that are highly technical and reflect real life experiences in using EDA languages, standards, methodologies and tools. Industry applications of interest include (but are not limited to) automotive, mobile communication, aerospace, healthcare, chip-cards, consumer and power electronics. Submissions are encouraged in (but not restricted to) the four topic areas listed below. Low power techniques and design for functional safety (e.g., ISO 26262, DO-254) are pervasive and can be addressed in any of these topics areas.

Please submit your draft version of the paper by May 1, 2015. Detailed instructions on the paper requirements and submission process can be found on

ESSCIRC/ESSDERC 2015 website is now active

 ESSCIRC/ESSDERC 2015 website is now active:

 The deadline for paper submission is 2 April, 2015.
 Looking forward to seeing you in Graz!

Prof. Wolfgang Pribyl: General Chair ESSCIRC/ESSDERC 2015
Franz Dielacher, Gernot Hueber: ESSCIRC TPC Chairs
Martin Schrems, Tibor Grasser: ESSDERC TPC Chairs

Thursday, 12 February 2015

Call for Papers: [fdl7] FDL2015

 Forum on Specification & Design Languages
 [fdl7] FDL 2015 CALL FOR PAPERS
  September 14-16, 2015 | Barcelona, Spain

FDL is an international forum to exchange experiences and promote new trends in the application of languages, their associated design methods and tools for the design of electronic systems. FDL stimulates scientific and controversial discussions within and in-between scientific topics as described below. The program structure includes research working sessions, embedded tutorials, panels, and technical discussions. The Forum includes tutorials and fringe meetings, such as user group or standardization meetings. “Wild and Crazy Ideas” are also welcome.

Important Dates:

  • Proposals for Special Session: March 22, 2015
  • Full Research Paper submission: May 4, 2015
  • Other Contributions submission: June 10, 2015
  • Notification of acceptance: July 4, 2015
  • Camera ready papers: August 12, 2015

[1st announcement] #SIXHackathon 20-21 March 2015 in Zurich (CH)

 #SIXHackathon 20-21 March 2015 in Zurich (CH)
 [1st announcement] 

Are you interested in the financial technology sector (FinTech)? Are you on the lookout for a challenge? Then take part in SIX's Hackathon in Zurich 20 - 21 March 2015 and rub shoulders with one of the financial sector's leading IT companies for 30 hours.

What you can expect
Fun, challenging questions, exciting data sets, new ideas, networking opportunities, an exchange with like-minded people; people interested in FinTech and employees from SIX who are also participating.

What you have to do
SIX will provide you with data and APIs (interface information) from FinTech. You will work in small teams. The aim is to present an expert jury with a prototype or a concept after 30 hours. You can either select a topic freely or take inspiration from one of the workshops on big data in the financial technology sector and payment solutions. You will be competing against around 100 participants.

Who is eligible to take part
In principle, any student aged over 18 at a Swiss university or university of applied science and all SIX employees are eligible to take part. Participants must have an affinity and a relevant skill-set in the areas of software development, graphic or interface design, marketing, project management or similar.

Why it’s worth to participate
You will have the opportunity to prove your skills using real-life problems and present your ideas to an expert jury. Furthermore, SIX is searching for new talents – depending on your background, successful Hackathon participants could be offered a permanent position or a traineeship at SIX.