Thursday, 14 August 2014

[mos-ak] [Final Program] 12th MOS-AK Workshop at the ESSDERC/ESSCIRC Conference in Venice

 Autumn MOS-AK Workshop in Venice 
 
 Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the 12th consecutive MOS-AK at the ESSDERC/ESSCIRC Conference. 

Venue:
Palazzo del Casinò
Lungomare Marconi, 30
30126 Venice Lido, Italy

MOS-AK Workshop Online Registration 
MOS-AK Workshop Program

08:30-08:50 On-site Registration
08:30-08:50 Morning Session: Open Source CAD/EDA Tools
Is It Time To Rethink the SPICE Input "Language"?
Larry Nagel
Omega Enterprises Consulting (USA)
Parallel Circuit Simulation: How Good Can It Get?
Andrei Vladimirescu
ISEP (FR); UCB (USA)
CUSPICE: The revolutionary NGSPICE on CUDA Platforms
Francesco Lannutti
Sapienza University of Rome (I)
10:30-11:00 Coffee break
Circuit Simulation Update: GPU Progress; Electrothermal Cosimulation
Rick Poore
Keysight Technologies (USA)
QUCS Roadmap
Mike Brinson
QUCS Development (EU)
12:30-13:30 Lunch
13:30-16:30 Afternoon MOS-AK Session: Device Level SPICE/Verilog-A Modeling
Total Virtual Fabrication of Advanced CMOS Devices and Processing
W. Clark, M. Hargrove, G. Schropfer, D. Fried 
Coventor (F)
Performance Comparison of Hall Effect Sensors Obtained by Regular Bulk or SOI CMOS Technology
Maria-Alexandra Paun
University of Cambridge, (UK)
RF Characterization and Modeling of Nanoscale MOSFET from Weak to Strong Inversion
Maria-Anna Chalkiadaki and Christian Enz
EPFL STI IMT ICLAB (CH)
THz Compact Modeling 
Michael Shur
Rensselaer Polytechnic Institute, NY, (USA)
Compact Modeling of Junctionless Cylindrical Nanowires
Benjamin Iniguez
URV, (SP)
Comparative Analysis of SOI/SOS MOSFET SPICE Models with Account for Radiation Effects
Konstantin Petrosyants(1), Igor Kharitonov (1), Lev Sambursky (1,2)
(1) MIEM HSE (RU), (2) IPPM RAS (RU)
16:30 End of the MOS-AK Workshop 

Postworkshop publications:
selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems 



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Monday, 11 August 2014

Dr. Jindal has been nominated for the Delegate-Elect/Director-Elect 2015

Dr. Renuka Jindal is Professor of Electrical and Computer Engineering at the University of Louisiana at Lafayette, LA, USA since 2002. His research and teaching interests lie in the theory and practice of random processes applicable to a wide variety of phenomena in electronic and photonic devices and circuits, lightwave and wireless communications systems and biological organs. Dr. Jindal was elected Fellow of IEEE in 1991 for his seminal work reducing MOSFET noise by almost an order of magnitude for analog and RF applications. He is also a recipient of the IEEE 3rd Millennium medal. For last four decades of his dual career in industry and academia, Dr. Jindal rose through the ranks as Editor, Editor-in-Chief, VP of Publications, and as EDS President in 2010- 2011. As President he formulated the vision and mission of EDS enhancing member benefits launching a plethora of initiatives reversing the decline in EDS membership. A partial list of his accomplishments is given below:


As Senior-Past President of EDS Dr. Jindal is still very much engaged with IEEE. Recently, Dr. Jindal has been nominated by IEEE Division I to run for the Delegate-Elect/Director-Elect 2015 position in the upcoming IEEE elections. The electorate consists of members of three societies i.e. Electron Devices (ED), Solid-State Circuits (SSC) and Circuits and Systems (CAS). The slate consists of three candidates one from each of these societies. 

On his behalf, I suggest to contact your colleagues in IEEE regions 1-10 for his support since IEEE ballots will be out by August 15.

Wednesday, 30 July 2014

Semiconductor Devices Characterization Seminar

Technical Seminars addressing the challenges of CMOS, Power and RF
semiconductor device measurement and modeling 
Agilent and it´s 25 collaborative partners invite you to attend this complimentary technical seminar on characterization and modeling of semiconductor devices. Two tracks in parallel will address the needs for:
  • Small scale silicon industry
  • Power silicon industry and RF Power
Common topics to both Tracks:
  • Live demonstration of GaN device characterization flow: DC I-V characteristic extraction, RF Power measurement, Spice models creation for further usage in design stage.
CMOS Track:
  • Accurate and repeatable on-the-wafer device extraction – Cascade Microtech
  • DC characterization for emerging nano-technologies
  • Flicker Noise and Random Telegraph Noise
  • Spice model libraries optimization for dedicated application
Power & RF Power Track:
  • High Power Devices measurement
  • III-V devices spice model (DynaFET)
  • Nonlinear Component characterization
  • Non-50ohm Load Pull solution – Maury
Where/when:
To obtain the detail agenda of the nearest session, please select one of the locations below.
CountryCityDateMore Information
FRGrenoble18 September 2014Register here
FIHelsinki23 September 2014Register here
DEMunich30 September 2014Register here
DEDresden2 October 2014Register here
CHLausanne14 October 2014Register here
BELeuven16 October 2014Register here
NLEindhoven17 October 2014Register here
SWGoteborg28 October 2014Register here
UKCambridge30 October 2014Register here
FRLes Ulis6 November 2014Register here


 

 

Monday, 28 July 2014

i-MOS version 201407 release

 The i-MOS team has announced new release of the interactive Modeling and On-line Simulation Platform (i-MOS), version 201407. Through the Developer module launched in April, the UMEM model for organic thin film transistors has been integrated with i-MOS for users' evaluations and applications. Another model implemented is the BSIM4 (version 4.0.0), together with model collections from the Predictive Technology Models.  

Any comments and other equerries can be addressed to
Lining Zhang,
PhD i-MOS Project Manager
The Hong Kong University of Science & Technology

Wednesday, 16 July 2014

[SISPAD] Compact Modeling Worksops - Enabling Better Insight of Device Features - Monday, September 8, 2014


 SISPAD Compact Modeling Workshop
 Enabling Better Insight of Device Features 
 Monday, September 8, 2014

 Workshop Program

09:15 - 09:20: Opening 

09:20 - 10:00: J. Takeya (University of Tokyo, Japan): invited Physics of Charge Transport in Organic Field-Effect Transistors
10:00 - 10:40: C. Jungemann (RWTH Aachen University, Germany): invited Validity of Macroscopic Noise Models in the Case of High-Frequency Bipolar Transistors
10:40 - 11:00: break
11:00 - 11:40: N. Goldsman (University of Maryland, USA): invited Key Issues in the Modeling of SiC Electronic Devices
11:40 - 12:10: C. Ma (Hiroshima University, Japan): invited Universal Model of the Negative Bias Temperature Instability (NBTI) Effect for Circuit Aging Simulation

12:10 - 12:30: poster presentations
  • P. X. Tran (International University, Vietnam) A Comprehensive Model for the Changing I-V Characteristics of raphene Transistors 
  • M. Ghittorelli, F. Torricelli, Z. M. Kovacs-Vajna, and L. Calalongo (University of Brescia, Italy) Accurate Modeling of Amorphous Indium-Gallium-Zinc-Oxide TFTs Deposited on Plastic Foil 
  • S. Sato, Y. Omura, and A. Mallik (Kansai University, Japan) Proposal of Simple Channel-Length-Dependent Current Model for Subthreshold Region of Nano-Wire Tunnel FET 
  • H. Miyamoto, H. Zenitani, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, and T. Nakagawa (HU & AIST, Japan) Consistent Compact Modeling of MOSFETs from Bulk to Double-Gate Structures
12:30 - 13:50: lunch

13:50 - 14:30: D. Warning (Creative Chips GmbH, Germany): invited NGSPICE – an Open Platform for Modeling and Simulation
14:30 - 15:00: A. Schaldenbrand (Cadence Design Systems, Japan): invited Benefits of Verilog-A for Behavioral Modeling and Compact Modeling
15:00 - 15:30: P. Lee (Micron Memory Japan, Inc.): invited Compact Model Coalition: World-Wide Model Standardization for an Expanding Industry

15:30 - 15:40: break

15:40 - 16:00: F. Torricelli, M. Ghittorelli, M. Rapisarda, L. Mariucci, S. Jacob, R. Coppard, E. Cantatore, Z. M. Kovacs-Vajna, and L. Colalongo (Unviersity of Brescia, Italy) Analytical Drain Current Model of Both p- and n-Channel OTFTs for Circuit Simulation
16:00 - 16:20: T. Nakagawa, T. Sekigawa, M. Hioki, Y. Ogasahara, H. Koike, H. Zenitani, H. Miyamoto, H. Kikuchihara, H. J. Mattausch, M. Miura-Mattausch, H. Oda, and N. Sugii (AIST, HU, LEAP, Japan) Parameter-Extraction Strategy of Ultra-Thin Silicon and BOX Layer MOSFETs for Low Voltage Applications
16:20 - 16:40: T. Mizoguchi, T. Naito, Y. Kawaguchi, and W. Hatano (Toshiba, Japan) Compact Modeling of GaN-MISFET for Power Applications
16:40 - 17:00: T. Yamamoto and H. Kato (Denso, Japan) Analysis and Modeling of Injection Enhanced Insulated Gate Bipolar Transistor

17:00: Closing

Tuesday, 10 June 2014

ESSDERC/ESSCIRC 2014 - Full conference program is now available

The technical programtutorial program, and workshop program of ESSDERC/ESSCIRC 2014
are now available at  ESSDERC/ESSCIRC 2014  website: http://www.esscirc-essderc2014.org 

Please remember to register to the conference and book a hotel room at before June 20, after 
which we cannot guarantee that you will find a hotel room at our rebated prices.
The event is technically co-sponsored by the
    IEEE Electron Device Society,
    IEEE Solid-State Circuit Society
    IEEE Circuits and Systems Society


We hope to see you in Venice

Best Regards
  Gaudenzio Meneghesso
ESSDERC/ESSCIRC 2014  General Chair

Roberto Bez and Paolo Pavan
ESSDERC 2014 TPC Chairs

Pietro Andreani and Andrea Bevilacqua 
ESSCIRC
 
2014 TPC Chairs


JOINT PLENARY TALKS 
Scott DeBoer
, Micron, ID, USA, A Semiconductor Memory Manufacturing and Development Perspective
Thomas H. Lee
, Stanford University, CA, USA Terahertz Electronics: The Last Frontier 
Fabio Marchiò
, STMicroelectronics, Italy, Automotive Electronics: Application & Technology Megatrends
Walter Snoeys
, CERN, Switzerland, How Chips Helped Discover the Higgs Boson at CERN
An Steegen
, IMEC, Belgium, Logic Scaling Beyond 10nm, a Power-Performance-Area-Cost Trade-off 
Sehat Sutardja
, Marvell Semiconductor, CA, USA Tremendous Benefits of Moore’s Law Have Yet to Come
ESSCIRC PLENARY TALKS
Hooman Darabi
, Broadcom Corporation, CA, USA Blocker Tolerant Software Defined Receivers
Un-Ku Moon, Oregon State University, OR, USA Emerging ADCs
Kathleen Philips
, IMEC-Holst Centre, The Netherlands Ultra-Low Power Short Range Radios
ESSDERC PLENARY TALKS
Umesh Mishra
, UCSB and TRanphorm, CA, USA,  GaN-based solutions from KHz to THz 
Eric Pop, Stanford University, CA, USA, Energy Efficiency and Conversion in 1D and 2D Electronics
Takao Someya
, University of Tokyo, Japan Bionic Skins Using Flexible Organic Devices

ESSCIRC TUTORIALS
Power Management for SoCs (Full Day), Organizer: Christoph Sandner, Infineon, Austria
High Performance Amplifiers 
(Half Day), Organizer: Angelo Nagari, STMicroelectronics, France
Phase Noise: from Fundamentals to Circuit Aspects (Half Day) Organizer: Christian Enz, EPFL, Switzerland
ESSDERC TUTORIALS
CMOS Technology at the nm Scale Era 
(Full Day) Organizer: Maud Vinet, CEA LETI, France
RRAM: from Technology to Applications (Half Day) Organizer: Bogdan Govoreanu, IMEC, Belgium 
3D: from Technology to Applications 
(Half Day) Organizer: Pascal Vivet, CEA LETI, France

ESSDERC/ESSCIRC Workshops
Beyond-CMOS for advanced More Moore and More than Moore applications
 
Organizers: Francis Balestra and Enrico Sangiorgi, Sinano Institute - Grenoble INP/CNRS, France
MOS-AK: Over Two Decades of Enabling Compact Modeling R&D Exchange   
Organizer: Wladek Grabinski, MOS-AK Group (EU),
Status of the GaN and SiC based device development
   
Organizer: Enrico Zanoni, University of Padova, DEI, Italy
THz-Workshop: Millimeter- and Sub-Millimeter-Wave circuit design and characterization
   
Organizer: Thomas Zimmer, University Bordeaux, France
Marie Curie ATWC
   
Organizer: Rinaldo Castello, University of Pavia and Marvell, Italy

Sunday, 18 May 2014

[mos-ak] 12th MOS-AK Workshop at the ESSDERC/ESSCIRC Conference in Venice

 Autumn MOS-AK Workshop in Venice 
 
Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the 12th consecutive MOS-AK at the ESSDERC/ESSCIRC Conference.

Venue:
Palazzo del Casinò
Lungomare Marconi, 30
30126 Venice Lido, Italy

Important Dates:
Call for Papers - May 2013
2nd Announcement - June 2014
Final Workshop Program - Aug. 2014
MOS-AK Workshop - Friday, Sept. 26, 2014
 8:30 -  9:00 - On Site Registration
 9:00 - 12:00 - Morning MOS-AK Session
12:00 - 13:00 - Buffet Lunch  
13:00 - 16:00 - Afternoon MOS-AK Session

Topics to be covered include the following:
Advances in semiconductor technologies and processing
Compact Modeling (CM) of the electron devices
Verilog-A language for CM standardization
New CM techniques and extraction software
Open Source TCAD/EDA modeling and simulation
CM of passive, active, sensors and actuators
Emerging Devices, CMOS and SOI-based memory cells
Microwave, RF device modeling, high voltage device modeling
Nanoscale CMOS devices and circuits
Technology R&D, DFY, DFT and IC Designs
Foundry/Fabless Interface Strategies

Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form (any related enquiries can be sent to abstracts@mos-ak.org)

Postworkshop publications:
selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems


[WG 052014]

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