Wednesday, 30 November 2016

The #efabless $15,000 #Design #Challenge https://t.co/OV5sjnfSxm #papers


from Twitter https://twitter.com/wladek60

November 30, 2016 at 01:17PM
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Tuesday, 29 November 2016

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers https://t.co/IS3MAiWqZY


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November 29, 2016 at 02:51PM
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Saturday, 26 November 2016

#Opensource #lab-on-a-board costs $29 https://t.co/cJIQPpDgvG #software #feedly #papers


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November 26, 2016 at 08:25PM
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Friday, 25 November 2016

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (zo) of the DE finger, the gap (zd) between the polyplate and the DE finger, and the STI depth (ys), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]

Thursday, 24 November 2016

[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz
Marina Denga, Thomas Quémeraisb, Simon Bouvota, b, Daniel Gloriab, Pascal Chevalierb
Sylvie Lépillieta, François Dannevillea, Gilles Dambrinea
aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 
59652 Villeneuve-d’Ascq Cedex, France
bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

Highlights
  • The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
  • Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
  • A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

http://dx.doi.org/10.1016/j.sse.2016.11.012

Wednesday, 23 November 2016

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

  • The Struggle to Keep Scaling BEOL, and What We Can Do Next
    Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
  • Physical Characterization of Advanced Devices
    Robert Wallace, Univ. Texas at Dallas
  • Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
    Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

  • Electronic Circuits and Architectures for Neuromorphic Computing Platforms
    Giacomo Indiveri, Univ. of Zurich and ETH Zurich
  • Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
    Ben Kaczer, Principal Scientist, IMEC
  • Embedded Systems and Innovative Technologies for IoT Applications
    Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here: http://ieee-iedm.org/onsite-registration-center/online-registration/

Friday, 18 November 2016

EKV302.00 in Cadence MMSIM 14.10

EKV302.00 is available in Cadence MMSIM 14.10. The new version can be accessed through version control parameter. It includes several enhancements, new flicker noise model and new operating point features.