Friday, 10 July 2015

Octave-Forge Community Choice POTM

The Octave-Forge packages -- Community Choice Project of the Month for July

For one of the July "Community Choice" Projects of the Month, the community elected Octave-Forge, a central location for the collaborative development of packages for GNU Octave, a high-level interpreted language. The Octave-Forge packages expand Octave's core functionality by providing field specific features via Octave's package system. Some of the individual Octave-Forge packages include: image and signal processing, fuzzy logic, instrument control, and statistics packages.

Download Octave-Forge now.

Related Projects:

Tuesday, 30 June 2015

Analog CMOS from 5 micrometer to 5 nanometer

 Sansen, W., "1.3 Analog CMOS from 5 micrometer to 5 nanometer," ISSCC 2015 IEEE International , vol., no., pp.1,6, 22-26 Feb. 2015 doi: 10.1109/ISSCC.2015.7062848 

Abstract: In our future, as usual, analog designers will continue to expand their expertise and knowledge in response to changing needs. While devices will change their nature and operate at higher and higher frequencies, their I-V characteristics will remain similar. In the near term, increased speed of MOS circuits, will be reached by operating deeper in weak inversion. Offset and 1/f noise will continue to play a critical role. Thus, in general, it seems that analog expertise is insensitive to technology change.
[read more]

Sunday, 28 June 2015

QUCS: Project of the Week, June 1, 2015

 The Qucs is one of the featured projects for the week (June 1, 2015), which appear on the front page of

 Qucs is a circuit simulator with a graphical user interface. The software aims to support all kinds of circuit simulation types such as, e.g. DC, AC, S-parameter, Transient, Noise, and Harmonic Balance analysis. Pure digital simulations are also supported.
[ Download Quite Universal Circuit Simulator ]

Wednesday, 17 June 2015

3rd Training Course on Compact Modeling

 3rd TCCM, 
 organized as IEEE EDS Mini-Colloquium 

Co-organizer: Institute of Electron Technology, Warsaw, Poland
Technical Program Promoter: DMCS, Lodz University of Technology, Łódź, Poland

Date: June 24, 2015.
Place: Hotel Bulwar (Lejda room) ul. Bulwar Filadelfijski 18, 87-100 Toruń, Poland

Final schedule of TCCM:
9:00 Wladek Grabinski, Opening
9:10 Henryk Przewłocki, "Weaknesses and corrections of the classical theory of photoelectric phenomena in the MOS system"
10:00 Juin J.Liou, "Compact Modeling of Junction Failure in Semiconductor Devices Subject to Electrostatic Discharge Stresses"
10:50 Coffee break
11:10 Jean-Michel Sallese, "Modeling Junctionless Field Effect Transistors"
12:00 Mike Brinson, "A unified approach to compact device modelling with the open source packages Qucs/ADMS and MAPP/Octave"
13:00 Lunch
14:30 Benjamin Iniguez, "Physically-Based Compact Modeling of GaN HEMT"
15:20 Wladek Grabinski, "Verilog-A Compact Model Standardization"
16:10 Daniel Tomaszewski, "Compact modeling and statistical modeling for parametric yield improvement"
17:00 Wladek Grabinski, Closing

Friday, 12 June 2015

Micro&Nano 2015 - 2nd Announcement

6th Micro & Nano Conference on Micro - Nanoelectronics, Nanotechnologies and MEMs
4-7 October, 2015, Athens, Greece
Second Announcement

The "Micro&Nano 2015" Conference will be held at the Fenix Hotel, in Glyfada, Athens, Greece. The Best Western Hotel Fenix is conveniently located in Glyfada, an attractive resort in the south coast of Athens. More details on the Conference venue can be found on the conference website:

Conference Topics:
  • Micro and Nano- Fabrication
  • Materials for Electronics, Photonics and Sensors
  • Electronic, Optoelectronic and Photonic Devices
  • Sensors and Actuators
All abstracts should not exceed the limit of 300 words. Please follow the abstract template that can be found here. The deadline for abstract submission is on 30 June 2015.

The Conference abstracts will be published in the "Abstract Book" that will be distributed to all the participants, at the beginning of the Conference. Selected papers will be published, after peer-review, in special issues of the following international journals:
  • Nanoscale Research Letters (the nanoscience related articles)
  • Microelectronic Engineering
[read more:]

Friday, 15 May 2015

[mos-ak] [2nd Announcement and Call for Papers] Autumn 2015 MOS-AK Workshop at ESSDERC/ESSCIRC

 Autumn 2015 MOS-AK Workshop at ESSDERC/ESSCIRC
Graz (A) September 18, 2015
2nd Announcement and Call for Papers

Together with the MOS-AK Workshop Scientific Program Coordinators Larry Nagel and Andrei Vladimirescu, local workshop chairs Benjamin Iniguez, URV (SP) and Jean-Michel Sallese, EPFL (CH) as well as Extended MOS-AK TPC Committee, we have pleasure to invite to the MOS-AK Workshop which will be held in Graz (A) at the ESSDERC/ESSCIRC Conference where also a joint modeling session (invited talks by Prof. C.C.Enz and Prof. C.Hu) as well as a session with regular modeling paper (and the invited talk by Prof. M.Lundstrom) are planed. Following MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors.

University of Technology,
Campus Inffeldgasse
Graz (A)

Important Dates:
  • Call for Papers - March 2015
  • 2nd Announcement - May 2015
  • Final Workshop Program - July 2015
  • MOS-AK Workshop - Sept.18, 2015
    • 08:30 - 09:00 - On-site Registration
    • 09:00 - 10:30 - Morning MOS-AK Session
    • 11:00 - 12:00 - CM Standardization Pannel
    • 12:00 - 13:00 - Lunch
    • 13:00 - 16:00 - Afternoon MOS-AK Session
Topics to be covered include the following:
  • Advances in semiconductor technologies and processing
  • Compact Modeling (CM) of the electron devices
  • Verilog-A language for CM standardization
  • New CM techniques and extraction software
  • Open Source TCAD/EDA modeling and simulation
  • CM of passive, active, sensors and actuators
  • Emerging Devices, CMOS and SOI-based memory cells
  • Microwave, RF device modeling, high voltage device modeling
  • Nanoscale CMOS devices and circuits
  • Technology R&D, DFY, DFT and IC Designs
  • Foundry/Fabless Interface Strategies
Online Abstract Submission:
Authors should submit an abstract using on-line MOS-AK submission form
(any related inquiries can be sent to

Free online workshop registration:
(any related inquiries can be sent to

Postworkshop publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee


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Monday, 16 March 2015

[MOS-AK/DATE 2015 Workshop] CEA-Leti's predictive model takes FDSOI further

 CEA-Leti's predictive model takes FDSOI further 

During DATE 2015’s MOS-AK Workshop, CEA-Leti presented the newest version of its advanced compact model for ultra-thin body and buried oxide fully depleted SOI (UTBB-FDSOI) technology.

Fully Depleted Silicon On Insulator (FDSOI) is a planar process technology that relies on two primary innovations. First, an ultra-thin layer of insulator, called the buried oxide, is positioned on top of the base silicon.

Then, a very thin silicon film implements the transistor channel. Thanks to its thinness, there is no need to dope the channel, thus making the transistor fully depleted. The combination of these two innovations is called “ultra-thin body and buried oxide Fully Depleted SOI” or UTBB-FDSOI.

Back in 2013, CEA-Leti had deployed a first compact model, but working in close cooperation with STMicroelectronics, the research lab understood that more subtle back gate channelling effects had to be addressed to fully exploit the benefits of UTBB-FDSOI and to explore the transistors’ behaviour in more details.

New analytical equations were written from scratch for the Leti-UTSOI2.1 compact model, improving on the predictability and accuracy capabilities of the previous version, Leti-UTSOI2.

To date, other models from the University of Hiroshima, and from the University of Berkeley fail to account for inversion effects at the back interface, when a strong forward back bias (FBB) is applied, told us Thierry Poiroux, Leti research engineer and model co-developer.

More specifically, the French lab used a unique analytical resolution scheme for the calculation of surface potentials at both interfaces of the transistor body, offering a refined description of narrow-channel effects, with an improved accuracy of moderate inversion regime and gate tunnelling current modelling.

Because the model is analytical, it is much faster than any numerical simulation. It is now available in all major SPICE and Fast SPICE simulators through licences with EDA vendors and will allow fabless companies and IC designers to virtually explore different UTBB-FDSOI parameters within a given foundry process node. The new model can also be used by foundries and fabless companies to perform a predictive analysis of future nodes to come, in order to orient their ongoing process optimization.

for more information visit CEA-Leti at