Oct 20, 2020

[Open PhD] #IMEC

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October 20, 2020 at 05:46PM

#Intel sells its NAND flash #memory business to #SKHynix for $9 billion https://t.co/9xJ6aZtcpw #semi https://t.co/4BTNalB6Ai

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October 20, 2020 at 11:44AM

Oct 19, 2020

#Dialog Semiconductor Licenses its #Non-Volatile #Resistive #RAM Technology to #GF for 22FDX Platform, Targeting IoT and AI https://t.co/ReWiCM4oCv #semi https://t.co/o7CMYt9HkV

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October 19, 2020 at 05:44PM

[paper] Single Gate Extended Source Tunnel FET

Jagritee Talukdara, Gopal Rawatb, Bijit Choudhuria, Kunal Singhc, Kavicharan Mummanenia
Device Physics Based Analytical Modeling for Electrical Characteristics of Single Gate Extended Source Tunnel FET (SG-ESTFET)
Superlattices and Microstructures (2020): 106725
DOI: 10.1016/j.spmi.2020.106725

aDECE, NIT Silchar, Assam, India
bDECE, NIT Hamirpur, Himachal Pradesh, India
cDECE, NIT Jamshedpur, Jharkhand, India

Abstract: In this paper, a 2D analytical model for Single Gate Extended Source Tunnel FET has been developed which is based on the solution of Poisson’s equation simplified using parabolic approximation method. Different electrical characteristics of device physics such as surface potential, drain current, lateral, and vertical electric field of SG-ESTFET are studied incorporating various parameters like mole fraction of SiGe layer, gate dielectric constants, etc. Furthermore, in modeling and simulation, the depletion region of the drain side is included considering the effect of the fringing field. The comercial TCAD device simulator has been used to verify the accuracy and validity of the proposed analytical model for various electrical parameters such as gate to source voltage, mole fraction, and gate dielectric constants. The validity of the proposed model is confirmed by observing a decent agreement between modeling and simulation. The proposed compact model delivers quick and accurate values of various performance parameters.
Fig: 2D schematic device structure of SG-ESTFET

[paper] Parameter Extraction Technique for IGBT Compact Model

N.V. Bharadwaj1, Dr. P. Chandrasekhar2 and Dr. M. Sivakumar3
A Consecutive Parameter Extraction Technique for IGBT Compact Model
ICMM-2019; AIP Conf. Proc. 2269, 030031-1–030031-5;
DOI: 10.1063/5.0019484

1Geethanjali College of Enegineering and Technology, Hyderabad, 501301, India 
2MGIT, Hyerabad, 500075, India 
3Gudlavalleru Engineering College, Gudlavalleru , 521356, India

Abstract: A consecutive parameter extraction technique describes the fitting target related parameters for Insulated-gate bipolar transistor (IGBT) model. The IGBT model has been represented by a couple of simplified equivalent circuits. Using simulated data for a trench-type IGBT as reference the performance of compact model IGBT is compared to an IGBT macro model. Due to physics based modeling, parameter extraction with the compact model is fast. With very less extraction effort, the compact model fits the dc current and capacitance characteristics accurately.

FIG: The IGBT cell structure with cell pitch = 4μm and trench gate depth = 3μm