Wednesday, November 30, 2016

The #efabless $15,000 #Design #Challenge #papers

from Twitter

November 30, 2016 at 01:17PM

Tuesday, November 29, 2016

Investigation of Gate Direct-Current and Fluctuations in Organic p-Type Thin-Film Transistors #papers

from Twitter

November 29, 2016 at 02:51PM

Saturday, November 26, 2016

#Opensource #lab-on-a-board costs $29 #software #feedly #papers

from Twitter

November 26, 2016 at 08:25PM

Friday, November 25, 2016

[paper] RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors
H. C. Tsai, R. H. Liou and C. Lien
IEEE Transactions on Electron Devices
vol. 63, no. 12, pp. 4603-4609, Dec. 2016

Abstract: Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width (zo) of the DE finger, the gap (zd) between the polyplate and the DE finger, and the STI depth (ys), is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Keywords: Conformal mapping, Doping, Electric breakdown, MOS devices, Semiconductor process modeling, Silicon, Transistors, Drain extended MOS (DEMOS), Lateral double Diffused MOS (LDMOS), poly field plate, reduced surface field (RESURF)

doi: 10.1109/TED.2016.2605504
[read more...]

Thursday, November 24, 2016

[paper] Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325 GHz

Small-Signal Characterization and Modeling of 55 nm SiGe BiCMOS HBT up to 325GHz
Marina Denga, Thomas Quémeraisb, Simon Bouvota, b, Daniel Gloriab, Pascal Chevalierb
Sylvie Lépillieta, François Dannevillea, Gilles Dambrinea
aIEMN UMR CNRS 8520, University of Lille, Avenue Poincaré, CS60069, 
59652 Villeneuve-d’Ascq Cedex, France
bSTMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France

  • The SiGe HBT full S-parameters from 250MHz to 325GHz under multiple bias conditions are presented for the first time.
  • Standard calibration and de-embedding techniques are used and remained valid up to 325GHz thanks to a reduction of the test structures dimensions.
  • A simple and accurate small-signal electrical model was extracted and compared with measurements up to 325GHz.

Received 19 September 2016, Revised 18 November 2016, Accepted 21 November 2016, Available online 22 November 2016 [read more...]

Wednesday, November 23, 2016

2016 IEDM Tutorials

2016 International Electron Devices Meeting Tutorials

The tutorials are in their sixth year and are 90 minute stand-alone presentations on specialized topics taught by world-class experts. These tutorials provide a brief introduction to their respective fields, and facilitate understanding of the technical sessions. The tutorial sessions will take place on Saturday, Dec.3, 2016. Three tutorials are given in parallel in two time slots, at 2:45 p.m.and 4:30 p.m. respectively.

Topics presented at 2:45pm - 4:15pm:

  • The Struggle to Keep Scaling BEOL, and What We Can Do Next
    Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries
  • Physical Characterization of Advanced Devices
    Robert Wallace, Univ. Texas at Dallas
  • Spinelectronics: From Basic Phenomena to Magnetoresistive Memory (MRAM) Applications
    Bernard Dieny, Chief Scientist, Spintec CEA

Topics presented at 4:30pm - 6:00pm:

  • Electronic Circuits and Architectures for Neuromorphic Computing Platforms
    Giacomo Indiveri, Univ. of Zurich and ETH Zurich
  • Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation
    Ben Kaczer, Principal Scientist, IMEC
  • Embedded Systems and Innovative Technologies for IoT Applications
    Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor

Register for the IEDM tutorials here:

Friday, November 18, 2016

EKV302.00 in Cadence MMSIM 14.10

EKV302.00 is available in Cadence MMSIM 14.10. The new version can be accessed through version control parameter. It includes several enhancements, new flicker noise model and new operating point features.

INFOS 2017 in Potsdam, Germany

20th Conference on “Insulating Films on Semiconductors” 
INFOS 2017
June 27th – 30th, 2017 in Potsdam, Germany

The INFOS conference is a prestigious biennial event which brings together electrical engineers, technologists, materials scientists, device physics and chemists from Europe and around the world to debate the latest development in thin insulating film technology and identify as well as address challenges ahead in this highly diversifying field [read more...]

Conference Topics:
  • High-k dielectrics, metal gate materials and SiO2 for future scaling
  • Gate stack materials for high mobility substrates (Ge, SiGe, GaN, III-V)
  • Stacked dielectrics for non-volatile memory (flash, nc-Si)
  • Dielectrics for resistive switching memories and spin memories
  • Dielectrics for DRAM and MIM
  • Low-k dielectrics
  • Semiconductors on insulators
  • Dielectrics for 2D materials, nanowires, 2D devices and carbon-based devices
  • Surface cleaning technologies
  • Physics and chemistry of dielectrics and defects
  • Characterization techniques for dielectrics and interfaces
  • Electrical reliability, leakage and modelling
  • Modelling of atomic structure of dielectrics, interfaces and thin films
  • Topological insulators
  • Ferroelectrics and functional oxides
  • Dielectrics and thin films for TFT, amorphous or organic devices and photovoltaics
  • Dielectrics for photonics and sensing

Creating A PCB In Everything: KiCad, Part 1 #todo #feedly #papers

from Twitter

November 17, 2016 at 11:23PM

Wednesday, November 16, 2016

Open Source License Compliance bei Embedded-Systemen

Open Source License Compliance bei Embedded-Systemen 
( Kompaktseminar, ESE Kongress 2016, in Sindelfingen )
Referent: Dr. Till Jaeger, JBB Rechtsanwälte
Zeit: 28.11.16 09:00-12:30

Abstract: When using Linux and other open source software (OSS), the license terms of the GPL and other open source licenses must be adhered to. As license violations lead directly to copyright infringements, appropriate compliance measures are necessary. The compact seminar presents the essential requirements for a compliance process based on the OpenChain Initiative. OpenChain aims at an international standard for suppliers using OSS in your products.

  1. What is Open Source Software?
  2. How does the open source license model work?
  3. Legal consequences of violation of OSS license terms
  4. How is it ensured that the use of OSS is known and which licensing conditions are affected?
  5. The Copyleft (1): When must self-development be released again as OSS?
  6. Copyleft (2): Verification of license compatibility between different OSS licenses
  7. Process to comply with sales obligations (for example, source code offer, co-delivery license texts)
  8. Methods of quality control

[read more...]

National Workshop on Advanced Nanoscale Device Design Using TCAD

The National Workshop on Advanced Nanoscale Device Design Using Technology Computer-Aided Design (TCAD) was organized by the IEEE SolidState Circuits Society (SSCS) College of Engineering Chengannur, India Chapter. The workshop was held 28 December 2015 through 1 January 2016 as a three-day tutorial and two-day handson session. The event was graced with the presence of distinguished lecturers from top institutions in India, including Prof. Yogesh S. Chouhan from IIT Kanpur delivering the keynote talk. The workshop attracted approximately 150 participants from 15 reputable academic institutions. People from industry and also attended the event.
The coordinators were proud to present a successful workshop as one of the first events since the formation of the Chapter. The event was funded by the SSCS extra subsidy program. The feedback received from the attendees was very positive. Each participant received a certificate during the closing ceremony of the event. The five-day workshop came to an end by the heartfelt vote of thanks by Nisha Kuruvilla, with a motto “This is just the beginning.” [read more...]

Tuesday, November 15, 2016

[paper] Analysis of aging effects - From transistor to system level

Analysis of aging effects - From transistor to system level
Maike Taddiken*, Nico Hellwege, Nils Heidmann, Dagmar Peters-Drolshagen, Steffen Paul
Institute of Electrodynamics and Microelectronics,
University of Bremen, Otto-Hahn-Allee 1, Bremen 28359,Germany

ABSTRACT: Due to shrinking feature sizes in integrated circuits, additional reliability effects have to be considered which influence the functionality of the system. These effects can either result from the manufacturing process or external influences during the lifetime such as radiation and temperature. Additionally, modern technology nodes are affected by time-dependent degradation i.e. aging. Due to the age-dependent degradation of a circuit, processes on the atomic scale of the semiconductor material lead to charges in the oxide silicon interface of CMOS devices, altering the performance parameters of the device and subsequently the behavior of the circuit. With the continuous downscaling of modern semiconductor technologies, the impact of these atomic scale processes affecting the overall system characteristics becomes more and more critical. Therefore, aging effects need to be assessed during the design phase and actions have to be taken guaranteeing the correct system functionality throughout a system’s lifetime. This work presents methods to investigate the influence of age-dependent degradation as well as process variability on different levels. An operating-point dependent sizing methodology based on the gm/ID method extended to incorporate aging, which aims at developing aging-resistent circuits is presented. The basic idea of the gm/ID sizing method is the dependence of the operating point of a MOS transistor on the state of inversion in the channel, its strong relation to circuit performance and the possibility to calculate transistor dimensions.The inversion coefficient IC is a fundamental metric within the gm/ID method and numerically represents the inversion level of a MOS device formally described in the EKV MOS model. Additionally, the sensitivity of circuit performances in regard to aging can be determined. In order to investigate the reliability of a complex system on behavioral level, a modeling method to represent the performance of system components in dependence of aging and process variability is introduced. [read more...]

Friday, November 11, 2016

ICNF 2017: 2nd Call for Papers

24th International Conference on Noise and Fluctuations (ICNF 2017) 
20-23 of June 2017 in Vilnius, Lithuania

We would like to invite you to submit your abstracts. For submission of the abstracts, please, REGISTER and go to the Abstract submission site. Instruction for authors and templates for abstract preparation can be found and downloaded  at the Conference website:
Deadline of the abstract submission is 22 January, 2017

Please also keep in mind ICNF2017 important dates:
  • Abstract submission deadline: 22 January, 2017
  • Notification of acceptance deadline: 27 February, 2017
  • Full paper submission deadline:27 March, 2017
  • Early bird registration: 19 April, 2017
  • Conference: 20-23 June, 2017
Please share this information to your colleagues and those who might be interested in ICNF 2017.

For more information visit the Conference website:
or contact us:

Looking forward to meeting you in Vilnius.

With best regards,
Sandra Pralgauskaitė and Paulius Sakalas - Organizing Committee Chairs

Thursday, November 10, 2016

[mos-ak] [Final Program] 9th International MOS-AK Workshop Berkeley DEC.7, 2016

9th International MOS-AK Workshop  
  Berkeley December 7, 2016 
    Final Workshop Program 
Together with the MOS-AK workshop host, Prof. Jaijeet Roychowdhury, UCB and International MOS-AK Board of R&D Advisers: Larry Nagel, Omega Enterprises Consulting (USA), Andrei Vladimirescu, UCB (USA); ISEP (FR) as well as all the Extended MOS-AK TPC Committee, we have pleasure to invite to the 9th International MOS-AK Workshop which will be held at EECS Department, University of California, Berkeley on December, 7, 2016. Planned MOS-AK workshop is organized with aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and CAD/EDA tool developers and vendors. 

Important Dates:
  • Preannouncement - Sept. 2016
  • Call for Papers - Oct. 2016
  • Final Workshop Program - Nov. 2016
  • MOS-AK Workshop - Dec. 7 2016
    •   9:00-12:00 Morning Session
    • 13:00-16:00 Afternoon Session
540 Cory Hall 
EECS Department
University of California, Berkeley
Directions to the DOP Center in Cory Hall
See also
Final MOS-AK/Berkeley Workshop Program Online

Online Workshop Registration:
(any related inquiries can be sent to

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication in a special issue of the International Journal of High Speed Electronics and Systems

Extended MOS-AK Committee


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Tuesday, November 8, 2016

[mos-ak] [press note] 14th MOS-AK ESSDERC/ESSCIRC Workshop

Arbeitskreis Modellierung von Systemen und Parameterextraktion 
Modeling of Systems and Parameter Extraction Working Group
Lausanne, September 12, 2016

The MOS-AK Modeling Working Group, a global compact/SPICE modeling and Verilog-A standardization forum, held its annual autumn workshop on September 12, 2016 in Lausanne (CH) as its 14th consecutive modeling event at the ESSDERC/ESSCIRC Conference. The event was coordinated by Larry Nagel, OEC (USA) and Andrei Vladimirescu, UCB (USA); ISEP (FR) representing the International MOS-AK Board of R&D Advisers. The workshop was co-sponsored by ASCENT Network (lead sponsor) and EPFL EDLab, with technical program sponsorship provided by the IEEE WiE Group (CH), Eurotraining and NEEDS of


A group of the international academic researchers and modeling engineers attended 12 technical compact modeling presentations covering full development chain form the nanoscaled technologies thru semiconductor devices modeling to advanced IC design support. The MOS-AK speakers have shared their latest perspectives on compact/SPICE modeling and Verilog-A standardization in the dynamically evolving semiconductor industry and academic R&D. 


The workshop was opened by Prof. J. Greer; Tyndall National Institute, the MOS-AK keynote speaker, who has introduced the ASCENT Network. The ASCENT is combined resources of Tyndall (Ireland), imec (Belgium) and Leti (France) nanofabrication capabilities and electrical characterization facilities integrated into a single research infrastructure present a truly unique R&D opportunity. It provides characterization community with access to advanced test chips, flexible fabrication and advanced test and characterization equipment to accelerate development of advanced models at scales of 14nm and below.


The event featured additional technical presentations covering compact model development, implementation, deployment and standardization. These contributions were delivered by leading academic and industrial experts, including: Denis Rideau; STM (F), presenting a modeling study of the drain current in advanced MOSFETs. Maria-Alexandra Paun; EPFL (CH), focusing on the humidity sensors based on MWCNTs/MMA composite in SOI CMOS technological process. Mike Brinson; London Met (UK), presenting QUCS-S - maturing GPL software package for circuit simulation and compact modeling of current and emerging technology devices. Alexander Kloes; THM Giessen (D), discussing a closed-form charge-based current model of organic TFT including non-linear injection effects. Jean-Michel Sallese; EPFL (CH), discussing an advances in analytical modeling. Marco Bellini, ABB CRC (CH), presenting extraction of compact models for EMI / EMC simulations of power devices. Muhammad Nawaz; ABB CRC (S), reviewed characterization and modeling of SiC MOSFET power modules. Mansun Chan; HKUST (HK), discussing concurrent device and circuit reliability simulation. Benjamin Iñiguez; URV (SP), talking about temperature dependent GIZO TFT modeling. Mike Schwarz; THM (D), discussing analytical III-V SB MOSFET modeling and its performance analysis from room to cryogenic temperature. Matthias Bucher; TUC (GR), giving an EKV3 model update. The presentations are available online for download at


The MOS-AK Modeling Working Group has various deliverables and initiatives including a book entitled "Open Source CAD Tools for Compact Modeling" and an open Verilog-A directory with models and supporting CAD software. The MOS-AK Association plans to continue its standardization efforts by organizing additional compact modeling meetings, workshops and courses in Europe, USA, India and China throughout 2016/2017 including:

* 9th International MOS-AK Workshop at Berkeley in the timeframe of IEDM and CMC meetings (Dec.7, 2016) 

* Spring MOS-AK Workshop in Lausanne during DATE Conference (March 31 2017)

* 2nd Sino MOS-AK Workshop in Hangzhou (June 2017)

* 15th MOS-AK ESSDERC/ESSCIRC Workshop in Leuven (Sept.11, 2017)


About MOS-AK Association:

MOS-AK, an international compact modeling association primarily focused in Europe, to enable international compact modeling R&D exchange in the North/Latin Americas, EMEA and Asia/Pacific Regions. The MOS-AK Modeling Working Group plays a central role in developing a common language among foundries, CAD vendors, IC designers and model developers by contributing and promoting different elements of compact/SPICE modeling and its Verilog-A standardization and related CAD/EDA tools for the compact models development, validation/implementation and distribution.


About ASCENT Network:

ASCENT provides fast and easy access to the world's most advanced CMOS technologies and infrastructure including access to 14nm CMOS device data, nanoscale test chips and device characterisation facilities at Tyndall (Ireland), imec (Belgium) and Leti (France). ASCENT has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 654384.

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Monday, November 7, 2016

[paper] Field programmable analog array: A boon for analog world

Field programmable analog array: A boon for analog world
Dipti and B. V. R. Reddy,
2016 3rd International Conference on Computing for Sustainable Global Development 
(INDIACom), New Delhi, India, 2016, pp. 2975-2980.

Abstract: n analog chips designing, fabricating, and testing takes a lot of time, money and perfection. In contrast design of digital integrated circuits is fully automated now a day. Due to simpler nature of digital circuits, as compared to Analog circuits, leads to development of libraries and synthesis tools for fast synthesis of digital circuits. To reduce the cost and time-to-market CPLDs and FPGAs are generally used for prototyping of digital integrated circuits. But FPAAs i.e Field Programmable Analog Arrays are boon for designing of analog and mixed-signal Integrated Circuits because of rapid prototyping. FPAA is not only optimal for all solution in contrast to FPGAs but it also reduces the verification and designing cost. This again results from complex nature of analog circuits which needs factors like signal to noise ratio, bandwidth, frequency response, linearity etc. to be addressed. FPAAs are made using configurable analog blocks (CAB) and networks, which are used to provide required interconnection among Cabs. Like FPGAs, circuit functionality is much more sensitive to parasitics introduced by the programming devices in FPAA. So the design of FPAAs architecture and CABs are mutually dependent. To design an efficient FPAA, a designer needs to compromise between flexibility and the number of programmable switches in designing FPAA architectures and the CAB topologies. Various papers are studied for different topologies used in FPAAs and various applications designed with the use of FPAA. In March 2013, Paul Hasler come up with automated approach based on EKV model for characterization of device mismatch, second order defects with temperature. After verification of characterization current sources were created with 2.2% RMS error over dynamic range of 25dB. Field programmable gate array represents a new direction to analog and mixed signal domain keeping the idea of FPGAs in digital domain. RASP is useful for analog designers because they can save the analog components in the form of CABs. RASPER tool was developed for placement and routing of RASP 2.7 and RASP 2.8 versions Whereas GRASPER was developed for RASP 2.9.In digital circuits parasitic only affect the speed of operation but in analog circuits they plays a crucial role for circuit performance and functionality. Floating gate technology was used to simplify designing and implementation, increased system reliability, high precision, innovative approach. In near future FPAA technology will come up with better architecture, low power and more applications with less time to market.

keywords: Decision support systems, Handheld computers, Configurable analog block (CAB), Field programmable analog array (FPAA), Generic reconfigurable array specification and programming environment tool (GRASPER), Operational Transconductance Amplifier, Reconfigurable analog signal processor (RASP)

[read more...]