Thursday, May 31, 2018

Digital and analog TFET circuits: Design and benchmark

Solid-State Electronics
Volume 146, August 2018, Pages 50–65
Invited Review
S. Strangioa,b, F. Settinoa,b, P. Palestria, M. Lanuzzab, F. Crupib, D. Essenia, L. Selmia,c

aDPIA, Università degli Studi di Udine, Via delle Scienze 206, I-33100 Udine, UD, Italy
bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy

ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
https://doi.org/10.1016/j.sse.2018.05.003

HIGHLIGHTS:

  • We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
  • Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
  • Performance are evaluated down to VDD = 200 mV.
  • Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.

ABSTRACT: In this work, we investigate by means of simulations the performance of basic digital, analog, and mixed-signal circuits employing tunnel-FETs (TFETs). The analysis reviews and complements our previous papers on these topics. By considering the same devices for all the analysis, we are able to draw consistent conclusions for a wide variety of circuits. A virtual complementary TFET technology consisting of III-V heterojunction nanowires is considered. Technology Computer Aided Design (TCAD) models are calibrated against the results of advanced full-quantum simulation tools and then used to generate look-up-tables suited for circuit simulations. The virtual complementary TFET technology is benchmarked against predictive technology models (PTM) of complementary silicon FinFETs for the 10nm node over a wide range of supply voltages (VDD) in the sub-threshold voltage domain considering the same footprint between the vertical TFETs and the lateral FinFETs and the same static power. In spite of the asymmetry between p- and n-type transistors, the results show clear advantages of TFET technology over FinFET for VDD lower than 0.4V. Moreover, we highlight how differences in the I-V characteristics of FinFETs and TFETs suggest to adapt the circuit topologies used to implement basic digital and analog blocks with respect to the most common CMOS solutions.


FIG: Sketch of n- and p-type TFET and FinFET device architectures. The red and blue colors indicate the n- and p-doping types, respectively (green: intrinsic semiconductor, transparent-grey: oxide). TFET dimensions are: LG=20nm, nanowire cross section (LS)=7nm, EOT=1nm. FinFET dimensions are: LG=14nm, tfin=8nm, hfin=21nm, EOT=0.88nm. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)

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May 31, 2018 at 09:33AM
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Friday, May 25, 2018

Wednesday, May 23, 2018

Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNY https://t.co/IYoTkGeB9i #paper https://t.co/I3DD9NOApR https://t.co/jBzSISralN


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May 23, 2018 at 06:48PM
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Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples by Viera STOPJAKOVA, Matej RAKUS, Martin KOVAC, Daniel ARBET, Lukas NAGY, Michal SOVCIK, Miroslav POTOCNY https://t.co/IYoTkGeB9i #paper https://t.co/I3DD9NOApR


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Saturday, May 19, 2018

[mos-ak] [Final Program] 3rd Sino MOS-AK Compact Modeling Workshop in Beijing, June 14-16 2018

3rd Sino MOS-AK Compact Modeling Workshop
Beijing, June 14-16 2018
Final Program 

Together with Professor Yan Wang, Tsinghua University, Honorary Committee; George Ponchak, T-MTT Editor and Yuhua Cheng, PKU, Advisory Committee as well as Min Zhang, XMOD, Organizing Committee General Co-Chair, we have pleasure to invite to the 3rd Sino MOS-AK Compact Modeling Workshop which will be organized successively in China between June 14-16, 2018

Scheduled,3rd subsequent MOS-AK modeling workshop organized in China, aims to strengthen a network and discussion forum among experts in the field, enhance open platform for information exchange related to compact/SPICE modeling and Verilog-A standardization, bring people in the compact modeling field together, as well as obtain feedback from technology developers, circuit designers, and TCAD/EDA tool developers and vendors. The MOS-AK workshop program is available online:

3rd Sino MOS-AK Compact Modeling Workshop program includes
Day 1 (June 14): MOS-AK Tutorial Day
Day 2 (June 15): MOS-AK SPICE/Verilog-A Modeling Workshop
Day 3 (June 16): MOS-AK SPICE/Verilog-A Modeling Workshop
Venue: 
会议场所:清华大学FIT-楼,在紫光国际国际交流中心旁
close to Tsinghua Unisplendour International Center
(any related inquiries can be sent to register@mos-ak.org)

Workshop Secretary:
Li Zhang
Office: +86 010 62771733;Mobile: +86 138 01302877
Email: zhangli95@tsinghua.edu.cn

Postworkshop Publications:
Selected best MOS-AK technical presentation will be recommended for further publication
in a special issue of the International Journal of High Speed Electronics and Systems


WG190518

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Wednesday, May 9, 2018

Advanced #FDSOI Device Design: The U-Channel Device for #7nm Node and Beyond https://t.co/fGaY4WQbu2 #paper


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May 09, 2018 at 09:01PM
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Wednesday, May 2, 2018

Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm https://t.co/vDJ9kII7pm


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May 02, 2018 at 12:25PM
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Universal Core #Model for Multiple-gate Field-effect Transistors with Short Channel and Quantum Mechanical Effects - IOPscience https://t.co/vDJ9kII7pm


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May 02, 2018 at 12:25PM
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