Volume 146, August 2018, Pages 50–65
bDIMES, Università della Calabria, Via P. Bucci, 41C, I-87036 Arcavacata di Rende (CS), Italy
cDipartimento di Ingegneria “Enzo Ferrari”, Università degli Studi di Modena e Reggio Emilia, I-41100 Modena, Italy
ARTICLE INFO: The review of this paper was arranged by Prof. S. Cristoloveanu
- We report simulations of basic analog and digital circuit blocks employing tunnel-FETs.
- Template III-V heterojunction tunnel-FETs are benchmarked against silicon FinFETs for the 10 nm node.
- Performance are evaluated down to VDD = 200 mV.
- Tunnel-FETs result advantageous with respect to silicon FinFET for VDD below approximately 400 mV.