[paper] MOSFET-Based Voltage Reference Circuits

Moisello, Elisabetta, Edoardo Bonizzoni, and Piero Malcovati

MOSFET-Based Voltage Reference Circuits in the Last Decade: A Review

Micromachines 15, no. 12 (2024): 1504

Abstract: Voltage reference circuits are a basic building block in most integrated microsystems, covering a wide spectrum of applications. Hence, they constitute a subject of great interest for the entire microelectronics community. MOSFET-based solutions, in particular, have emerged as the implementation of choice for realizing voltage reference circuits, given the supply voltage scaling and the ever-lower power consumption specifications in various applications. For these reasons, this paper aims to review MOSFET-based voltage reference circuits, illustrating their principles of operation, as well as presenting a detailed overview of the state-of-the-art, in order to paint an accurate picture of the encountered challenges and proposed solutions found in the field in the last decade, thus providing a starting point for future research in the field.

FIG: Schematic of a generic threshold voltage-based MOSFET reference circuit

and graphical representation of a transistor ZTC point.

[book] Advanced Nanoscale MOSFET Architectures

Advanced Nanoscale MOSFET Architectures:

Current Trends and Future Perspectives

Kalyan Biswas, Angsuman Sarkar

John Wiley & Sons - Technology & Engineering (2024) 336 pages

ISBN: 978-1-394-18894-9

Comprehensive reference on the fundamental principles and basic physics dictating metal–oxide–semiconductor field-effect transistor (MOSFET) operation. Advanced Nanoscale MOSFET Architectures provides an in-depth review of modern metal–oxide–semiconductor field-effect transistor (MOSFET) device technologies and advancements, with information on their operation, various architectures, fabrication, materials, modeling and simulation methods, circuit applications, and other aspects related to nanoscale MOSFET technology. The text begins with an introduction to the foundational technology before moving on to describe challenges associated with the scaling of nanoscale devices. Other topics covered include device physics and operation, strain engineering for highly scaled MOSFETs, tunnel FET, graphene based field effect transistors, and more. The text also compares silicon bulk and devices, nanosheet transistors and introduces low-power circuit design using advanced MOSFETs.

Table of Contents:

[1] Emerging MOSFET Technologies; pp. 1

Kalyan Biswas and Angsuman Sarkar

[2] MOSFET: Device Physics and Operation; pp. 15

Ruthramurthy Balachandran, Savitesh M. Sharma, and Avtar Singh

[3] High-k Dielectrics in Next Generation VLSI/Mixed Signal Circuits; pp. 47

Asutosh Srivastava

[4] Consequential Effects of Trap Charges on Dielectric Defects for MU-G FET; pp. 61

Annada S. Lenka and Prasanna K. Sabu

[5] Strain Engineering for Highly Scaled MOSFETs; pp. 85

Chinmay K. Maiti, Taraprasanna Dash, Jhansirani Jena, and Eleena Mohapatra

[6] TCAD Analysis of Linearity Performance on Modified Ferroelectric Layer in FET Device with Spacer; pp. 113

Yash Pathak, Kajal Verma, Bansi Dhar Malhotra, and Rishu Chauzar

[7] Electrically Doped Nano Devices: A First Principle Paradigm; pp. 125

Debarato D. Ray, Pradipta Roy, and Debashis De

[8] Tunnel FET: Principles and Operations; pp. 143

Zahra Ahangari

[9] GaN Devices for Optoelectronics Applications; pp. 175

Nagarajan Mohankumar and Girish S. Mishra

[10] First Principles Theoretical Design on Graphene-Based Field-Effect Transistors; pp. 201

Yoshitaka Fujimoto

[11] Performance Analysis of Nanosheet Transistors for Analog ICs; pp. 221

Yogendra R Pundir, Arvind Bisht, and Pankaj K. Pal

[12] Low-Power Analog Amplifier Design using MOS Transistor in the Weak Inversion Mode; pp. 255

Soumya Pandit and Koyel Mukherjee

[13] Ultra-conductive Junctionless Tunnel FET-based Biosensor with Negative Capacitance; pp. 281

Palasri Dhar, Soumik Poddar, and Sunipa Roy

[14] Conclusion and Future Perspectives; pp. 301

Kalyan Biswas and Anqsuman Sarkar

[INDEX]; pp. 311

[paper] Rapid MOSFET Threshold Voltage Testing

Michael H. Herman; Trenton T. Nguyen; Ken Wong; Jeff Johnson; Ben Morris

Rapid MOSFET Threshold Voltage Testing

for High Throughput Semiconductor Process Monitoring

2024 IEEE 36th International Conference on Microelectronic Test Structures (ICMTS)

Edinburgh, United Kingdom, 2024, pp. 1-6

doi : 10.1109/ICMTS59902.2024.10520252

* Parametric Test Group, Advantest America, San Jose, CA 95134 United States

Abstract : We describe a method for rapid MOSFET threshold voltage (Vt) measurement. Multiple spot Ids measurements are compared to stored reference data. Each spot measurement yields an independent Vt estimate, and these enable quality metric calculation. A Vt and quality metric can be measured within 7 msec, using two spot measurements. The method permits parallel MOS testing.

FIG : Reference Ids-Vgs Curve with Gm curveB2Q8 device 2N7002 NMOS Transistor
at Vds = 0.05 Gm(max) 0.02272 at Vgs 2.25V; Extrap tangent line at 1.8665V

[paper] SiC Power MOSFET SPICE modelling

Akbar Ghulam

Accurate & Complete behaviourial SPICE modelling 

of commercial SiC Power MOSFET OF 1200V, 75A

25th EuroSimE, Catania, Italy, 2024, pp. 1-4,

DOI: 10.1109/EuroSimE60745.2024.10491420

* UNIPA Palermo (IT)

Abstract: Silicon Carbide (SiC) is proved to be an excellent replacement for Silicon in high voltage and high frequency applications due to its electro-thermal properties. Since SiC power MOSFETs have only recently been more widely available commercially, accurate simulation models are immediately required to forecast device behavior and facilitate circuit designs. The goal of this paper is to develop an accurate LTSPICE model based on a modified Enz-Krumenacher-Vittoz (EKV), MOSFET model for a 1200V, 30mΩ & 75ASiC power MOSFET “SCTW100N120G2AG” provided by STMicroelectronics that is currently on the market. The modified EKV model outperforms the reduced quadratic model by describing MOSFET behavior over different zones which are weak, moderate, and strong inversion zones with only a single equation. A wide range of experimental data was used to build the model's parameters. To estimate device performance in high frequency switching applications, the model has been expanded to include package parasitic components that include parasitic capacitances. The model's static and transient properties were simulated, and the results were compared with those acquired from the actual device.

FIG: The SiC MOSFET's circuit schematic utilizing a modified EKV model

Acknowledgements: We would like to thank STMicroelectronics, as for completion of this study has been greatly aided by their participation and availability of relevant data.

[paper] CMOS Technology for Analog Applications in High Energy Physics

Gianluca Traversi, Luigi Gaioni, Lodovico Ratti, Valerio Re and Elisa Riceputi

Characterization of a 28 nm CMOS Technology

for Analog Applications in High Energy Physics 

in IEEE Transactions on Nuclear Science

DOI: 10.1109/TNS.2024.3382348

1 INFN Pavia and Dipartimento di Ingegneria e Scienze Applicate, Uni. Bergamo, Italy
2 INFN Pavia and Dipartimento di Ingegneria Industriale e dell’Informazione, Uni. Pavia, Italy

Abstract: In the last few years, the 28 nm CMOS technology has raised interest in the High Energy Physics community for the design and implementation of readout integrated circuits for high granularity position sensitive detectors. This work is focused on the characterization of the 28 nm CMOS node with a particular focus on the analog performance. Small signal characteristics and the behavior of the white and 1/f noise components are studied as a function of the device polarity, dimensions, and bias conditions to provide guidelines for minimum noise design of front-end electronics. Comparison with data extracted from previous CMOS generations are also presented to assess the performance of the technology node under evaluation. 

Fig: Transconductance efficiency gm/ID as a function of the normalized

drain current IDL/W for NMOS (a) and PMOS (b) devices (|VDS| = 0.9 V)

Acknowledgment: The activity leading to the results presented in this paper was carried out in the framework of the Falaphel project, funded by the Italian Institute for Nuclear Physics (INFN). The authors wish to thank Prof. Massimo Manghisoni (University of Bergamo) for the valuable advice which contributed to improve this work and Dr. Stefano Bonaldo (University of Padova) for fruitful discussions on the measurement results. The authors wish to thank also Barbara Pini (INFN Torino) for the wire bonding of the chips, Emilio Meroni and Nicola Cattaneo (University of Bergamo) for the characterization activity.

[Habilitation] Assessment of novel devices in CMOS technology

Assessment of novel devices in CMOS technology

by electrical characterization and physics-based model

Habilitation Presented To Obtain The Authorization 

To Direct Research From Sorbonne University

Lionel Trojman, PhD

Sorbonne Université, 2020

Organization of the thesis

Chapter 1: This chapter extends research work after the author’s PhD study. It focuses on HfO2-based dielectric MOSFETs with sub-1nm EOT. The study explores the impact of transport factors like saturation velocity on planar MOSFETs and the mobility of FDSOI-UTBB MOSFETs. Notably, the back-biased effect is considered, and an inversion charge model is developed for different front and back biases.

Chapter 2: Emphasis the application of the statistical defect-centric model to assess the impact of channel hot carriers on the reliability of low-dimensional MOSFETs.

Chapter 3: This chapter shifts focus to GaN-on-Si wafer devices for power electronic applications. These devices integrate MOS-like structures into III-V material-based devices, specifically MOS-HEMT and GET-SBD.

Chapter 4: Investigates RERAM devices. It stems from cooperative research with UNICAL and a PhD program in collaboration with Aix-Marseille University

FIG: Description of the gate structure (half device) of the studied device including the parasitic capacitance inner fringing (CIF), outer fringe (COF) and Junction overlap capacitance (COV)

 

 

[paper] Polylogarithms in MOSFET Modeling

A. Ortiz-Conde and F. J. García-Sánchez

Recent Applications of Polylogarithms in MOSFET Modeling

2023 IEEE 33rd International Conference on Microelectronics

MIEL, Nis, Serbia, 2023, pp. 1-8

DOI: 10.1109/MIEL58498.2023.10315897

Department of Electronics and Circuits, Universidad Simón Bolívar, Caracas, Venezuela

Abstract: We present a review of recent uses of the special mathematical function known as the polylogarithm for MOSFET modeling applications. We first summarize some basic properties of polylogarithms, with a particular focus on those with negative exponential argument. After examining cases of the use of first order polylogarithms pertinent to electron device modeling, we explain the reasons that motivate the use of polylogarithms of diverse orders for formulating mono- and poly-crystalline succinct compact MOSFET models. We then analyze a particular representative example: the modeling of polysilicon MOSFETs using the polylogarithm. Recalling that polylogarithms may be used to faithfully represent Fermi-Dirac Integrals in general, and considering that they are analytically differentiable and integrable, we describe a full Fermi–Dirac Statistics-based version of the usually approximate Boltzmann Statistics-based MOSFET Surface Potential Equation (SPE).

TABLE: Some Features of Polylogarithms with Negative Exponential Argument

[paper] PSP RF Model

Xiaonian Liu^{1, 2} and Yansen Liu¹

A Scalable PSP RF Model for 0.11 µm MOSFETs

Progress In Electromagnetics Research Letters, Vol. 113, 43–51, 2023

DOI :10.2528/PIERL23081405

1 School of Physics and Electronics, Hunan Normal University, Changsha 410081, China.
2 Key Laboratory of Physics and Devices in Post-Moore Era, College of Hunan Province, Changsha 410081, China.

Abstract : An accurate, efficient and scalable SPICE model is essential for modern integrated circuits design, especially for radio frequency (RF) circuit design. A PSP based scalable RF model is extracted and verified in 0.11 CMOS manufacturing process. The S parameter measurement system and open-short de-embedding technique is applied. The macro-model equivalent subcircuit and parameters extraction strategy are discussed. The extracted model can match the de-embedded S parameters data well. By combining the model parameters’ dependencies on each geometry quantity, the scalable expression of parameters with all geometry quantities included can be obtained. This work can be a reference for the RF MOSFETs modeling and RF circuit design.

Fig: The RF PSP Model Subcircuit

Acknowledgment : This work is supported by the National Natural Science Foundation of China under Grant 62204083, and the Youth Fund of Education Department of Hunan Province under Grant 21B0057.

[book chapters] Equation-Based Compact Modeling

 

Debnath, P., Sarkar, B., & Chanda, M. (Eds.). (2023).

Differential Equation Based Solutions 

for Emerging Real-Time Problems

(1st ed.). CRC Press 

DOI 10.1201/9781003227847

Chapter: Differential Equation-Based Compact 2-D Modeling of Asymmetric Gate Oxide Heterojunction Tunnel FET; By: Sudipta Ghosh, Arghyadeep Sarkar

Abstract: Tunnel Field Effect Transistor (TFET) has emerged as an effective alternative device to replace MOSFET for a few decades. The major drawbacks of MOSFET devices are the short-channel effects, due to which the leakage current increases with a decrease in device dimension. So, scaling down TFET is more efficacious than that of MOSFETs. Sub-threshold swing (SS) is another advantageous characteristic of TFET devices for high-speed digital applications. In TFETs the SS could be well below 60 mV/decade, which is the thermal limit for MOSFET devices and therefore makes it more suitable than MOSFET for faster switching applications. It is observed from the literature studies that the performances of the TFET devices have been explored thoroughly by using 2-D TCAD simulation but an analytical model is always essential to understand the physical behavior of the device and the physics behind this; which facilitates further, the analysis of the device performances at circuit level as and when implemented.

Chapter: Differential Equation-Based Analytical Modeling of the Characteristics Parameters of the Junctionless MOSFET-Based Label-Free Biosensors; by: Manash Chanda, Papiya Debnath, Avtar Singh

Abstract: Recently Field Effect transistor (FET)-based biosensing applications have gained significant attention due to the demand for quick and accurate diagnosis of different enzymes, proteins, DNA, viruses, etc; cost-effective fabrication process; portability and better sensitivity and selectivity compared to the existing biosensors. FET is basically a three-terminal device with source, drain, and gate terminals. Basically, the gate terminal controls the current flow between the source and drain terminals. In FETs, first, a nanogap is created in the oxide layer or in the gate by etching adequate materials. When the biomolecules are trapped inside the nanocavity then the surface potentials change and also the threshold voltage varies. As a result, the output current also changes. Finally, by measuring the changes in the threshold voltage or the device current, one can easily detect the biomolecules easily.

[paper] FDSOI Threshold Voltage Model

Hung-Chi Han1, (Student, IEEE), Zhixing Zhao2, Steffen Lehmann2,

Edoardo Charbon1, (Fellow, IEEE), and Christian Enz1 (Life Fellow, IEEE)

Novel Approach to FDSOI Threshold Voltage Model Validated at Cryogenic Temperatures

in IEEE Access, DOI: 10.1109/ACCESS.2023.3283298

1 Ecole Polytechnique Fédérale de Lausanne (EPFL), 2000 Neuchâtel, Switzerland
2 GlobalFoundries, 01109 Dresden, Germany

Abstract: The paper presents a novel approach to to the modeling of the back-gate dependence of the threshold voltage of Fully Depleted Silicon-On-Insulator (FDSOI) MOSFETs down to cryogenic temperatures by using slope factors with a gate coupling effect. The FDSOI technology is well-known for its capability to modulate the threshold voltage efficiently by the back-gate voltage. The proposed model analytically demonstrates the threshold voltage as a function of the back-gate voltage without the pre-defined threshold condition, and it requires only a calibration point, i.e., a threshold voltage with the corresponding back-gate voltage, front- and back-gate slope factors, and work functions of front and back gates. The model has been validated over a wide range of the back-gate voltages at room temperature and down to 3 K. It is suitable for optimizing low-power circuits at cryogenic temperatures for quantum computing applications

FIG: Room temperature back-gate coefficient η versus VT−VB for an n-type conventional well (RVT) FDSOI FET with 1 µm of gate length and width. The θ=0 happens at VT−VB = −0.63V due to −0.63V of the front-back gate work function difference 

Acknowledgment: The authors would like to thank Claudia Kretzschmar from GlobalFoundries Germany and GlobalFoundries University Partnership Program for providing 22 FDX® test structures and support. Hung-Chi Han would like to thank Davide Braga from Fermi National Accelerator Laboratory for his valuable support. This project has received funding from the European Union’s Horizon 2020 Research & Innovation Program under grant agreement No. 871764. SEQUENCE.

[paper] Noise Characterization of MOSFETs for Cryogenic Electronics

Variable-Temperature Broadband Noise Characterization of MOSFETs

for Cryogenic Electronics: From Room Temperature down to 3K

Kenji Ohmori¹ and Shuhei Amakawa²

TechRxiv. DETM 2022 Preprint

DOI: 10.36227/techrxiv.21762917.v1

1 Device Lab Inc., Tsukuba, Ibaraki, Japan,

2 Hiroshima University, Higashihiroshima, Hiroshima, Japan

Abstract: A broadband noise measurement system is newly developed and demonstrated at temperatures between 3K and 300K. Using the system, wideband noise spectroscopy (WBNS) from 20kHz to 500MHz is carried out for the first time, revealing that shot noise is the dominant white noise down to 3K. The paper also suggests, by means of WBNS, the possibility of extracting the baseline noise characteristics, which do not include the noise component that varies a great deal from device to device.

FIG: a.) IdVg Curves at T = 2.9K ... 300K and b.) 1/f Noise at T=5K

Acknowledgement: 

This work was partially supported by NEDO-SBIR.

[paper] highly segmented hybrid pixel detectors

R. Ballabriga^a, J.A. Alozy^a, F.N. Bandi^a, G. Blaj^b, M. Campbell^a, P. Christodoulou^{a c d}, V. Coco^a, A. Dorda^{a e}, S. Emiliani^{a h}, K. Heijhoff f, E. Heijne a c, T. Hofmann^a, J. Kaplon^a, A. Koukab^h,
I. Kremastiotis^a, X. Llopart^a, M. Noy^a, A. Paterno^a, M. Piller^{a g}, J.M. Sallesse^h, V. Sriskaran^a,
L. Tlustos^{a c}, M. van Beuzekom^f

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volume 1045, 1 January 2023, 167489

DOI: 10.1016/j.nima.2022.167489

a CERN, Experimental Physics Department, Meyrin, 1211, Switzerland
b SLAC National Accelerator Laboratory, Menlo Park, 94025, CA, United States
c IEAP, Czech Technical University in Prague, Prague, 11000, Czech Republic
d Department of Biomedical technology, Faculty of Biomedical Engineering, Czech Technical University in Prague, nam. Sitna 3105, Kladno, 272 01, Czech Republic
e KIT - Karlsruhe Institute of Technology, Institute for Data Processing and Electronics (IPE), Hermann-von-Helmholtz-Platz 1, Eggenstein-Leopoldshafen, 76344, Germany
f Nikhef, Science Park 105, Amsterdam, 1098, Netherlands
g Institute of Electronics, Graz University of Technology, Graz, 8010, Austria
h Electron Device Modeling and Technology Laboratory (EDLAB), EPFL, Switzerland

Abstract: This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65 nm CMOS process, and consists of a four side buttable matrix of 448X512 pixels with 55µm pitch. The analog front-end has a gain of 36 mV/ke- when configured in High Gain Mode, and 20 mV/ke- when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e-rms and ~80e-rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode, the incoming hits can be time stamped within a 200ps time bin and the chip can deal with a maximum flux of 3.6MHz mm-2s-1. In photon counting mode, the chip can deal with up to 5GHz mm-2s-1. The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

Fig: Transconductance that can be obtained for the input transistor as an EKV function of the Inversion Coefficient (IC). The asymptotes for the velocity without and with velocity saturation are shown.

Acknowledgments: The authors would like to acknowledge the Medipix Collaborations for their continuous support in the design of hybrid pixel detector readout chips.

[paper] Cryogenic Characteristics of InGaAs MOSFET

L. Södergren, P. Olausson and E. Lind

Cryogenic Characteristics of InGaAs MOSFET

in IEEE TED, vol. 70, no. 3, pp. 1226-1230, March 2023,

DOI: 10.1109/TED.2023.3238382

Abstract: We present an investigation of the temperature dependence of the current characteristic of a long-channel InGaAs quantum well MOSFET. A model is developed, which includes the effects of band tail states, electron concentration-dependent mobility, and interface trap density to accurately explain the measured data over all modes of operation. The increased effect of remote impurity scattering is associated with mobility degradation in the subthreshold region. The device has been characterized down to 13 K, with a minimum inverse subthreshold slope of 8 mV/dec and a maximum ON-state mobility of 6700 cm2/Vs and with values of 75 mV/dec and 3000 cm2/Vs at room temperature.

FIG: Measured transfer characteristics at 13, 100, and 300 K together with the fit model with

(a) VDS=50 mV and (b) VDS=500 mV.

[paper] 50 Two-Transistor MOSFET Circuits

Harald Pretl* and Matthias Eberlein**

Fifty Nifty Variations of Two-Transistor Circuits: A tribute to the versatility of MOSFETs

IEEE Solid-State Circuits Magazine 13(3):38-46, August 2021

DOI: 10.1109/MSSC.2021.3088968  

  

* Institute for Integrated Circuits, JKU, Linz, Austria
** Semiconductor electronics, TU, Darmstadt, Germany

Abstract: We present a compendium of two-MOS-transistor circuits, spanning the range from simple standard configurations to ingenious arrangements. Using these building blocks, circuit designers can assemble a vast array of complex analog functions. This (incomplete) collection shall serve as a reference and inspiration to junior circuit designers and hopefully contains at least one unexpected example for the professional engineer.

Part 1/2 #thisismagic #circuit #mosfet

Part 2/2 #thisismagic #circuit #mosfet

Acknowledgments: We thank the reviewers for their many mindful suggestions. We want to thank our colleagues at the Institute for Integrated Circuits, Johannes Kepler University Linz, for their support in preparing this manuscript and for their many enlightening discussions.

[paper] DL Physics-Driven MOSFET Modeling

Ming-Yen Kao, H. Kam, and Chenming Hu, Life Fellow, IEEE

Deep-Learning-Assisted Physics-Driven MOSFET Current-Voltage Modeling

in IEEE Electron Device Letters

DOI: 10.1109/LED.2022.3168243

Abstract: In this work, we propose using deep learning to improve the accuracy of the partially-physics-based conventional MOSFET current-voltage model. The benefits of having some physics-driven features in the model are discussed. Using a portion of the Berkeley Short-channel IGFET Common-Multi-Gate (BSIM-CMG), the industry-standard FinFET and GAAFET compact model, as the physics model and a 3-layer neural network with 6 neurons per layer, the resultant model can well predict IV, output conductance, and transconductance of a TCAD-simulated gate-all-around transistor (GAAFET) with outstanding 3-sigma errors of 1.3%, 4.1%, and 2.9%, respectively. Implications for circuit simulation are also discussed.

Fig: (a) Model implementation for circuit simulations, without the relative gm and gds errors terms in the cost function, Model shows larger prediction error in (b) gm and (c) gds.

Acknowledgements: This work was supported by the Berkeley Device Modeling Center, 

UCB, CA (USA)

[paper] Noise Degradation and Recovery in Gamma-irradiated SOI nMOSFET

S.Amora^b, V.Kilchytska^a, F.Tounsi^a, N.André^a, M.Machhout^b, L.A.Francis^a, D.Flandre^a

Characteristics of noise degradation and recovery in gamma-irradiated SOI nMOSFET

with in-situ thermal annealing

Solid-State Electronics; 108300; online 7 April 2022, 

DOI: 10.1016/j.sse.2022.108300

   
a SMALL, ICTEAM Institute, Université catholique de Louvain (B)
b Faculté des Sciences de Université de Monastir (TN)

Abstract: This paper demonstrates a procedure for complete in-situ recovery of on-membrane CMOS devices from total ionizing dose (TID) defects induced by gamma radiation. Several annealing steps were applied using an integrated micro-heater with a maximum temperature of 365°C. The electrical characteristics of the on-membrane nMOSFET are recorded prior and during irradiation (up to 348 krad (Si)), as well as after each step of the in-situ thermal annealing. High-resolution current sampling measurements reveal the presence of oxide defects after irradiation, with a clear dominant single-trap signature in the random telegraph noise (RTN) traces. Drain current over time measurements are used for the trap identification and further for the defects' parameters extraction. The power spectral density (PSD) curves confirm a clear dominance of the RTN behavior in the low-frequency noise. A radiation-induced oxide trap is detected at 5.4 nm from the Si-SiO2 interface, with an energy of 0.086 eV from the Fermi level in the bandgap. After annealing, the RTN behavior vanishes with a further important reduction of flicker noise. Low-frequency noise measurements of the transistor confirmed the neutralization of oxide defects after annealing. The electro-thermal annealing of the nMOSFET allows a total recovery of its original characteristics after being severely degraded by radiation-induced defects.

Fig: Device under test : (a) cross-section schematic, (b) microscopic front view

showing the membrane and other embedded elements

[paper] Electron Mobility Distribution in FD-SOI MOSFETs

Nima Dehdashti Akhavan^a, Gilberto Antonio Umana-Membreno^a, Renjie Gu^a, Jarek Antoszewski^a, Lorenzo Faraone^a and Sorin Cristoloveanu^b

Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach

Solid-State Electronics; Available online 14 March 2022, 108283

DOI: 10.1016/j.sse.2022.108283

   
a The University of Western Australia, Crawley (AU)
b IMEP-LAHC, INP Minatec, Grenoble (F)

Abstract: Modern electronic devices consist of several semiconductor layers, where each layer exhibits a unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Fig: Qinv is defined as the electron density per unit length at the maximum 

of the first subband (top of the barrier) often referred to as a “virtual source”

Acknowledgements: This work was supported by the Australian Research Council (DP170104555), the Horizon 2020 ASCENT EU project (Access to European Nanoelectronics Network – Project no. 654384), the Western Australian node of the Australian National Fabrication Facility (ANFF), and the Western Australian Government’s Department of Jobs, Tourism, Science and Innovation.

[paper] Charge Trapping/Detrapping in Scaled MOSFETs

Ruben Asanovski, Pierpaolo Palestri*, and Luca Selmi

Importance of Charge Trapping/Detrapping Involving the Gate Electrode on the Noise Currents of Scaled MOSFETs

IEEE TED, Vol. 69, No. 3, March 2022 1313

DOI: 10.1109/TED.2022.3147158

  

 Università degli Studi di Modena e Reggio Emilia, Modena, Italy

*Università degli Studi di Udine, Udine, Italy

Abstract: Carrier trapping/detrapping from/to the gate into dielectric traps is often neglected when modeling noise in MOSFETs and, to the best of our knowledge, no systematic study of its impacts on scaled devices is available. In this article, we show that this trapping mechanism cannot be neglected in nowadays aggressively scaled gate dielectric thicknesses without causing errors up to several orders of magnitude in the estimation of the drain current noise. The noise generation mechanism is modeled analytically and then analyzed through the use of 2-D and 3-D TCAD simulations of scaled MOSFETs with different architectures and channel/gate-stack materials. The results provide new insights for technology and device designers, highlight the relevance of the choice of the gate metal work function (WF) and the role of valence band electron trapping at high gate voltages.

Fig: (a) FinFET with the single trap location highlighted. (b) Drain current noise comparison between TCAD simulations at VGS = 0.7 V, VDS = 25 mV and single trap located as in (a).

[paper] Modeling of SIC VDMOS FET

Anirban Kar∗, Ahtisham Pampori∗, Noriyoshi Hashimoto† and Yogesh Singh Chauhan∗

A Charge-Based Silicon Carbide MOSFET Compact Model for Power Electronics Applications

2021 IEEE 8th Uttar Pradesh Section UPCON)

DOI: 10.1109/UPCON52273.2021.9667643

∗Department of Electrical Engineering, IIT Kanpur (IN)
†Keysight Technologies (J)

Abstract: This paper presents a charge-based compact model for Silicon Carbide (SiC) power MOSFETs, which captures the static characteristics of the device over a wide range of voltages and currents. The drift region resistance and charges in the channel have been formulated to calculate the drain current in a self-consistent manner. The proposed model has been validated against the measured transfer and output characteristics of a commercial 1.2kV power MOSFET (Infineon IMW120R045M1) with a maximum current rating of 52A.

Fig: a) Transfer characteristics of SiC MOSFET with Vd=1 to 20V

b) Transconductance of SiC MOSFET with Vd=1 to 20V 

Acknowledgement: This work was supported in part by the Swarna Jayanti Fellowship under Grant DST/SJF/ETA02/2017-18 and in part by the Department of Science and Technology through the FIST Scheme under Grant SR/FST/ETII-072/2016 and Keysight Technologies, USA. The measurement of the device was carried out at Keysight Technologies, Japan.

[paper] Compact Modelling of Si Nanowire/Nanosheet MOSFETs

A. Cerdeira¹, M. Estrada¹, and M. A. Pavanello²

On the compact modelling of Si nanowire and Si nanosheet MOSFETs

Semiconductor Science and Technology, vol. 37, no. 2, p. 025014, Jan. 2022.

DOI: 10.1088/1361-6641/ac45c0

   

1 Centro de lnvestigacién y de Estudios Avanzados del IPN, Mexico City, Mexico
2 Centro Universitario PEI, Sao Bernardo do Cainpo, Sao Paulo, Brazil

Abstract: In this paper, three-dimensional technology computer aided design simulations are used to show that the electron concentration, current density, and electric field distribution from the interface at the lateral channels and from the top channel to the centre of the silicon wire, in nanowire and nanosheet structures, are practically same. This characteristic makes it possible to consider that the total channel width for these structures is equal to the perimeter of the transistor sheet, allowing to extend of the application of the symmetric doped double-gate model (SDDGM) model to nanowires and nanosheets metal-oxide-semiconductor field effect transistors, with no need to include new parameters. The model SDDGM is validated for this application using several measured and simulated structures of nanowires and nanosheets transistors, with different aspect ratios of fin width and fin height, showing very good agreement between measured or simulated characteristics and modelled. SDDGM is encoded in Verilog-A language and implemented in SPICE circuit simulator.

Fig: a.) Normalized measured and modelled transfer characteristics of stacked transistor in the linear region at VDS=0.025V and in saturation region at VDS=0.75V; b.) Output characteristic and conductance at VGS=1V.

Acknowledgments: The authors are grateful to CEA—Leti for providing the exper- imental samples used in this paper. This work was supported by the CONACYT project 236887, CNPq, Sao Paulo Research Foundation (FAPESP) Grants 2015/ 1049 1-7 and 2019/ 15500- 5, and the IBM/STMicroelectronics/Leti Joint Development Alliance.