Tuesday, March 31, 2020

#paper: Bootsma, G.J., Nordström, H., Eriksson, M. and Jaffray, D.A., 2020. Monte Carlo kilovoltage X-ray tube simulation: A statistical analysis and compact simulation method. Physica Medica, 72, pp.80-87 https://t.co/9C1S4Y3023 https://t.co/D7RzqFb7tP


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March 31, 2020 at 09:18PM
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#COVID-19 Related Research and Technologies #Free to Access in #IEEE #Xplore https://t.co/8wtkdHydcI #paper https://t.co/kKCTCwfSCt


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March 31, 2020 at 02:50PM
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Professional #Ventilator Design #OpenSource Today by #Medtronic https://t.co/YkzX6fpU80 https://t.co/KA23i6RVDJ


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March 31, 2020 at 11:01AM
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Monday, March 30, 2020

#paper: N. Zagni et al. "Systematic Modeling of Electrostatics, Transport, and Statistical Variability Effects of Interface Traps in End-of-the-Roadmap III–V MOSFETs," in IEEE TED, vol. 67, no. 4, pp. 1560-1566, April 2020. https://t.co/wtk1U4sFuB https://t.co/xWzZ5GnQal


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March 30, 2020 at 05:01PM
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#paper: X. Li, T. Pu, L. Li and J. Ao, "Enhanced Sensitivity of GaN-Based Temperature Sensor by Using the Series Schottky Barrier Diode Structure," in IEEE EDL, vol. 41, no. 4, pp. 601-604, April 2020 https://t.co/koGfb8GeST https://t.co/LCE1l2wdly


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March 30, 2020 at 11:14AM
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conference paper reached 700 reads

M. Bucher, A. Bazigos and W. Grabinski, "Determining MOSFET Parameters in Moderate Inversion," 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems, Krakow, 2007, pp. 1-4.

Abstract: Deep submicron CMOS technology scaling leads to reduced strong inversion voltage range due to non-scalability of threshold voltage, while supply voltage is reduced. Moderate inversion operation therefore becomes increasingly important. In this paper, a new method of determining MOSFET parameters in moderate inversion is presented. Model parameters are determined using a constant current bias technique, where the biasing current is estimated from the transconductance-to-current ratio. This technique is largely insensitive to mobility effects and series resistance. Statistical data measured on 40 dies a 0.25 um standard CMOS technology are used for the illustration of this method.

#paper Y. Nakamura, N. Kuroda, T. Yanagi, H. Sakairi and K. Nakahara, "High-Voltage and High-Current Id–Vds Measurement Method for Power Transistors Improved by Reducing Self-Heating," in IEEE EDS (Open Access), vol. 41, no. 4, pp. 581-584, April 2020. https://t.co/85eA0jPQKb https://t.co/PT6CUQRELM


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March 30, 2020 at 09:52AM
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Sunday, March 29, 2020

#paper: T. Mikolajick, U. Schroeder and S. Slesazeck, "The Past, the Present, and the Future of Ferroelectric Memories," in IEEE TED, vol. 67, no. 4, pp. 1434-1443, April 2020. https://t.co/OmPJ0xf6wU https://t.co/jWifCPdJ1D


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March 29, 2020 at 06:08PM
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#paper: Scientists from the POWERlab at #EPFL, have built a nanodevice capable of producing high-power Terahertz (#THz) waves https://t.co/Cl6jBInynx https://t.co/4PIJmN6Jpm


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March 29, 2020 at 05:38PM
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#paper: L. Nagy, D. Arbet, M. Kovac, M. Potocny, M. Sovcik and V. Stopjakova, "EKV Transistor Model For Ultra Low-Voltage Bulk-Driven Circuits," 2019 17th ICETA, Starý Smokovec, Slovakia, 2019, pp. 546-551. https://t.co/eT4lyE9Uwe https://t.co/DABJ68O7ar


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March 29, 2020 at 04:33PM
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Friday, March 27, 2020

The Art of Reverse Engineering appeared first on #OpenSource For You https://t.co/B1sKAzlzAh https://t.co/OZ4ErMqS0Y


from Twitter https://twitter.com/wladek60

March 27, 2020 at 04:44PM
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#paper: Q. Huo et al., "A Novel General Compact Model Approach for 7-nm Technology Node Circuit Optimization From Device Perspective and Beyond," in IEEE J-EDS, vol. 8, pp. 295-301, 2020 DOI: 10.1109/JEDS.2020.2980441 https://t.co/QrqdHdvHmT https://t.co/vTr39EBQ6r


from Twitter https://twitter.com/wladek60

March 27, 2020 at 10:23AM
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100 #wafer #fabs taken out of production in the last decade https://t.co/wtWEahOHfF #paper https://t.co/FVBSYTOYld


from Twitter https://twitter.com/wladek60

March 27, 2020 at 09:46AM
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[blog] Image Sensors World

blog shares news and discussions about image sensors

Read 5 Recent Comments:
I think the FOV of the ST Micro Lidar is too narro... - 3/27/2020 - Anonymous
Announced to the press but ST page lists them as &... - 3/26/2020 - Anonymous
Who is supplying this LIDAR Scanner? - 3/26/2020 - Anonymous
"from the financial sector than a biological ... - 3/26/2020 - Anonymous
Is this the STMicroelectronics MEMS lidar? Or what... - 3/25/2020 - Dharmaone

Since the end of January, the #opensource community has contributed to thousands of open source repositories that mention coronavirus or #COVID-19 https://t.co/VsVksULG6l https://t.co/096vvMt3Ed


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March 27, 2020 at 09:07AM
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Tuesday, March 24, 2020

#paper A. A. Zope, J. Chang, T. Liu and S. Li, "A CMOS-MEMS Thermal-Piezoresistive Oscillator for Mass Sensing Applications," in IEEE TED, vol. 67, no. 3, pp. 1183-1191, March 2020 doi: 10.1109/TED.2020.2969967 https://t.co/A1UCrpxzZw https://t.co/7cm4KbfWMn


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March 24, 2020 at 05:59PM
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#paper: A. Yesayan, F. Jazaeri and J. Sallese, "Analytical Modeling of Double-Gate and Nanowire Junctionless ISFETs," in IEEE TED, vol. 67, no. 3, pp. 1157-1164, March 2020 doi: 10.1109/TED.2020.2965167 https://t.co/ZQqam0Idam https://t.co/fLVyDK5rfB


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March 24, 2020 at 04:29PM
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#paper M. H. Mohamed Sathik, P. Sundararajan, F. Sasongko, J. Pou and S. Natarajan, "Comparative Analysis of IGBT Parameters Variation Under Different Accelerated Aging Tests," in IEEE TED, vol. 67, no. 3, pp. 1098-1105 doi: 10.1109/TED.2020.2968617 https://t.co/pcQI7dpLeO https://t.co/9Sz1Vqnaf2


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March 24, 2020 at 11:15AM
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#paper: W. Chen, J. Cheng and X. B. Chen, "A Novel IGBT With High-k Dielectric Modulation Achieving Ultralow Turn-Off Loss," in IEEE TED, vol. 67, no. 3, pp. 1066-1070, March 2020 doi: 10.1109/TED.2020.2964879 https://t.co/uoh7n0NYFa https://t.co/wdqFNSMBur


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March 24, 2020 at 10:24AM
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Monday, March 23, 2020

[paper] Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs

Charge-based Modeling of Ultra Narrow Cylindrical Nanowire FETs 
Danial Shafizade, Majid Shalchian and Farzan Jazaeri
IEEE TED, Vol. XX, No. XX, 15 March 2020

Abstract: This brief proposes an analytical approach to model the dc electrical behavior of extremely narrow cylindrical junctionless nanowire field-effect transistor (JLNW-FET). The model includes explicit expressions, taking into account the first order perturbation theory for calculating eigenstates and corresponding wave functions obtained by the Schrodinger equation in the cylindrical coordinate. Assessment of the proposed model with technology computer-aided design (TCAD) simulations and measurement results confirms its validity for all regions of operation. This represents an essential step toward the analysis of circuits mainly biosensors based on junctionless nanowire transistors.

MicroTec: Semiconductor Process and Device Simulator

Software Package for 2D Process and Device Simulation
Version 4.0 for Windows
User’s Manual
Publisher: Siborg Systems Inc
Editor: Michael S. Obrecht

MicroTec allows 2D silicon process modeling including implantation, diffusion and oxidation and 2D steady-state semiconductor device simulation like MOSFET, DMOS, JFET, BJT, IGBT, Schottky, photosensitive devices etc. Although MicroTec is significantly simplified compared to widely available commercial simulators, it nevertheless is a very powerful modeling tool for industrial semiconductor process/device design. In many instances MicroTec outperforms existing commercial tools and it is remarkably robust and easy-to-use.

FIG: MicroTec SibGraf GUI windows




#paper: J. N. Ramos-Silva, A. Pacheco-Sinchez, M. A. Enciso-Aguilar, D. Jimenez, E. Ramirez-Garcia: Small-signal parameters extraction and noise analysis of CNTFETs, IOPscience SST 35(4), 045024 (Mar 2020) doi:10.1088/1361-6641/ab760b https://t.co/vY5g9t4h1B https://t.co/L00nT1AkMS


from Twitter https://twitter.com/wladek60

March 23, 2020 at 11:01AM
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Thursday, March 19, 2020

#XFAB Further Expands its #SiC Capacity and Adds New In-House Epitaxy Capabilities https://t.co/1ZecCr6k92 #paper https://t.co/5RCDzb1cbv


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March 19, 2020 at 11:30AM
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[paper] Negative Capacitance Double-Gate JunctionlessFETs


Negative Capacitance Double-Gate JunctionlessFETs: A Charge-based Modeling Investigation of Swing, Overdrive and Short Channel Effect
Amin Rassekh, Jean-Michel Sallese, Farzan Jazaeri, Morteza Fathipour and Adrian M. Ionescu
IEEE TED, Vol. XX, No. XX, March 3, 2020

Abstract: In this paper, an analytical predictive model of the negative capacitance (NC) effect in symmetric long channel double-gate junctionless transistor is proposed based on a charge-based model. In particular, we have investigated the effect of the thickness of the ferroelectricon the I-V characteristics. Importantly, for the first time,our model predicts that the negative capacitance minimizes short channel effects and enhances current over-drive, enabling both low power operation and more efficient transistor size scaling, while the effect on reducing subthreshold slope shows systematic improvement, with subthermionic subthreshold slope values at high current levels (0.1 μA/μm). Our predictive results in a long channel junctionless with NC show an improvement in ON current by a factor of 6 in comparison to junctionless FET. The set of equations can be used as a basis to explore how such a technology booster and its scaling will impact the main figures of merit of the device in terms of power performances and gives a clear understanding of the device physics. The validity of the analytical model is confirmed by extensive comparisons with numerical TCAD simulations in all regions of operation, from deep depletion to accumulation and from linear to saturation.
Fig: The difference of the potential across the ferroelectric (left axis) and the difference of total charge density of ferroelectric (right axis) in high VDS and low VDS versus the channel length. ∆Vf somehow represents ∆VG (The difference of VG in high and low VDS). The inset illustrates the schematic of the I-V characteristic of a regular double gate JLFET and a double gate JLFET with negative capacitance at low and high VDS.


Wednesday, March 18, 2020

#paper: J. Leise et al., "Charge-Based Compact Modeling of Capacitances in Staggered Multi-Finger OTFTs," in IEEE J-EDS doi: 10.1109/JEDS.2020.2978400 https://t.co/FJVoSI3mJ5 https://t.co/3xiWGBvVcj


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March 18, 2020 at 02:47PM
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Tuesday, March 17, 2020

#paper: Keene, S., van de Burgt, Y. Lowering the threshold for bioelectronics. Nat. Mater. (2020) https://t.co/Vro0bQq2ND https://t.co/oeNFCdGouJ https://t.co/VwLwojqZh3


from Twitter https://twitter.com/wladek60

March 17, 2020 at 05:44PM
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[postponed]: EUROSOI-ULIS 2020 organizers have announced that the conference and of the associated satellite events will be postponed to August 31st - September 4th https://t.co/fWjf3w8FGp #paper https://t.co/2WUnHvq2dg


from Twitter https://twitter.com/wladek60

March 17, 2020 at 04:16PM
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Monday, March 16, 2020

Thursday, March 12, 2020

Ultimate Medical #Hackathon: How Fast Can We Design and Deploy an #opensource #Ventilator? https://t.co/nCVKtlq28P https://t.co/vQWAkeEaZn


from Twitter https://twitter.com/wladek60

March 12, 2020 at 02:43PM
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How to write effective documentation for your #opensource project https://t.co/6ub8SQhZiv https://t.co/2bSdgsa884


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March 12, 2020 at 11:32AM
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ESSCIRC ESSDERC 2020 | TPC Meeting goes VIRTUAL


GRENOBLE (FRANCE) - September 14-18, 2020

Dear TPC members,​
The safety and health of all ESSCIRC-ESSDERC TPC and Steering Committee members, and generally of IEEE SSCS and EDS members, volunteers, and attendees of SSCS and EDS events are our first priority. Given the currently sanitary situation related to corona-virus, and after consulting with our Steering Committee and SSCS and EDS direction, the ESSCIRC-ESSDERC 2020 Conference Organizing Committee has decided to organize a virtual paper selection meeting. We want to ensure a high scientific quality of the paper selection process, and we want to make sure each TPC member can provide high quality feedback in the same manner.

Regarding the different meeting:

  • The virtual participation of ALL TPC members is mandatory
  • We are currently working on the organization modalities, and we will inform you soon about the practical organization: phone bridges and screen sharing software will be put in place for each track in order to properly be able to discuss and select the best papers
  • We will try to accommodate a time schedule fitting to most of WW time zones represented in our TPC
  • The final dates of this virtual meeting will be very close to the initially scheduled one, i.e. May 18th 2020 for the TPC meeting, and May 19th for the SC meetings

The paper submission deadline stays the same, April 17th, and we strongly encourage you and your research teams to submit papers. As well, please do advertise among your personal networks the paper submission to our conference.
On a more positive note, ESSCIRC-ESSDERC 2020 paper selection meeting will be the first full virtual SSCS/EDS of such type of meeting. With this new experience, we will learn new ways to better serve our community and also reduce our carbon footprint.
Thank you very much for your understanding, and we count on the support of each and every TPC and SC member to make of ESSCIRC-ESSDERC 2020 a successful conference even in times of crisis!

Kind regards,

Andreia Cathelin, ESSCIRC TPC chair
Sylvain Clerc, ESSCIRC TPC co-chairFrancois
Andrieu, ESSDERC TPC chair
Maud Vinet, ESSDERC TPC co-chair
Thomas Ernst, General Chair
Dominique Thomas, General co-chair











x

Tuesday, March 10, 2020

Senior and Junior Researcher positions at URV, in Tarragona, Spain

The Nanoelectronic and Photonic Systems (NEPHOS) Group at the Department of Electronic, Electrical and Automatic Control Engineering (DEEEiA) of the Universitat Rovira i Virgili (URV) in Tarragona, Spain, is looking for candidades for long-term Senior and Junior Researcher Contracts funded by URV and the Spanish Ministry of Science.

Candidates with less than 7 years of postdoctoral research outside Spain can apply for the Junior position, with a  minimu duration of 4 years.

Candidates with more than 7 years of postdoctoral research outside Spain can apply for the Junior position, which after 4 years can become permanent.

The selected candidates will propose  research and teaching project together with the hosting group at URV.

Candidates must have performed important contributions in the field of semiconductor devices.

The NEPJHOS Group at URV is currently working on the physics, characterization and modeling (in particular compact modeling) of emerging devices, and also in the fabrication and characterization of nanostructured organic photovoltaic devices. Regarding emerging devices, the present interests of the group at URV are the characterization and modeling of nanowire MOSFETs, GaN HEMTs, Graphene and 2D semiconductor FETs and organic and oxide TFTs. Other interests are the fabrication of polymeric TFTs and the modeling of organic solar cells.

Candidates must send their CVs, by March 18 to:

benjamin.iniguez@urv.cat

Tarragona is about 100 Km south from Barcelona, on the coast (the so-called "Costa Daurada", Golden Coast). Traveling to Tarragona from Barcelona is easier. There are frequent direct buses between Tarragona and Barcelona Airport, and also frequent trains between Tarragona and Barcelona. Besides, from some European cities it is possible to fly to Reus Airport, which is about 10 Km from Tarragona.

Tarragona is one of the most important hubs of tourism in Europe, not only because of the nice beaches around the city, but also because of its historical landmarks.. Tarragona was a very important city of the Roman Empire. In 2000 UNESCO committee officially declared the Roman archaeological complex of Tarraco (name of Tarragona during the Roman Empire) a World Heritage Site. This recognition is intended to help ensure the conservation of the monuments, as well as to introduce them to the broader international public.

#paper A 3D map of atoms in 2D materials [Nature Materials, doi:10.1038/s41563-020-0646-3] Scanning atomic electron tomography measurements reveal the 3D local structure around single dopant atoms in 2D transition metal dichalcogenides https://t.co/oeNFCdXZTj https://t.co/2zG0FdpduE


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March 10, 2020 at 04:15PM
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#paper: Guest Editorial for the special issue on devices and circuits for millimeter‐wave and THz applications by Yuehang Xu First published: 09 March 2020 https://t.co/886FiJL5zU https://t.co/xSbxKCGFub https://t.co/cbQzWbTh4Z


from Twitter https://twitter.com/wladek60

March 10, 2020 at 02:57PM
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François Anceau, Founder of CMP, has died. He was 80. "Today is a sad day for the entire CMP family," CMP’s Director Kholdoun Torki said. "François was a visionary, he influenced generations of microelectronic developments in France" https://t.co/K9ASeQmTsX #paper https://t.co/mT5RVrnxme


from Twitter https://twitter.com/wladek60

March 10, 2020 at 11:23AM
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article reached 1500 reads


A. Bazigos, M. Bucher, J. Assenmacher, S. Decker, W. Grabinski and Y. Papananos, "An Adjusted Constant-Current Method to Determine Saturated and Linear Mode Threshold Voltage of MOSFETs," in IEEE TED, vol. 58, no. 11, pp. 3751-3758, Nov. 2011.

Abstract: The constant-current (CC) method uses a current criterion to determine the threshold voltage (VTH) of metal-oxide-semiconductor (MOS) field-effect transistors. We show that using the same current criterion in both saturation and linear modes leads to inconsistent results and incorrect interpretation of effects, such as drain-induced barrier lowering in advanced CMOS halo-implanted devices. The generalized adjusted CC method is based on the theory of the charge-based MOS transistor model. It introduces an adjusted current criterion, depending on VDS, allowing to coherently determine VTH for the entire range of V DS from linear operation to saturation. The method uses commonly available ID versus VG data with focus on moderate inversion. The method is validated with respect to the ideal surface potential model, and its suitability is demonstrated with technology-computer-aided-design data from a 65-nm CMOS technology and measured data from a 90-nm CMOS technology. Comparison with other widely used threshold voltage extraction methods is provided.

Monday, March 9, 2020

CICC 2020 March 22 – March 25, 2020 Virtually from anywhere! https://t.co/6LMk0g4HDq #paper https://t.co/FTH07ngklp


from Twitter https://twitter.com/wladek60

March 09, 2020 at 04:03PM
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Friday, March 6, 2020

The New Dates of SEMICON/FPD China 2020 https://t.co/m1znJk8eKK #paper https://t.co/nUAveoEvpl


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March 06, 2020 at 01:15PM
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#paper: Y. Liu, S. Yang and K. Sheng, "Design and Optimization of Vertical GaN PiN Diodes With Fluorine-Implanted Termination," in IEEE Journal of the Electron Devices Society, vol. 8, pp. 241-250, 2020 doi: 10.1109/JEDS.2020.2975220 https://t.co/34ZWW1P73Y https://t.co/hKNGErgo4I


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March 06, 2020 at 09:17AM
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Thursday, March 5, 2020

#paper: S. Mocevic et al., "Comparison and Discussion on Shortcircuit Protections for SiC MOSFET Modules: Desaturation vs. Rogowski Switch-Current Sensor," in IEEE Transactions on Industry Applications doi: 10.1109/TIA.2020.2972816 https://t.co/qYVwtxy2BF https://t.co/Z4oY9m6Dhl


from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:59PM
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#paper: Q. Huo et al., "Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond," in IEEE Transactions on Electron Devices, vol. 67, no. 3, pp. 907-914, March 2020 doi: 10.1109/TED.2020.2964610 https://t.co/wEf5wGKzFv https://t.co/AGBu4ZUtVR


from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:56PM
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#DATE 2020 in Grenoble replaced by a virtual conference that will be scheduled in the coming weeks https://t.co/vwd8IZqhPo #paper https://t.co/FNMBVw2LUl


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March 05, 2020 at 03:30PM
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#EDTM 2020 Conference going Virtual -The conference will be held as a Virtual conference with all presentations be posted online. -The pre-conference Tutorials and Short Courses on March 15th, 2020 is cancelled https://t.co/x9cC8kKu6D #paper https://t.co/M8C5uO6DQY


from Twitter https://twitter.com/wladek60

March 05, 2020 at 03:24PM
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Wednesday, March 4, 2020

#paper: Krishna Pradeep, Patrick Scheer, Thierry Poiroux, André Juge and Gerard Ghibaudo; In-Wafer variability in FD-SOI MOSFETs: Detailed analysis and statistical modelling" Accepted Manuscript online 27 February 2020 by IOP Publishing Ltd https://t.co/rEjVnoRLuH https://t.co/V98FnxCpeo


from Twitter https://twitter.com/wladek60

March 04, 2020 at 02:51PM
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#paper #PhD: Michael Kollmitzer: Modeling of reverse current effects in trench-based smart power technologies. Gottfried Wilhelm Leibniz Universität, Diss., 2019, viii, 141 S. DOI: https://t.co/Uz3n1mRzzt https://t.co/mbBC0FR04m https://t.co/CVFveW4DXr


from Twitter https://twitter.com/wladek60

March 04, 2020 at 02:34PM
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Tuesday, March 3, 2020

#paper: S. Rhee et al. "Extension of the DG Model to the Second-Order Quantum Correction for Analysis of the Single-Charge Effect in Sub-10-nm MOS Devices," in IEEE JEDS, vol. 8, pp. 213-222, 2020 doi: 10.1109/JEDS.2020.2971426 https://t.co/LhdoMi9pP3 https://t.co/YgUVWiBxlv


from Twitter https://twitter.com/wladek60

March 03, 2020 at 08:23AM
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Monday, March 2, 2020

“It is predicted that in 2030 transistors will be a sixth smaller" by Stephen Crosher https://t.co/ErClcb0e2R #paper https://t.co/PuTy7flK9O


from Twitter https://twitter.com/wladek60

March 02, 2020 at 08:42AM
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#paper: A. Debnath, N. DasGupta and A. DasGupta, "Charge-Based Compact Model of Gate Leakage Current for AlInN/GaN and AlGaN/GaN HEMTs," in IEEE TED, vol. 67, no. 3, pp. 834-840, March 2020 doi: 10.1109/TED.2020.2965561 https://t.co/2HcKKjKOqE https://t.co/m6cKvAatEC


from Twitter https://twitter.com/wladek60

March 02, 2020 at 08:29AM
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