Friday, October 29, 2010

PRIME 2011 Conference

4-8 July 2011, Madonna di Campiglio (TN), Italy

The main objectives of PRIME 2011 Conference are:
  • to encourage favorable exposure to Ph.D. students in the early stages of their careers
  • to benchmark Ph.D. research in a friendly and cooperative environment
  • to enable sharing of student and supervisor experiences of scientific and engineering research
  • to connect Ph.D. students and their supervisors with companies and research centers
Paper Submission
The PRIME 2011 conference will allow only electronic submission of papers in PDF format (maximum file size must not exceed 2 Mbytes). Papers must not exceed four A4 pages with all illustrations and references included. The quality of the conference will be guaranteed by a thoroughly selected Technical Program Committee, which will provide detailed feedback to the authors. The accepted papers in the final camera ready format will be available on IEEE Xplore database. Papers submission will be opened during the first week of January, 2011. Manuscript guidelines as well as instructions on how to submit electronically your paper will be available soon on the conference web page.


14 inch Transparent OLED Display Notebook from Samsung mobile

I couldn't resist the temptation to share this...

Thursday, October 28, 2010

TriQuint rolls new GaAs foundry process

RF chip maker TriQuint Semiconductor Inc. has released its latest 150-mm gallium arsenide (GaAs) commercial foundry process. The process, dubbed TQP15, is targeted at the Ka-band segment. It is designed for building millimeter wave (mmWave) MMICs for applications such as VSAT, satellite communications and point to point radios [read more...]

Wednesday, October 27, 2010

New papers (October 27, 2010)

  • Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis (abstract)
  • Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method (abstract)
  • A Physics-Based Compact Model for Polysilicon Resistors (abstract)
  • The Equivalent-Thickness Concept for Doped Symmetric DG MOSFETs (abstract)
  • An Analytical I–V Model for Surrounding-Gate Transistors That Includes Quantum and Velocity Overshoot Effects (abstract)
  • Failure of the Scalar Dielectric Function Approach for the Screening Modeling in Double-Gate SOI MOSFETs and in FinFETs (abstract)
  • Device Physics and Characteristics of Graphene Nanoribbon Tunneling FETs (abstract)
  • Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges (abstract)

And other papers that I've found interesting:

  • Dual Threshold Voltage Organic Thin-Film Transistor Technology (abstract)
  • Complementary Organic Circuits Using Evaporated $ hbox{F}_{16}hbox{CuPc}$ and Inkjet Printing of PQT (abstract)
  • Low-Voltage High-Performance Pentacene Thin-Film Transistors With Ultrathin PVP/High- $kappa$ HfLaO Hybrid Gate Dielectric (abstract)
  • High-Performance Pentacene Thin-Film Transistors Fabricated by Organic Vapor-Jet Printing (abstract)
  • Magnetic-Field Area Sensor Using Poly-Si Micro Hall Devices (abstract)
  • On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits (abstract)
  • On Undetectable Faults and Fault Diagnosis (abstract)

Monday, October 25, 2010

Job offers in LinkedIn: RF Modeling Device Engineer

Remember, this is only for information. We're not connected to them!

HIRING - Peregrine Semiconductor - RF Modeling Device Engineer

Click Here to Apply:

Job Description:
This position is responsible for:
Member of team responsible for device modeling of Peregrine’s patented high-performance UltraCMOSTM silicon-on-sapphire CMOS process and packaging technology. The candidate will work closely with modeling engineers and CAD to support our design groups and external foundry customers.

Roles & Responsibilities will include:
• Responsible for modeling of passive components.
• Responsible for parasitic analysis of RF active components and BEOL.
• Model extraction for components on-wafer, modules, and packages.
• Manufacturing data analysis to develop statistical and corner models.
• Test chip DOE development, layout, and measurement.
• Provide guidance to design teams on best practice.


Minimum Requirements:
• Ph.D. in Physics or Electrical Engineering (MS okay with demonstrated experience)
• Understanding of RF device performance metrics
• Experience using SPICE like circuit simulators to develop sub-circuit models.
• Experience using EM simulators (HFSS, Momentum, etc.) to study device performance.
• Demonstrated ability to extract models from measured data.
• Demonstrated problem solving skills.

The following traits are highly valued:
• Strong programming background and ability to develop automation scripts.
• Experience with Matlab, ICCAP, or other tool for model extraction.
• Layout optimization for RF applications.
• Experience configuring and automating test equipment.
• Large signal RF device characterization.

Friday, October 15, 2010

[mos-ak] MOS-AK/GSA Seville Workshop Press Release

Press release:
"MOS-AK/GSA Modeling Working Group Holds Workshop in Seville"
can be found on the GSA site at

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Modelling people wanted...

I copy from LinkedIn:

Looking for PhD/ MS candidates in device physics , modelling back ground for one of the Semiconductor research and development centre at Bangalore .

see more...

Wednesday, October 13, 2010

Accurately simulate an LED

Accurately simulate an LED: " View as PDF Read More Design IdeasSolid-state-lighting applicatio..."

SEMI urges less bureaucratic approach to EU research funding

SEMI urges less bureaucratic approach to EU research funding: "San Jose-based manufacturing organization SEMI is advocating for a simplifica..."

Tuesday, October 5, 2010

The Nobel Prize in Physics 2010 (graphene)

The Royal Swedish Academy of Sciences has decided to award the Nobel Prize in Physics for 2010 to Andre Geim and Konstantin Novoselov, both at University of Manchester, UK “for groundbreaking experiments regarding the two-dimensional material graphene”.

Andre Geim, Dutch citizen. Born 1958 in Sochi, Russia. Ph.D. 1987 from Institute of Solid State Physics, Russian Academy of Sciences, Chernogolovka, Russia. Director of Manchester Centre for Meso-science & Nanotechnology, Langworthy Professor of Physics and Royal Society 2010 Anniversary Research Professor, University of Manchester, UK. 
Konstantin Novoselov, Brittish and Russian citizen. Born 1974 in Nizhny Tagil, Russia. Ph.D. 2004 from Radboud University Nijmegen, The Netherlands. Professor and Royal Society Research Fellow, University of Manchester, UK.

Read the press release...

AWR Announces New PDK for Cree GaN HEMT MMIC Foundry

The Cree GaN HEMT MMIC process features high power density (4-6 watts/mm) transistors, slot vias, and high reliability (up to 225ÂșC operating channel temperatures), as well as scalable transistors. [more]

Sunday, October 3, 2010

[mos-ak] MOS-AK/GSA Seville Workshop on-line Publications

MOS-AK/GSA Seville workshop on-line publications are available:

More that 50 registered participants followed 2 keynote invited
presentations, 7 technical compact modeling talks as well as 15 poster
presentation at the MOS-AK/GSA ESSEDERC/ESSCIRC Compact Modeling
Workshop. I would like to thank all MOS-AK/GSA speakers and poster
presenters for sharing their compact modeling competence, R&D
experience and delivering valuable MOS-AK/GSA presentations. I am
sure, that our modeling event in Seville was beneficial to all MOS-AK
Workshop attendees.

Please note that as a result of post workshop discussion, the Dolphin
Verilog-A Compact Model Coding Whitepaper is available for direct

Organization of our modeling event would not be possible without our
generous sponsors: Cascade Microtech and X-FAB Semiconductor Foundries
as well as the IEEE EDS, technical co-sponsor. I also would like to
personally acknowledge local ESSDERC/ESSCIRC organizers, in
particular, Professors Manuel Delgado Restituto, Andrés Godoy, the
ESSDERC/ESSCIRC Tutorials & Workshops Chairs for their dedication,
commitment. My very special 'thank you' goes also to Susana Eiroa for
her assistance and providing smooth workshop logistics.

I hope, we would have a next chance to meet us with your academic and
industrial partners at future MOS-AK/GSA modeling events (check the
list below).

- with regards - WG (for the MOS-AK/GSA Committee)
MOS-AK/Seville on-line publications <>
MOS-AK/California (Dec.2010; IEDM time frame)
IWCM at ASP-DAC in Yokohama Jan.2011 (with MOS-AK Support)
MOS-AK/Paris at LIP6 (March/April 2011)
MIXDES in Gliwice June 16-18, 2011 (with MOS-AK Session)
MOS-AK/Helsinki Sept.16, 2011 (ESSDERC time frame)

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Friday, October 1, 2010

CEA-Leti Makes a R&D 20nm Fully Depleted SOI Process available through CMP

Grenoble, FRANCE, and Tokyo, JAPAN, October 1st , 2010, CEA-Leti and CMP (Circuits Multi Projets®) announced during the FDSOI Workshop at Tokyo University the launch of an Exploratory MPW (Multi Project Wafers) initiative based on FDSOI (Fully Depleted SOI) 20nm process, opening the access of its 300mm infrastructure to the design community. This MPW offer is partly supported by EUROSOI+ network that gathers the main European academic partners on SOI.

The basis of the Fully Depleted SOI 20nm technology offer will be the following:
  • CMOS transistors with an undoped channel and a silicon film thickness of 6nm
  • High-k / Metal Gate stack
  • Single threshold voltage (Vth) n- and p-MOSFET with balanced Vth of ±0.4V
  • Associated Design Kit, including SPICE model (Verilog-A language), model cards extracted from silicon data, p-cells, DRC, LVS, schematic, parasitics
  • Design Kit documentation
CMP Press Contacts:
Bernard Courtois +33 4 76 57 46 15
Kholdoun Torki +33 4 76 57 47 63