Showing posts with label interface traps. Show all posts
Showing posts with label interface traps. Show all posts

Aug 30, 2021

Generalized EKV Compact MOSFET Model

On the Explicit Saturation Drain Current in the Generalized EKV Compact MOSFET Model
Francisco J. García-Sánchez, Life Senior Member, IEEE,
and Adelmo Ortiz-Conde, Senior Member, IEEE
IEEE TED Aug 9. 2021
DOI: 10.1109/TED.2021.3101186

*Solid State Electronics Laboratory, Universidad Simón Bolívar, Caracas 1080, Venezuela


Abstract: We present and discuss explicit closed-form expressions for the saturation drain current of short channel metal-oxide-semiconductorfield-effect transistors (MOSFETs) with gate oxide and interface-trapped charges, and including carrier velocity saturation, according to the generalized Enz-Krummenacher-Vittoz (EKV) MOSFET compact model. The normalized saturation drain current is derived as an explicit function of the normalized terminal voltages by solving the transcendental voltage versus charge equation using the Lambert W function. Because this special function is analytically differentiable, other important quantities, such as the transconductance and the transconductance-to-currentratio, can be readily expressed as explicit functions of the terminal voltages.
Fig: Comparison of simulated transfer characteristics with (red lines and symbols) and another without (black lines and symbols) radiation-induced oxide and interface-trapped charges. Calculation of VGB versus IDsat (lines) comes from denormalization and the explicit IDsat versus VGB (symbols) comes from denormalization of the proposed explicit expressions




Nov 20, 2020

[paper] Characterization of ultrathin FDSOI devices using subthreshold slope method

Teimuraz Mchedlidze1, and Elke Erben2
Characterization of ultrathin FDSOI devices using subthreshold slope method
Phys. Status Solidi A. Accepted Manuscript
DOI: 10.1002/pssa.202000625

1 TU Dresden, Germany
2 Globalfoundries, Dresden, Germany

Abstract: The subthreshold current-voltage (subthreshold slope) characteristic of fully depleted silicon-on-insulator high-k dielectric-metal gate field-effect transistor is applied for evaluation of the interface traps located at both, the front and back channels. The proposed characterization method allows an estimation of averaged trap densities separately for the front and the back interfaces of the channel. Performing subthreshold slope measurements at several temperatures allow the extraction of the energy distributions of the interface trap densities for both interfaces and obtaining essential characteristics of the stack.

Fig: Results of ID(VGF,k,T) measurements for EG sample. At each temperature 
(200, 300 and 400K) a group of curves contains data for eight k values
(k = 0 to 3 with step 0.5 and kOC; solid curve). 

Acknowledgements: The authors would like to acknowledge funding of the study in the frames of the IPCEI WIN- FDSOI project from Global Foundries. We want to thank Jörg Weber (TU Dresden), Luca Pirro (Global Foundries) and Rolf Öttking (AQ Computare, Chemnitz) for thoughtful discussions and suggestions.